MC14514B, MC14515B. 4-Bit Transparent Latch / 4-to-16 Line Decoder

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MC14514B, MC145B 4-Bit Traparent Latch / 4-to-16 Line Decoder The MC14514B and MC145B are two output optio of a 4 to 16 line decoder with latched inputs.

1 MC14514B, MC145B 4-Bit Traparent Latch / 4-to-16 Line Decoder The MC14514B and MC145B are two output optio of a 4 to 16 line decoder with latched inputs. The MC14514B (output active high option) presents a logical 1 at the selected output, whereas the MC145B (output active low option) presents a logical 0 at the selected output. The latches are RS type flipflops which hold the last input data presented prior to the strobe traition from 1 to 0. These high and low optio of a 4bit latch / 4 to 16 line decoder are cotructed with Nchannel and Pchannel enhancement mode devices in a single monolithic structure. The latches are RS type flipflops and data is admitted upon a signal incident at the strobe input, decoded, and presented at the output. These complementary circuits find primary use in decoding applicatio where low power dissipation and/or high noise immunity is desired. Features Supply Voltage Range = 3.0 to 18 Capable of Driving Two Lowpower TTL Loads or One Lowpower Schottky TTL Load the Rated Temperature Range These Devices are PbFree and are RoHS Compliant MAXIMUM RATINGS (Voltages Referenced to ) Parameter Symbol Value Unit DC Supply Voltage Range 0.5 to V Input or Output Voltage Range (DC or Traient) Input or Output Current (DC or Traient) per Pin V in, V out 0.5 to +0.5 I in, I out ± ma V MARKING DIAGRAM 24 1 SOIC24 DW SUFFIX CASE 751E MC145xxB AWLYYWWG xx = 14 or A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = PbFree Package PIN ASSIGNMENT Power Dissipation per Package (Note 1) P D 500 mw Ambient Temperature Range T A 55 to +125 C Storage Temperature Range T stg 65 to +0 C Lead Temperature (8Second Soldering) T L 260 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditio is not implied. Extended exposure to stresses above the Recommended Operating Conditio may affect device reliability. 1. Temperature Derating: Plastic P and D/DW Packages: 7.0 mw/ C From 65 C To 125 C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, V in and V out should be cotrained to the range (V in or V out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. ST S7 S6 S5 S4 S3 S1 S INH S S S8 S9 S14 S S12 S13 ORDERING INFORMATION See detailed ordering and shipping information in the package dimeio section on page 2 of this data sheet. Semiconductor Components Industries, LLC, 20 June, 20 Rev. 7 1 Publication Order Number: MC14514B/D

2 MC14514B, MC145B BLOCK DIAGRAM DECODE TRUTH TABLE (Strobe = 1)* DATA 1 DATA 2 DATA 3 DATA 4 STROBE INHIBIT = PIN 24 = PIN 12 TRANSPARENT LATCH 9 S1 S2 S3 8 S4 7 A 6 S5 5 S6 B S7 4 4 TO 16 C 18 DECODER S8 S9 17 D 20 S S S12 S13 S14 S Data Inputs Selected Output MC14514 = Logic 1 Inhibit D C B A MC145 = Logic S S S S S S S S S S S S S S S 1 X X X X All Outputs = 0, MC14514 All Outputs = 1, MC145 X = Don t Care *Strobe = 0, Data is latched ORDERING INFORMATION MC14514BDWR2G Device Package Shipping SOIC24 (PbFree) 00 / Tape & Reel MC145BDWR2G SOIC24 00 / Tape & Reel (PbFree) For information on tape and reel specificatio, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specificatio Brochure, BRD80/D. 2

3 MC14514B, MC145B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to ) Characteristic Output Voltage 0 Level V in = or 0 V in = 0 or 1 Level Input Voltage 0 Level (V O = 4.5 or 0.5 ) (V O = 9.0 or 1.0 ) (V O = 13.5 or 1.5 ) 1 Level (V O = 0.5 or 4.5 ) (V O = 1.0 or 9.0 ) (V O = 1.5 or 13.5 ) Output Drive Current (V OH = 2.5 ) Source (V OH = 4.6 ) (V OH = 9.5 ) (V OH = 13.5 ) (V OL = 0.4 ) Sink (V OL = 0.5 ) (V OL = 1.5 ) Symbol V OL V OH V IL V IH I OH I OL 55 C 25 C 125 C Min Max Min Typ (Note 2) Max Min Max Input Current I in ±0.1 ± ±0.1 ±1.0 Adc Input Capacitance (V in = 0) C in 7.5 pf uiescent Current (Per Package) I DD Total Supply Current (Note 3, 4) (Dynamic plus uiescent, Per Package) ( = 50 pf on all outputs, all buffers switching) I TL I T = (1.35 A/kHz) f + I DD I T = (2.70 A/kHz) f + I DD I T = (4.05 A/kHz) f + I DD 2. Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance. 3. The formulas given are for the typical characteristics only at 25 C. 4. To calculate total supply current at loads other than 50 pf: I T ( ) = I T (50 pf) + ( 50) Vfk where: I T is in A (per package), in pf, V = ( ) in volts, f in khz is input frequency, and k = Unit madc madc Adc Adc 3

4 MC14514B, MC145B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS (Note 5) ( = 50 pf, T A = 25 C) All Types Characteristic Symbol Min Typ (Note 6) Max Unit Output Rise Time t TLH = (3.0 /pf) + 30 t TLH = (1.5 /pf) + t TLH = (1.1 /pf) + t TLH Output Fall Time t THL = (1.5 /pf) + 25 t THL = (0.75 /pf) t THL = (0.55 /pf) t THL Propagation Delay Time; Data, Strobe to S t PLH, t PHL = (1.7 /pf) t PLH, t PHL = (0.86 /pf) t PLH, t PHL = (0.5 /pf) t PLH, t PHL Inhibit Propagation Delay Times t PLH, t PHL = (1.7 /pf) + 3 t PLH, t PHL = (0.66 /pf) + 7 t PLH, t PHL = (0.5 /pf) + 75 t PLH, t PHL su Hold Time Strobe to Data t h WH 5. The formulas given are for the typical characteristics only at 25 C. 6. Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance V DS For MC14514B 1. For Pchannel: Inhibit = 1. and cotitute 1. binary code for output 1. under test. 2. For Nchannel: Inhibit = STROBE INHIBIT S1 S2 S3 S4 S5 S6 S7 S8 S9 S S S12 S13 S14 S I D EXTERNAL POWER SUPPLY For MC145B 1. For Pchannel: Inhibit = 2. For Nchannel: Inhibit = 2. and cotitute binary 2. code for output under test. Figure 1. Drain Characteristics Test Circuit 4

5 MC14514B, MC145B PULSE GENERATOR I D 24 STROBE INHIBIT S 500 F 0.01 F CERAMIC V in % % 12 Figure 2. Dynamic Power Dissipation Test Circuit and Waveform PROGRAMMABLE PULSE GENERATOR STROBE INHIBIT S1 OUTPUT OUTPUT S1 INPUT OUTPUT t PLH % t TLH 90% 50% 20 90% 50% % t THL t PHL S OUTPUT S t TLH t THL Figure 3. Switching Time Test Circuit and Waveforms 5

6 MC14514B, MC145B DATA 1 2 DATA 2 3 DATA 3 21 DATA 4 22 STROBE 1 INHIBIT 23 S R S R S R S R A B C D LOGIC DIAGRAM IN MC145B ONLY ABC D A BCD A B CD A BCD ABC D A BCD A B CD A BCD 9 S1 S2 8 S3 7 S4 6 S5 5 S6 4 S7 18 S8 17 S9 20 S 19 S 14 S12 13 S13 16 S14 S 6

7 MC14514B, MC145B COMPLEX DATA ROUTING Two MC14512 eightchannel data selectors are used here with the MC14514B fourbit latch/decoder to effect a complex data routing system. A total of 16 inputs from data registers are selected and traferred via a 3state data bus to a data distributor for rearrangement and entry into 16 output registers. In this way sequential data can be rerouted or intermixed according to patter determined by data select and distribution inputs. Data is placed into the routing scheme via the eight inputs on both MC14512 data selectors. One register is assigned to each input. The signals on A0, A1, and A2 choose one of eight inputs for trafer out to the 3state data bus. A fourth signal, labelled Dis, disables one of the MC14512 selectors, assuring trafer of data from only one register. In addition to a choice of input registers, 1 thru 16, the rate of trafer of the sequential information can also be varied. That is, if the MC14512 were addressed at a rate that is eight times faster then the shift frequency of the input registers, the most significant bit (MSB) from each register could be selected for trafer to the data bus. Therefore, all of the most significant bits from all of the registers can be traferred to the data bus before the next most significant bit is presented for trafer by the input registers. Information from the 3state bus is redistributed by the MC14514B fourbit latch/decoder. Using the fourbit address, thru, the information on the inhibit line can be traferred to the addressed output line to the desired output registers, A thru P. This distribution of data bits to the output registers can be made in many complex patter. For example, all of the most significant bits from the input registers can be routed into output register A, all of the next most significant bits into register B, etc. In this way horizontal, vertical, or other methods of data slicing can be implemented. DATA ROUTING SYSTEM INPUT REGISTERS DATA TRANSFER 3-STATE DATA BUS DATA DISTRIBUTION OUTPUT REGISTERS DATA SELECT REGISTER 1 REGISTER 8 REGISTER 9 REGISTER 16 D0 D5 D6 DIS MC14512 D7 A0 A1 A2 A0 A1 A2 D0 D5 D6 D7 DIS MC14512 STROBE S1 S2 S3 S4 S5 S6 S7 S8 S9 S S S12 S13 INHIBIT S14 S MC14514B REGISTER A REGISTER P 7

8 MC14514B, MC145B PACKAGE DIMENSIONS SOIC24 CASE 751E04 ISSUE E A T SEATING PLANE B 12X 12 24X D 0.0 (0.25) M T A S B S C 22X G K P 0.0 (0.25) M B M J F M R X 45 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0. (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G 1.27 BSC 0 BSC J K M P R ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, coequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specificatio can and do vary in different applicatio and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any licee under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@oemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative MC14514B/D

MC14532B. 8-Bit Priority Encoder

MC14532B. 8-Bit Priority Encoder MC4532B 8-Bit Priority Encoder The MC4532B is cotructed with complementary MOS (CMOS) enhancement mode devices. The primary function of a priority encoder is to provide a binary address for the active