High Performance Silicon Gate CMOS

Transcription

1 High Performance Silicon Gate CMOS The MC74HC446A is similar in function to the MC446 Metal gate CMOS device. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC446A phase locked loop contains three phase comparators, a voltage controlled oscillator (CO) and unity gain op amp DEMOUT. The comparators have two common signal inputs, COMPIN, and SIGIN. Input SIGIN and COMPIN can be used directly coupled to large voltage signals, or indirectly coupled (with a series capacitor to small voltage signals). The self bias circuit adjusts small voltage signals in the linear region of the amplifier. Phase comparator (an exclusive OR gate) provides a digital error signal PCOUT and maintains 9 degrees phase shift at the center frequency between SIGIN and COMPIN signals (both at 5% duty cycle). Phase comparator 2 (with leading edge sensing logic) provides digital error signals PC2OUT and PCPOUT and maintains a degree phase shift between SIGIN and COMPIN signals (duty cycle is immaterial). The linear CO produces an output signal COOUT whose frequency is determined by the voltage of input COIN signal and the capacitor and resistors connected to pins CA, CB, R and R2. The unity gain op amp output DEMOUT with an external resistor is used where the COIN signal is needed but no loading can be tolerated. The inhibit input, when high, disables the CO and all op amps to minimize standby power consumption. Applications include FM and FSK modulation and demodulation, frequency synthesis and multiplication, frequency discrimination, tone decoding, data synchronization and conditioning, voltage to frequency conversion and motor speed control. Output Drive Capability: LSTTL Loads Low Power Consumption Characteristic of CMOS Devices Operating Speeds Similar to LSTTL Wide Operating oltage Range: to Low Input Current:. µa Maximum (except SIGIN and COMPIN) In Compliance with the Requirements Defined by JEDEC Standard No. 7A Low Quiescent Current: 8 µa Maximum (CO disabled) High Noise Immunity Characteristic of CMOS Devices Diode Protection on all Inputs Chip Complexity: 279 FETs or 7 Equivalent Gates PDIP N SUFFIX CASE 648 SO D SUFFIX CASE 75B TSSOP DT SUFFIX CASE 948F SOEIAJ F SUFFIX CASE 966 MARKING DIAGRAMS MC74HC446AN AWLYYWW A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week ORDERING INFORMATION HC446A AWLYWW HC4 46A ALYW Device Package Shipping MC74HC446AN PDIP 2 / Box MC74HC446AD SOIC 48 / Rail MC74HC446ADR2 SOIC 25 / Reel 74HC446B AWLYWW MC74HC446AF SOIC EIAJ See Note MC74HC446AFEL SOIC EIAJ NO TAG See Note NO TAG. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative. Semiconductor Components Industries, LLC, 2 March, 2 Rev. 7 Publication Order Number: MC74HC446A/D

2 Pin No. Symbol Name and Function PCPOUT PCOUT COMPIN COOUT INH CA CB COIN DEMOUT R R2 PC2OUT SIGIN PC3OUT Phase Comparator Pulse Output Phase Comparator Output Comparator Input CO Output Inhibit Input Capacitor C Connection A Capacitor C Connection B Ground ( ) SS CO Input Demodulator Output Resistor R Connection Resistor R2 Connection Phase Comparator 2 Output Signal Input Phase Comparator 3 Output Positive Supply oltage PIN ASSIGNMENT PCPout PCout 2 5 PC3out COMPin 3 4 SIGin COout 4 3 PC2out INH 5 2 R2 CA 6 R CB 7 DEMout 8 9 COin MAXIMUM RATINGS* ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ Symbol Parameter alue Unit ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ DC Supply oltage (Referenced to ).5 to + 7. ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ in DC Input oltage (Referenced to ).5 to +.5 ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ out DC Output oltage (Referenced to ).5 to +.5 ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Iin DC Input Current, per Pin ± 2 ma ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Iout DC Output Current, per Pin ± 25 ma ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ICC DC Supply Current, and Pins ± 5 ma ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ PD Power Dissipation in Still Air Plastic DIP 75 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SOIC Package ÎÎÎÎÎ 5 ÎÎÎ mw ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Tstg Storage Temperature ÎÎÎÎÎ 65 to + 5ÎÎÎ C ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ TL Lead Temperature, mm from Case for Seconds ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Plastic DIP and SOIC Package ÎÎÎÎÎ 26 ÎÎÎ C *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating Plastic DIP: mw/ C from 65 to 25 C SOIC Package: 7 mw/ C from 65 to 25 C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D). RECOMMENDED OPERATING CONDITIONS ÎÎÎÎ Symbol ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Parameter ÎÎÎ Min ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Supply oltage (Referenced to ) ÎÎÎ ÎÎ Max ÎÎÎ Unit ÎÎÎ DC Supply oltage (Referenced to ) NON CO DC Input oltage, Output oltage (Referenced to ) ÎÎÎ ÎÎ TA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Operating Temperature, All Package Types ÎÎÎ 55 ÎÎ C tr, tf ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Input Rise and Fall Time = ÎÎÎ ÎÎ ns (Pin 5) = 5 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ = ÎÎÎ ÎÎ 4 ÎÎÎÎ in, outîîîîîîîîîîîîîîî ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ CCÎÎÎ + 25ÎÎÎ ÎÎÎ ÎÎÎ This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be constrained to the range (in or out). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. 2

3 [Phase Comparator Section] DC ELECTRICAL CHARACTERISTICS (oltages Referenced to ) Symbol Parameter Test Conditions IH IL OH Minimum High Level Input oltage DC Coupled SIGIN, COMPIN Maximum Low Level Input oltage DC Coupled SIGIN, COMPIN Minimum High Level Output oltage PCPOUT, PCnOUT out = or Iout 2 µa out = or Iout 2 µa in = IH or IL Iout 2 µa olts Guaranteed Limit 55 to 25 C 85 C 25 C Unit in = IH or IL Iout 4. ma Iout 5.2 ma (continued) [Phase Comparator Section] DC ELECTRICAL CHARACTERISTICS continued (oltages Referenced to ) Symbol Parameter Test Conditions OL Maximum Low Level Output oltage Qa Qh PCPOUT, PCnOUT out = or Iout 2 µa olts Guaranteed Limit 55 to 25 C 85 C 25 C Unit Iin IOZ ICC Maximum Input Leakage Current SIGIN, COMPIN Maximum Three State Leakage Current PC2OUT Maximum Quiescent Supply Current (per Package) (CO disabled) Pins 3, 5 and 4 at Pin 9 at ; Input Leakage at Pins 3 and 4 to be excluded in = IH or IL Iout 4. ma Iout 5.2 ma in = or Output in High Impedance State in = IH or IL out = or in = or Iout = µa ± ± 7. ± 8. ± ± 4. ± 9. ± 2 ± ± 5. ±. ± 27. ± 45. µa ±.5 ± 5. ± µa 4. 4 µa NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D). [Phase Comparator Section] AC ELECTRICAL CHARACTERISTICS (CL = 5 pf, Input tr = tf = ns) Symbol tplh, tphl tplh, tphl Parameter Maximum Propagation Delay, SIGIN/COMPIN to PCOUT (Figure ) Maximum Propagation Delay, SIGIN/COMPIN to PCPOUT (Figure ) Guaranteed Limit olts 55 to 25 C 85 C 25 C Unit ns ns 3

4 [Phase Comparator Section] AC ELECTRICAL CHARACTERISTICS (CL = 5 pf, Input tr = tf = ns) tplh, tphl tplz, tphz tpzh, tpzl ttlh, tthl Maximum Propagation Delay, SIGIN/COMPIN to PC3OUT (Figure ) Maximum Propagation Delay, SIGIN/COMPIN Output Disable Time to PC2OUT (Figures 2 and 3) Maximum Propagation Delay, SIGIN/COMPIN Output Enable Time to PC2OUT (Figures 2 and 3) Maximum Output Transition Time (Figure ) [CO Section] DC ELECTRICAL CHARACTERISTICS (oltages Referenced to ) Symbol Parameter Test Conditions IH IL OH Minimum High Level Input oltage INH Maximum Low Level Input oltage INH Minimum High Level Output oltage COOUT out = or Iout 2 µa out = or Iout 2 µa in =IH or IL Iout 2 µa olts Guaranteed Limit to 25 C 85 C 25 C Unit ns ns ns ns in =IH or IL Iout 4. ma Iout 5.2 ma OL Maximum Low Level Output oltage COOUT out = or Iout 2 µa Iin COIN Maximum Input Leakage Current INH, COIN Operating oltage Range at COIN over the range specified for R; For linearity see Fig. 5A, Parallel value of R and R2 should be > 2.7 kω in =IH or IL Iout 4. ma Iout 5.2 ma in = or.. µa INH = IL R Resistor Range R2 C Capacitor Range.4.4 Min Max Min Max Min Max No Limit kω pf 4

5 [CO Section] AC ELECTRICAL CHARACTERISTICS (CL = 5 pf, Input tr = tf = ns) Guaranteed Limit Symbol f/t fo Frequency Stability with Temperature Changes (Figure 3A, B, C) CO Center Frequency (Duty Factor = 5%) (Figure 4A, B, C, D) Parameter 55 to 25 C 85 C 25 C olts Min Max Min Max Min Max Unit fco CO Frequency Linearity CO Duty Factor at COOUT 3 3 %/K MHz See Figures 5A, B, C % Typical 5% % [Demodulator Section] DC ELECTRICAL CHARACTERISTICS Guaranteed Limit Symbol Parameter Test Conditions RS Resistor Range At RS > kω the Leakage Current can Influence DEMOUT OFF RD Offset oltage COIN to DEMOUT Dynamic Output Resistance at DEMOUT i = COIN = /2 ; alues taken over RS Range. 55 to 25 C 85 C 25 C olts Min Max Min Max Min Max Unit DEMOUT = / See Figure 2 Typical 25 Ω kω m Ω 5

6 SWITCHING WAEFORMS SIGIN, COMPIN INPUTS 5% SIGIN INPUT 5% PCPOUT, PCOUT PC3OUT OUTPUTS tthl tphl 9% 5% % tplh ttlh COMPIN INPUT PC2OUT OUTPUT tpzh 5% 5% tphz 9% OH HIGH IMPEDANCE Figure. Figure 2. SIGIN INPUT COMPIN INPUT PC2OUT OUTPUT 5% tpzl 5% 5% tplz % HIGH IMPEDANCE OL DEICE UNDER TEST OUTPUT TEST POINT CL* *INCLUDES ALL PROBE AND JIG CAPACITANCE Figure 3. Figure 4. Test Circuit 6

7 DETAILED CIRCUIT DESCRIPTION oltage Controlled Oscillator/Demodulator Output The CO requires two or three external components to operate. These are R, R2, C. Resistor R and Capacitor C are selected to determine the center frequency of the CO (see typical performance curves Figure 4). R2 can be used to set the offset frequency with volts at CO input. For example, if R2 is decreased, the offset frequency is increased. If R2 is omitted the CO range is from Hz. The effect of R2 is shown in Figure 24, typical performance curves. By increasing the value of R2 the lock range of the PLL is increased and the gain (volts/hz) is decreased. Thus, for a narrow lock range, large swings on the CO input will cause less frequency variation. Internally, the resistors set a current in a current mirror, as shown in Figure 5. The mirrored current drives one side of the capacitor. Once the voltage across the capacitor charges up to ref of the comparators, the oscillator logic flips the capacitor which causes the mirror to charge the opposite side of the capacitor. The output from the internal logic is then taken to CO output (Pin 4). The input to the CO is a very high impedance CMOS input and thus will not load down the loop filter, easing the filters design. In order to make signals at the CO input accessible without degrading the loop performance, the CO input voltage is buffered through a unity gain Op amp to Demod Output. This Op amp can drive loads of 5K ohms or more and provides no loading effects to the CO input voltage (see Figure 2). An inhibit input is provided to allow disabling of the CO and all Op amps (see Figure 5). This is useful if the internal CO is not being used. A logic high on inhibit disables the CO and all Op amps, minimizing standby power consumption. 2 REF + _ I R2 CURRENT MIRROR I + I2 = I3 COIN 9 + _ I2 4 COOUT R I3 DEMODOUT + _ C (EXTERNAL) 6 7 ref + + INH 5 Figure 5. Logic Diagram for CO The output of the CO is a standard high speed CMOS output with an equivalent LS TTL fan out of. The CO output is approximately a square wave. This output can either directly feed the COMPIN of the phase comparators or feed external prescalers (counters) to enable frequency synthesis. 7

8 Phase Comparators All three phase comparators have two inputs, SIGIN and COMPIN. The SIGIN and COMPIN have a special DC bias network that enables AC coupling of input signals. If the signals are not AC coupled, standard 74HC input levels are required. Both input structures are shown in Figure 6. The outputs of these comparators are essentially standard 74HC outputs (comparator 2 is TRI STATEABLE). In normal operation and ground voltage levels are fed to the loop filter. This differs from some phase detectors which supply a current to the loop filter and should be considered in the design. (The MC446 also provides a voltage). SIGIN 4 PC2OUT 3 COMPIN 3 PCPOUT PC3OUT 5 PCOUT 2 Figure 6. Logic Diagram for Phase Comparators Phase Comparator This comparator is a simple XOR gate similar to the 74HC86. Its operation is similar to an overdriven balanced modulator. To maximize lock range the input frequencies must have a 5% duty cycle. Typical input and output waveforms are shown in Figure 7. The output of the phase detector feeds the loop filter which averages the output voltage. The frequency range upon which the PLL will lock onto if initially out of lock is defined as the capture range. The capture range for phase detector is dependent on the loop filter design. The capture range can be as large as the lock range, which is equal to the CO frequency range. To see how the detector operates, refer to Figure 7. When two square wave signals are applied to this comparator, an output waveform (whose duty cycle is dependent on the phase difference between the two signals) results. As the phase difference increases, the output duty cycle increases and the voltage after the loop filter increases. In order to achieve lock when the PLL input frequency increases, the CO input voltage must increase and the phase difference between COMPIN and SIGIN will increase. At an input frequency equal to fmin, the CO input is at. This requires the phase detector output to be grounded; hence, the two input signals must be in phase. When the input frequency is fmax, the CO input must be and the phase detector inputs must be 8 degrees out of phase. SIGIN COMPIN PCOUT COIN Figure 7. Typical Waveforms for PLL Using Phase Comparator The XOR is more susceptible to locking onto harmonics of the SIGIN than the digital phase detector 2. For instance, a signal 2 times the CO frequency results in the same output duty cycle as a signal equal to the CO frequency. The difference is that the output frequency of the 2f example is twice that of the other example. The loop filter and CO range should be designed to prevent locking on to harmonics. 8

9 Phase Comparator 2 This detector is a digital memory network. It consists of four flip flops and some gating logic, a three state output and a phase pulse output as shown in Figure 6. This comparator acts only on the positive edges of the input signals and is independent of duty cycle. Phase comparator 2 operates in such a way as to force the PLL into lock with phase difference between the CO output and the signal input positive waveform edges. Figure 8 shows some typical loop waveforms. First assume that SIGIN is leading the COMPIN. This means that the CO s frequency must be increased to bring its leading edge into proper phase alignment. Thus the phase detector 2 output is set high. This will cause the loop filter to charge up the CO input, increasing the CO frequency. Once the leading edge of the COMPIN is detected, the output goes TRI STATE holding the CO input at the loop filter voltage. If the CO still lags the SIGIN then the phase detector will again charge up the CO input for the time between the leading edges of both waveforms. If the CO leads the SIGIN then when the leading edge of the CO is seen; the output of the phase comparator goes low. This discharges the loop filter until the leading edge of the SIGIN is detected at which time the output disables itself again. This has the effect of slowing down the CO to again make the rising edges of both waveforms coincidental. When the PLL is out of lock, the CO will be running either slower or faster than the SIGIN. If it is running slower the phase detector will see more SIGIN rising edges and so the output of the phase comparator will be high a majority of the time, raising the CO s frequency. Conversely, if the CO is running faster than the SIGIN, the output of the detector will be low most of the time and the CO s output frequency will be decreased. As one can see, when the PLL is locked, the output of phase comparator 2 will be disabled except for minor corrections at the leading edge of the waveforms. When PC2 is TRI STATED, the PCP output is high. This output can be used to determine when the PLL is in the locked condition. This detector has several interesting characteristics. Over the entire CO frequency range there is no phase difference between the COMPIN and the SIGIN. The lock range of the PLL is the same as the capture range. Minimal power was consumed in the loop filter since in lock the detector output is a high impedance. When no SIGIN is present, the detector will see only CO leading edges, so the comparator output will stay low, forcing the CO to fmin. Phase comparator 2 is more susceptible to noise, causing the PLL to unlock. If a noise pulse is seen on the SIGIN, the comparator treats it as another positive edge of the SIGIN and will cause the output to go high until the CO leading edge is seen, potentially for an entire SIGIN period. This would cause the CO to speed up during that time. When using PC, the output of that phase detector would be disturbed for only the short duration of the noise spike and would cause less upset. Phase Comparator 3 This is a positive edge triggered sequential phase detector using an RS flip flop as shown in Figure 6. When the PLL is using this comparator, the loop is controlled by positive signal transitions and the duty factors of SIGIN and COMPIN are not important. It has some similar characteristics to the edge sensitive comparator. To see how this detector works, assume input pulses are applied to the SIGIN and COMPIN s as shown in Figure 9. When the SIGIN leads the COMPIN, the flop is set. This will charge the loop filter and cause the CO to speed up, bringing the comparator into phase with the SIGIN. The phase angle between SIGIN and COMPIN varies from to 36 and is 8 at fo. The voltage swing for PC3 is greater than for PC2 but consequently has more ripple in the signal to the CO. When no SIGIN is present the CO will be forced to fmax as opposed to fmin when PC2 is used. The operating characteristics of all three phase comparators should be compared to the requirements of the system design and the appropriate one should be used. SIGIN COMPIN PC2OUT COIN PCPOUT SIGIN COMPIN PC3OUT COIN HIGH IMPEDANCE OFF STATE Figure 8. Typical Waveforms for PLL Using Phase Comparator 2 Figure 9. Typical Waveform for PLL Using Phase Comparator 3 9

10 8 = 4. = = = R I = (k Ω ) 4 = I I ( µ A) = /2. /2 I () / /2 CC 5 m /2 /2 + 5 m I () Figure. Input Resistance at SIGIN, COMPIN with I =. at Self Bias Point Figure. Input Current at SIGIN, COMPIN with I = 5 m at Self Bias Point DEM OUT DEMOD OUT = RS= k = RS=5 k = RS= k = RS=5 k = RS= k = RS=5 k COIN () Figure 2. Offset oltage at Demodulator Output as a Function of COIN and RS FREQUENCY STABILITY (%) R= kω R= kω R= kω R= kω R= kω = R= kω C = pf; R2 = ; COIN=/ AMBIENT TEMPERATURE ( C) Figure 3A. Frequency Stability versus Ambient Temperature: = FREQUENCY STABILITY (%) R= kω R= kω = C = pf; R2 = ; COIN = / AMBIENT TEMPERATURE ( C) R= kω FREQUENCY STABILITY (%) R= kω R= kω R= kω = 8. C = pf; R2 = ; COIN=/ AMBIENT TEMPERATURE ( C) Figure 3B. Frequency Stability versus Ambient Temperature: = Figure 3C. Frequency Stability versus Ambient Temperature: =

11 f CO (MHz) = = = R = kω C = 39 pf COIN () f CO (KHz) = = = R = kω C = µf COIN () Figure 4A. CO Frequency (fco) as a Function of the CO Input oltage (COIN) Figure 4B. CO Frequency (fco) as a Function of the CO Input oltage (COIN) f CO (MHz). =.9 = =.8 = =.7.6 = R = kω.2 R = kω C = 39 pf C = µf COIN () COIN () f CO (KHz) Figure 4C. CO Frequency (fco) as a Function of the CO Input oltage (COIN) Figure 4D. CO Frequency (fco) as a Function of the CO Input oltage (COIN) = f CO (%). C =. µf f2 f f f. C = 39 pf R2 = ; = R (kω) Figure 5A. Frequency Linearity versus R, C and MIN /2 MAX =.5 OER THE RANGE: FOR CO LINEARITY f = (f + f2) / 2 LINEARITY = (f f) / f ) x % Figure 5B. Definition of CO Frequency Linearity

12 6 C L = 5 pf; R2 = ; COIN = /2 CC FOR CC = AND ; COIN = /3 CC FOR CC = ; T amb =25 C 6 C L = 5 pf; R = ; COIN =; T amb =25 C PR (µ W) CC =, C = 4 pf CC =, C =. µf CC =, C = 4 pf CC =, C =. µf CC =, C = 4 pf CC =, C =. µf 2 3 R (kω) PR2 (µ W) 5 4 CC =, C = 4 pf CC =, C =. µf CC =, C = 4 pf CC =, C =. µf 3 CC =, C =. µf CC =, C = 4 pf R2 (kω) 2 3 Figure. Power Dissipation versus R Figure 7. Power Dissipation versus R2 P DEM ( µ W) 3 2 R = R2 = ; T amb =25 C CC = CC = f CO (Hz) CC = INH = ; T amb =25 C; R2 = ; COIN = /3 CC R= kω CC = 2 3 RS (kω) Figure 8. DC Power Dissipation of Demodulator versus RS 3 2 R= kω R= kω C (pf) Figure 9. CO Center Frequency versus C f off (Hz) CC = R = ; COIN = /2 CC FOR CC = AND ; COIN = /3 CC FOR CC = ; INH = ; T amb =25 C R2= kω 2fL (Hz) = ; R2 = 3 2 R2= kω R2= kω C (pf) Figure 2. Frequency Offset versus C RC Figure 2. Typical Frequency Lock Range (2fL) versus RC 2

13 FREQ. (MHz) 2 R= kω R= kω 5 R=2 kω R=3 kω R=4 kω R=5 kω 5. R= kω C=39 pf R= kω R2 ( kω) Figure 22. R2 versus fmax FREQ. (MHz) R2 ( kω) Figure 23. R2 versus fmin C=39 pf R=3 kω R= kω R=2 kω R=3 kω R=4 kω R=5 kω R= kω R= kω 2 C=39 pf L(MHz) 2f R= kω R= kω R=2 kω R=3 kω R=4 kω R=5 kω R= kω R2 ( kω) R= kω Figure 24. R2 versus Frequency Lock Range (2fL) 3

14 APPLICATION INFORMATION The following information is a guide for approximate values of R, R2, and C. Figures 9, 2, and 2 should be used as references as indicated below, also the values of R, R2, and C should not violate the Maximum values indicated in the DC ELECTRICAL CHARACTERISTICS tables. Phase Comparator Phase Comparator 2 Phase Comparator 3 R2 = R2 R2 = R2 R2 = R2 Given f Use f with Figure 9 to determine R and C. (see Figure 23 for characteristics of the CO operation) Given f and fl Calculate fmin fmin = f fl Determine values of C and R2 from Figure 2. Determine R C from Figure 2. Calculate value of R from the value of C and the product of RC from Figure 2. (see Figure 24 for characteristics of the CO operation) Given fmax and f Determine the value of R and C using Figure 9 and use Figure 2 to obtain 2fL and then use this to calculate fmin. Given f and fl Calculate fmin fmin = f fl Determine values of C and R2 from Figure 2. Determine R C from Figure 2. Calculate value of R from the value of C and the product of RC from Figure 2. (see Figure 24 for characteristics of the CO operation) Given fmax and f Determine the value of R and C using Figure 9 and Figure 2 to obtain 2fL and then use this to calculate fmin. Given f and fl Calculate fmin: fmin = f fl Determine values of C and R2 from Figure 2. Determine R C from Figure 2. Calculate value of R from the value of C and the product of RC from Figure 2. (see Figure 24 for characteristics of the CO operation) PACKAGE DIMENSIONS PDIP N SUFFIX CASE ISSUE R A 8 9 B NOTES:. DIMENSIONING AND TOLERANCING PER ANSI YM, CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. H G F S C K T SEATING PLANE D PL.25 (.) M T A M J L M DIM A B C D F G H J K L M S INCHES MIN MAX BSC.5 BSC MILLIMETERS MIN MAX BSC.27 BSC

15 PACKAGE DIMENSIONS SOIC D SUFFIX CASE 75B 5 ISSUE J T SEATING PLANE A 8 G D PL 9 K B C P 8 PL.25 (.) M T B S A S.25 (.) M B M M R X 45 J F NOTES:. DIMENSIONING AND TOLERANCING PER ANSI YM, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 5 (.6) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 27 (.5) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX INCHES MIN MAX BSC.5 BSC (.6) T 5 (.6) T (.4) T SEATING PLANE L U PIN IDENT. U D S S 2X L/2 C X K REF 9 8 A G TSSOP DT SUFFIX CASE 948F ISSUE O (.4) M T U S S B U H N N J J F DETAIL E DETAIL E K K ÇÇÇ ÇÇÇ ÉÉÉ SECTION N N.25 (.) M W NOTES:. DIMENSIONING AND TOLERANCING PER ANSI YM, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 5 (.6) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED.25 (.) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE.8 (.3) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C.2.47 D F G.65 BSC.26 BSC H J J K K L 6.4 BSC.252 BSC M 8 8 5

16 PACKAGE DIMENSIONS e 9 Z b D A HE A 3 (.5) M (.4) 8 E SOEIAJ F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 966 ISSUE O IEW P M LE L DETAIL P Q c NOTES:. DIMENSIONING AND TOLERANCING PER ANSI YM, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 5 (.6) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE.8 (.3) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE.46 (.8). MILLIMETERS INCHES DIM MIN MAX MIN MAX A 5.8 A b c D E e.27 BSC.5 BSC H E L L E M Q Z.78.3 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 53, Denver, Colorado 827 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada ONlit@hibbertco.com Fax Response Line: or Toll Free USA/Canada N. American Technical Support: Toll Free USA/Canada EUROPE: LDC for ON Semiconductor European Support German Phone: (+) (M F :pm to 5:pm Munich Time) ONlit german@hibbertco.com French Phone: (+) (M F :pm to 5:pm Toulouse Time) ONlit french@hibbertco.com English Phone: (+) (M F 2:pm to 5:pm UK Time) ONlit@hibbertco.com EUROPEAN TOLL FREE ACCESS*: *Available from Germany, France, Italy, England, Ireland CENTRAL/SOUTH AMERICA: Spanish Phone: (Mon Fri 8:am to 5:pm MST) ONlit spanish@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor Asia Support Phone: (Tue Fri 9:am to :pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: ONlit asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4 32 Nishi Gotanda, Shinagawa ku, Tokyo, Japan Phone: r4525@onsemi.com ON Semiconductor Website: For additional information, please contact your local Sales Representative. MC74HC446A/D