MM74HC00 Quad 2-Input NAND Gate

Transcription

1 MM74HC00 Quad 2-Input NAND Gate Features Typical propagation delay: 8 Wide power supply range: 2 6 Low quiescent current: 20µA maximum (74HC Series) Low input current: 1µA maximum Fanout of 10 LS-TTL loads General Description February 2008 The MM74HC00 NAND gates utilize advanced silicongate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power coumption of standard CMOS integrated circuits. All gates have buffered outputs. All devices have high noise immunity and the ability to drive 10 LS-TTL loads. The 74HC logic family is functionally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to CC and ground. MM74HC00 Quad 2-Input NAND Gate Ordering Information Order Number Package Number Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. Package Description MM74HC00M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC00SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC00MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC00N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Connection Diagram Logic Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP Top iew 1983 Fairchild Semiconductor Corporation MM74HC00 Rev

2 Absolute Maximum Ratings (1) Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditio and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditio may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Rating CC Supply oltage 0.5 to +7.0 IN DC Input oltage 1.5 to CC +1.5 OUT DC Output oltage 0.5 to CC +0.5 I IK, I OK Clamp Diode Current ±20mA I OUT DC Output Current, per pin ±25mA I CC DC CC or GND Current, per pin ±50mA T STG Storage Temperature Range 65 C to +150 C P D Power Dissipation Note 2 600mW S.O. Package only 500mW T L Lead Temperature (Soldering 10 seconds) 260 C MM74HC00 Quad 2-Input NAND Gate Notes: 1. Unless otherwise specified all voltages are referenced to ground. 2. Power Dissipation temperature derating plastic N package: 12mW/ C from 65 C to 85 C. Recommended Operating Conditio The Recommended Operating Conditio table defines the conditio for actual device operation. Recommended operating conditio are specified to eure optimal performance to the datasheet specificatio. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter Min. Max. Units CC Supply oltage 2 6 IN, OUT DC Input or Output oltage 0 CC T A Operating Temperature Range C t r, t f Input Rise or Fall Times CC = CC = CC = Fairchild Semiconductor Corporation MM74HC00 Rev

3 DC Electrical Characteristics (3) Symbol Parameter CC () Conditio IH IL OH OL I IN I CC Minimum HIGH Level Input oltage Maximum LOW Level Input oltage Minimum HIGH Level Output oltage Maximum LOW Level Output oltage Maximum Input Current Maximum Quiescent Supply Current T A = 25 C T A = 40 C to 85 C T A = 55 C to 125 C Units Note: 3. For a power supply of 5 ±10% the worst case output voltages ( OH, and OL ) occur for HC at 4.5. Thus the 4.5 values should be used when designing with this supply. Worst case IH and IL occur at CC = 5.5 and 4.5 respectively. (The IH value at 5.5 is 3.85.) The worst case leakage current (I IN, I CC, and I OZ ) occur for CMOS at the higher voltage and so the 6.0 values should be used. Typ. Guaranteed Limits IN = IH or IL, I OUT 20µA IN = IH or IL, I OUT 4.0mA 6.0 IN = IH or IL, I OUT 5.2mA IN = IH, I OUT 20µA IN = IH, I OUT 4.0mA 6.0 IN = IH, I OUT 5.2mA IN = CC or GND ±0.1 ±1.0 ±1.0 µa 6.0 IN = CC or GND, I OUT = 0µA µa MM74HC00 Quad 2-Input NAND Gate 1983 Fairchild Semiconductor Corporation MM74HC00 Rev

4 AC Electrical Characteristics CC = 5, T A = 25 C, C L = 15pF, t r = t f = 6 Symbol Parameter Conditio Typ. AC Electrical Characteristics CC = 2.0 to 6.0, C L = 50pF, t r = t f = 6 (unless otherwise specified) Guaranteed Limit t PHL, t PLH Maximum Propagation Delay 8 15 Symbol Parameter CC () Conditio t PHL, t PLH t TLH, t THL C PD C IN Maximum Propagation Delay Maximum Output Rise and Fall Time T A = 25 C Typ. T A = 40 C to 85 C Guaranteed Limits T A = 55 C to 125 C Units Units Power Dissipation Capacitance (4) (per gate) 20 pf Maximum Input pf Capacitance MM74HC00 Quad 2-Input NAND Gate Note: 4. C PD determines the no load dynamic power coumption, P D = C PD CC 2 f + I CC CC, and the no load dynamic current coumption, I S = C PD CC f + I CC Fairchild Semiconductor Corporation MM74HC00 Rev

5 M54HC02 M74HC02 QUAD 2-INPUT NOR GATE. HIGH SPEED tpd = 6 (TYP.) AT CC =5.LOW POWER DISSIPATION I CC =1µA (MAX.) AT T A =25 C.HIGH NOISE IMMUNITY NIH =NIL =28%CC (MIN.) OUTPUT DRIE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH =IOL = 4 ma (MIN.) BALANCED PROPAGATION DELAYS t PLH =t. PHL WIDE OPERATING OLTAGE RANGE CC (OPR) = 2 TO 6 PIN AND FUNCTION COMPATIBLE WITH 54/74LS02 B1R (Plastic Package) M1R (Micro Package) F1R (Ceramic Package) C1R (Chip Carrier) ORDER CODES : M54HC02F1R M74HC02M1R M74HC02B1R M74HC02C1R DESCRIPTION The M54/74HC02 is a high speed CMOS QUAD 2- INPUT NOR GATEfabricated in silicongate C 2 MOS technology. It has the same high speed performance of LSTTL combined with true CMOSlow power coumption. The internal circuit is composed of 3 stages including buffer output, which gives high noise immunity and stable output. All inputs are equipped with protection circuits agait static discharge and traient excess voltage. PIN CONNECTIONS (top view) INPUT AND OUTPUT EQUIALENT CIRCUIT NC = No Internal Connection December /9

6 M54/M74HC02 TRUTH TABLE IEC LOGIC SYMBOL A B Y L L H L H L H L L H H L PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 2, 5, 8, 11 1A to 4A Data Inputs 3, 6, 9, 12 1B to 4B Data Inputs 1, 4, 10, 12 1Y to 4Y Data Outputs 7 GND Ground (0) 14 CC Positive Supply oltage SCHEMATIC CIRCUIT (Per Gate) ABSOLUTE MAXIMUM RATINGS Symbol Parameter alue Unit CC Supply oltage -0.5 to +7 I DC Input oltage -0.5 to CC O DC Output oltage -0.5 to CC I IK DC Input Diode Current ± 20 ma I OK DC Output Diode Current ± 20 ma IO DC Output Source Sink Current Per Output Pin ± 25 ma I CC or I GND DC CC or Ground Current ± 50 ma P D Power Dissipation 500 (*) mw Tstg Storage Temperature -65 to +150 o C T L Lead Temperature (10 sec) 300 o C Absolute MaximumRatings are those values beyond whichdamage tothe device may occur. Functional operation under these condition isnotimplied. (*) 500 mw: 65 o C derate to 300 mw by 10mW/ o C: 65 o Cto85 o C 2/9

7 M54/M74HC02 RECOMMENDED OPERATING CONDITIONS Symbol Parameter alue Unit CC Supply oltage 2 to 6 I Input oltage 0 to CC O Output oltage 0 to CC Top Operating Temperature: M54HC Series -55 to +125 M74HC Series -40 to +85 o C C t r,t f Input Rise and Fall Time CC = 2 0 to 1000 CC = to 500 CC = 6 0 to 400 DC SPECIFICATIONS Symbol IH IL OH OL II ICC Parameter High Level Input oltage Low Level Input oltage High Level Output oltage Low Level Output oltage Input Leakage Current Quiescent Supply Current CC () Test Conditio TA =25 o C 54HC and 74HC alue -40 to 85 o C 74HC -55 to 125 o C 54HC Min. Typ. Max. Min. Max. Min. Max I = 4.5 I O =-20 µa IH or IL I O =-4.0 ma I O =-5.2 ma I = 4.5 IO= 20µA IH 6.0 or IL IO= 4.0 ma I O = 5.2 ma I =CC or GND ±0.1 ±1 ±1 µa 6.0 I = CC or GND µa Unit 3/9

8 M54/M74HC02 AC ELECTRICAL CHARACTERISTICS (CL =50pF,Inputtr=tf=6) Symbol t TLH t THL Parameter Output Traition Time CC () Test Conditio TA =25 o C 54HC and 74HC alue -40 to 85 o C 74HC -55 to 125 o C 54HC Min. Typ. Max. Min. Max. Min. Max t PLH Propagation t PHL Delay Time CIN Input Capacitance pf CPD (*) Power Dissipation 21 Capacitance pf (*) CPD is defined as the value of the IC s internal equivalent capacitance which is calculated from the operating current coumption without load. (Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD CC fin + ICC/4 (per Gate) Unit SWITCHING CHARACTERISTICS TEST CIRCUIT TEST CIRCUIT I CC (Opr.) INPUT WAEFORM IS THE SAME AS THAT IN CASE OF SWITCHING CHARACTERISTICS TEST. 4/9

9 M54HC164 M74HC164 8 BIT SIPO SHIFT REGISTER. HIGH SPEED t PD = 15 (TYP.) AT CC =5.LOW POWER DISSIPATION ICC =4µA (MAX.) AT TA =25 C.OUTPUT DRIE CAPABILITY 10 LSTTL LOADS BALANCED PROPAGATION DELAYS tplh = tphl SYMMETRICAL OUTPUT IMPEDANCE I OL = IOH = 4 ma (MIN.) HIGH NOISE IMMUNITY NIH =NIL =28%CC (MIN.). WIDE OPERATING OLTAGE RANGE CC (OPR) = 2 TO 6 PIN AND FUNCTION COMPATIBLE WITH 54/74LS164 B1R (Plastic Package) M1R (Micro Package) F1R (Ceramic Package) C1R (Chip Carrier) ORDER CODES : M54HC164F1R M74HC164M1R M74HC164B1R M74HC164C1R PIN CONNECTIONS (top view) DESCRIPTION The M54/74HC164 is a high speed CMOS 8 BIT SIPO SHIFT REGISTER fabricated in silicon gate C 2 MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power coumption. The HC164 is an 8 bit shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (A or B), either of these inputs can be used as an active high enable for data entry through the other input. An unused input must be high, or both inputs connected together. Each low-to-high traition on the clock input shifts data one place to the right and entersintoqa, the logic NAND of the two data inputs (A B), the data that existed before the rising clock edge. A low level on the clear input overrides all other inputs and clears the register asynchronously, forcing all Q outputs low. All inputs are equipped with protection circuits agait static discharge and traient excess voltage. NC = No Internal Connection October /12

10 M54/M74HC164 INPUT AND OUTPUT EQUIALENT CIRCUIT TRUTH TABLE INPUTS OUTPUS CLEAR CLOCK SERIAL IN A B QA QB... QH L X X X L L... L H X X NO CHANGE H L X L QAn... QGn H X L L QAn... QGn H H H H QAn... QGn X: Don t Care QAn - QGn : The level of QA -QG, respectively. before the most-recent traition of th clock. LOGIC DIAGRAM 2/12

11 M54/M74HC164 PIN DESCRIPTION IEC LOGIC SYMBOL PIN No SYMBOL NAME AND FUNCTION 1, 2 A, B Data Inputs 3, 4, 5, 6, 10, 11, 12, 13 QA to QH Outputs 8 CLOCK Clock Input (LOW to HIGH, Edge-triggered) 9 CLEAR Master Reset Input 7 GND Ground (0) 14 CC Positive Supply oltage ABSOLUTE MAXIMUM RATINGS Symbol Parameter alue Unit CC Supply oltage -0.5 to +7 I DC Input oltage -0.5 to CC O DC Output oltage -0.5 to CC I IK DC Input Diode Current ± 20 ma I OK DC Output Diode Current ± 20 ma IO DC Output Source Sink Current Per Output Pin ± 25 ma I CC or I GND DC CC or Ground Current ± 50 ma P D Power Dissipation 500 (*) mw Tstg Storage Temperature -65 to +150 o C T L Lead Temperature (10 sec) 300 o C Absolute MaximumRatings are those values beyond whichdamage tothe device may occur. Functional operation under these condition isnotimplied. (*) 500 mw: 65 o C derate to 300 mw by 10mW/ o C: 65 o Cto85 o C RECOMMENDED OPERATING CONDITIONS Symbol Parameter alue Unit CC Supply oltage 2 to 6 I Input oltage 0 to CC O Output oltage 0 to CC T op Operating Temperature: M54HC Series M74HC Series -55 to to +85 o C C t r,t f Input Rise and Fall Time CC = 2 0 to 1000 CC = to 500 CC = 6 0 to 400 3/12

12 M54/M74HC164 DC SPECIFICATIONS Symbol IH IL OH OL II I CC Parameter High Level Input oltage Low Level Input oltage High Level Output oltage Low Level Output oltage Input Leakage Current Quiescent Supply Current CC () Test Conditio TA =25 o C 54HC and 74HC alue -40 to 85 o C 74HC -55 to 125 o C 54HC Min. Typ. Max. Min. Max. Min. Max I = 4.5 I O =-20 µa IH or IL IO=-4.0 ma IO=-5.2 ma I = 4.5 I O =20µA IH or IL I O = 4.0 ma IO= 5.2 ma I =CC or GND ±0.1 ±1 ±1 µa 6.0 I = CC or GND µa Unit 4/12

13 M54/M74HC164 AC ELECTRICAL CHARACTERISTICS (CL =50pF,Inputtr=tf=6) Symbol t TLH tthl tplh tphl tphl f MAX tw(h) tw(l) tw(l) t s t h Parameter Output Traition Time Propagation Delay Time (CLOCK - Q) Propagation Delay Time (CLEAR - Q) Maximum Clock Frequency Minimum Pulse Width (CLOCK) Minimum Pulse Width (CLEAR) Minimum Set-up Time (A, B - CK) Minimum Hold Time (A, B - CK) CC () Test Conditio TA =25 o C 54HC and 74HC alue -40 to 85 o C 74HC -55 to 125 o C 54HC Min. Typ. Max. Min. Max. Min. Max trem Minimum Removal Time CIN Input Capacitance pf Power Dissipation 99 Capacitance pf CPD (*) (*) CPD is defined as the value of the IC s internal equivalent capacitance which is calculated from the operating current coumption without load. (Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD CC fin + ICC Unit MHz 5/12

14 M54/M74HC164 TIMING CHART 6/12

15 M54HC393 M74HC393 DUAL BINARY COUNTER. HIGH SPEED fmax = 72 MHz (TYP.) AT CC =5.LOW POWER DISSIPATION I CC =4µA (MAX.) AT T A =25 C.HIGH NOISE IMMUNITY NIH =NIL =28%CC (MIN.) OUTPUT DRIE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOH =IOL = 4 ma (MIN.) BALANCED PROPAGATION DELAYS t PLH =t. PHL WIDE OPERATING OLTAGE RANGE CC (OPR) = 2 TO 6 PIN AND FUNCTION COMPATIBLE WITH 54/74LS393 B1R (Plastic Package) M1R (Micro Package) F1R (Ceramic Package) C1R (Chip Carrier) ORDER CODES : M54HC393F1R M74HC393M1R M74HC393B1R M74HC393C1R PIN CONNECTIONS (top view) DESCRIPTION The M54/74HC393 is a high speed CMOS DUAL BINARY COUNTER fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true COMS low power coumption. This counter circuit contai independent ripple carry counters and two 4-bit ripple carry binary counters, which can be cascated to create a single divide by 256 counter. Each 4-bit counter is incremented on the high to low traition (negative edge) of the clock input,and each has an independent clear input. When clear is set to low all four bits of each counter are set to a low level. This enables count truncation and allows the implementation od divide by N counter configuratio. All inputs are equipped with protection circuits agait static discharge and traient excess voltage. NC = No Internal Connection February /12

16 M54/M74HC393 INPUT AND OUTPUT EQUIALENT CIRCUIT TRUTH TABLE INPUTS OUTPUS CLOCK CLEAR QD QC QB QA X H L L L L L COUNT UP L NO CHANGE X: Don t Care COUNT OUTPUT QD QC QB QA 0 L L L L 1 L L L H 2 L L H L 3 L L H H 4 L H L L 5 L H L H 6 L H H L 7 L H H H 8 H L L L 9 H L L H 10 H L H L 11 H L H H 12 H H L L 13 H H L H 14 H H H L 15 H H H H 2/12

17 M54/M74HC393 LOGIC DIAGRAM TIMING CHART 3/12

18 M54/M74HC393 PIN DESCRIPTION IEC LOGIC SYMBOL PIN No SYMBOL NAME AND FUNCTION 1, 13 1 CLOCK A 2 CLOCK A 2, 12 1 CLEAR 2 CLEAR Clocck Input (HIGH to LOW Edge triggered) Asynchronou Master Reset Inputs 3, 4, 5, 6 1QA to 1QD Flip Flop Outputs 11, 10, 9, 8 2QA to 2QD Flip Flop Outputs 7 GND Ground (0) 14 CC Positive Supply oltage ABSOLUTE MAXIMUM RATINGS Symbol Parameter alue Unit CC Supply oltage -0.5 to +7 I DC Input oltage -0.5 to CC O DC Output oltage -0.5 to CC I IK DC Input Diode Current ± 20 ma I OK DC Output Diode Current ± 20 ma IO DC Output Source Sink Current Per Output Pin ± 25 ma I CC or I GND DC CC or Ground Current ± 50 ma P D Power Dissipation 500 (*) mw Tstg Storage Temperature -65 to +150 o C T L Lead Temperature (10 sec) 300 o C Absolute MaximumRatings are those values beyond whichdamage tothe device may occur. Functional operation under these condition isnotimplied. (*) 500 mw: 65 o C derate to 300 mw by 10mW/ o C: 65 o Cto85 o C RECOMMENDED OPERATING CONDITIONS Symbol Parameter alue Unit CC Supply oltage 2 to 6 I Input oltage 0 to CC O Output oltage 0 to CC T op Operating Temperature: M54HC Series M74HC Series -55 to to +85 o C C t r,t f Input Rise and Fall Time CC = 2 0 to 1000 CC = to 500 CC = 6 0 to 400 4/12

19 M54/M74HC393 DC SPECIFICATIONS Symbol IH IL OH OL II I CC Parameter High Level Input oltage Low Level Input oltage High Level Output oltage Low Level Output oltage Input Leakage Current Quiescent Supply Current CC () Test Conditio TA =25 o C 54HC and 74HC alue -40 to 85 o C 74HC -55 to 125 o C 54HC Min. Typ. Max. Min. Max. Min. Max I = 4.5 I O =-20 µa IH or IL IO=-4.0 ma IO=-5.2 ma I = 4.5 I O =20µA IH or IL I O = 4.0 ma IO= 5.2 ma I =CC or GND ±0.1 ±1 ±1 µa 6.0 I = CC or GND µa Unit 5/12

20 M54/M74HC393 AC ELECTRICAL CHARACTERISTICS (CL =50pF,Inputtr=tf=6) Symbol t TLH tthl tplh tphl tplh t PHL t PLH t PHL tplh tphl tplh tphl f MAX t W(H) tw(l) tw(h) Parameter Output Traition Time Propagation Delay Time (CLOCK - QA) Propagation Delay Time (CLOCK - QB) Propagation Delay Time (CLOCK - QC) Propagation Delay Time (CLOCK - QD) Propagation Delay Time (CLEAR - Qn) Maximum Clock Frequency Minimum Pulse Width (CLOCK) Minimum Pulse Width (CLEAR) CC () Test Conditio TA =25 o C 54HC and 74HC alue -40 to 85 o C 74HC -55 to 125 o C 54HC Min. Typ. Max. Min. Max. Min. Max trem Minimum Removal Time C IN Input Capacitance pf CPD (*) Power Dissipation 35 Capacitance pf (*) C PD is defined as the value of the IC s internal equivalent capacitance which is calculated from the operating current coumption without load. (Refer to Test Circuit). Average operting current can be obtained by the following equation. I CC(opr) = C PD CC f IN +I CC/4 (per Flip Flop) Unit MHz 6/12

21 Einführungsprojekt Elektrotechnik 2009 Einheit_4: Logische Schaltungen und Automaten Abbildung 1: Pinbelegung des 4x NAND-74HC00 Abbildung 2: Pinbelegung des 4x NOR-74HC02-1 -