FAST CMOS OCTAL D REGISTERS (3-STATE)
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- Jacob Morton
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1 Integrated evice Technology, Inc. FAST CMOS OCTA REGISTERS (3-STATE) IT4/4FCT34/A/C IT4/4FCT34/A/C IT4/4FCT4/A/C FEATURES: IT4/4FCT34/34/4 equivalent to FAST speed and drive IT4/4FCT34A/34A/4A up to 30% faster than FAST IT4/4FCT34C/34C/4C up to 0% faster than FAST IO = 4mA (commercial) and 32mA (military) CMOS power levels (mw typ. static) Edge triggered master/slave, -type flip-flops Buffered common clock and buffered common threestate control Product available in Radiation Tolerant and Radiation Enhanced versions Military product compliant to MI-ST-3, Class B Meets or exceeds JEEC Standard specifications ESCRIPTION: The IT4/4FCT34/A/C, IT4/4FCT34/A/C and IT4/4FCT4/A/C are -bit registers built using an advanced dual metal CMOS technology. These registers consist of eight -type flip-flops with a buffered common clock and buffered 3-state output control. When the output enable () is OW, the eight outputs are enabled. When the input is IG, the outputs are in the high-impedance state. Input data meeting the set-up and hold time requirements of the inputs is transferred to the O outputs on the OW-to- IG transition of the clock input. The IT4/4FCT34/A/C and IT4/4FCT4/A/ C have non-inverting outputs with respect to the data at the inputs. The IT4/4FCT34/A/C have inverting outputs. FUNCTIONA BOCK IAGRAM IT4/4FCT34 AN IT4/4FCT cnv* 0 FUNCTIONA BOCK IAGRAM IT4/4FCT cnv* 02 The IT logo is a registered trademark of Integrated evice Technology, Inc. FAST is a trademark of National Semiconductor, Inc. MIITARY AN COMMERCIA TEMPERATURE RANGES MAY Integrated evice Technology, Inc..3 SC-422/2
2 IT4/4FCT34/34/4/A/C FAST CMOS OCTA REGISTERS (3-STATE) MIITARY AN COMMERCIA TEMPERATURE RANGES PIN CONFIGURATIONS IT4/4FCT GN P S0-2 & E IP/SOIC/CERPACK 4 INEX cnv* cnv* GN CC 4 IT4/4FCT GN P S0-2 & 4 E IP/SOIC/CERPACK INEX GN cnv* cnv* 0 CC IT4/4FCT GN P S0-2 & E IP/SOIC/CERPACK 4 INEX cnv* cnv* 0 GN CC 4.3 2
3 IT4/4FCT34/34/4/A/C FAST CMOS OCTA REGISTERS (3-STATE) MIITARY AN COMMERCIA TEMPERATURE RANGES PIN ESCRIPTION FUNCTION TABE () i- Pin Names N ON ON Function oad Register escription flip-flop data inputs. Clock Pulse for the register. Enters data on OW-to-IG transition. 3-state outputs, (true). 3-state outputs, (inverted). Active OW 3-state Output Enable input. 203 tbl 0 FCT34 FCT34/4 Inputs Outputs Internal Outputs Internal N ON N ON N u u u u X X NOTE: 203 tbl 0. = IG Voltage evel = igh Impedance = OW Voltage evel NC = No Change X = on t Care u = OW-to-IG transition NC NC NC NC ABSOUTE MAXIMUM RATINGS () Symbol Rating Commercial Military Unit VTERM (2) Terminal Voltage 0. to to +.0 V with Respect to GN VTERM (3) Terminal Voltage 0. to 0. to V with Respect to GN TA Operating 0 to +0 to +2 C Temperature TBIAS Temperature to +2 to +3 C Under Bias TSTG Storage to +2 to +0 C Temperature PT Power issipation W IOUT C Output Current ma CAPACITANCE (TA = +2 C, f =.0Mz) Symbol Parameter () Conditions Typ. Max. Unit CIN Input VIN = 0 pf Capacitance COUT Output Capacitance VOUT = 2 pf NOTE: 203 tbl 02. This parameter is measured at characterization but not tested. NOTES: 203 tbl 0. Stresses greater than those listed under ABSOUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed by +0.V unless otherwise noted. 2. Input and terminals only. 3. Outputs and I/O terminals only..3 3
4 IT4/4FCT34/34/4/A/C FAST CMOS OCTA REGISTERS (3-STATE) MIITARY AN COMMERCIA TEMPERATURE RANGES C EECTRICA CARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: VC = 0.2V; VC = 0.2V Commercial: TA = 0 C to +0 C, =. ± %; Military: TA = C to +2 C, =. ± 0% Symbol Parameter Test Conditions () Min. Typ. (2) Max. Unit VI Input IG evel Guaranteed ogic IG evel 2.0 V VI Input OW evel Guaranteed ogic OW evel 0. V II Input IG Current = Max. VI = µa VI = 2.V (4) II Input OW Current VI = 0.V (4) VI = GN IO Off State (igh Impedance) = Max. VO = 0 µa Output Current VO = 2.V 0 (4) IO VO = 0.V 0 (4) VO = GN 0 VIK Clamp iode Voltage = Min., IN = ma 0..2 V IOS Short Circuit Current = Max. (3), VO = GN 0 20 ma VO Output IG Voltage =, VIN = VC or VC, IO = 32µA VC V = Min. IO = 300µA VC VIN = VI or VI IO = 2mA MI IO = ma COM' VO Output OW Voltage =, VIN = VC or VC, IO = 300µA GN VC V = Min. IO = 300µA GN VC (4) VIN = VI or VI IO = 32mA MI IO = 4mA COM' NOTES: 203 tbl 03. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at =., +2 C ambient and maximum loading. 3. Not more than one output should be shorted at one time. uration of the short circuit test should not exceed one second. 4. This parameter is guaranteed but not tested..3 4
5 IT4/4FCT34/34/4/A/C FAST CMOS OCTA REGISTERS (3-STATE) MIITARY AN COMMERCIA TEMPERATURE RANGES POWER SUPPY CARACTERISTICS VC = 0.2V; VC = 0.2V Symbol Parameter Test Conditions () Min. Typ. (2) Max. Unit uiescent Power Supply Current = Max. ICC 0.2. ma VIN VC; V IN VC ICC ICC uiescent Power Supply Current TT Inputs IG ynamic Power Supply Current (4) = Max. VIN = 3.4V (3) ma = Max. Outputs Open = GN One Input Toggling 0% uty Cycle IC Total Power Supply Current () = Max. Outputs Open f = 0Mz 0% uty Cycle = GN fi = Mz 0% uty Cycle One Bit Toggling = Max. Outputs Open f = 0Mz 0% uty Cycle = GN Eight Bits Toggling fi = 2.Mz 0% uty Cycle VIN VC VIN VC VIN VC VIN VC (FCT) VIN = 3.4V VIN = GN VIN VC VIN VC (FCT) VIN = 3.4V VIN = GN ma/ Mz. 4.0 ma ().2. () NOTES: 203 tbl 04. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at =., +2 C ambient. 3. Per TT driven input (VIN = 3.4V); all other inputs at or GN. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.. IC = IUIESCENT + IINPUTS + IYNAMIC IC = ICC + ICC NT + ICC (f/2 + fini) ICC = uiescent Current ICC = Power Supply Current for a TT igh Input (VIN = 3.4V) = uty Cycle for TT Inputs igh NT = Number of TT Inputs at ICC = ynamic Current Caused by an Input Transition Pair ( or ) f = Clock Frequency for Register evices (ero for Non-Register evices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz..3
6 IT4/4FCT34/34/4/A/C FAST CMOS OCTA REGISTERS (3-STATE) MIITARY AN COMMERCIA TEMPERATURE RANGES SWITCING CARACTERISTICS OVER OPERATING RANGE FCT34/34/4 FCT34A/34A/4A FCT34C/34C/4C Com'l. Mil. Com'l. Mil. Com'l. Mil. Symbol Parameter Conditions () Min. (2) Max. Min. (2) Max. Min. (2) Max. Min. (2) Max. Min. (2) Max. Min. (2) Max. Unit tp tp tp tp tp tp tsu t tw Propagation elay to ON (3) Output Enable Time Output isable Time Set-up Time IG or OW, N to old Time IG or OW, N to Pulse Width IG or OW C = 0pF R = 00Ω ns ns ns ns ns ns NOTES: 203 tbl 0. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation elays. 3. ON for FCT34 and FCT4, ON for FCT34..3
7 IT4/4FCT34/34/4/A/C FAST CMOS OCTA REGISTERS (3-STATE) TEST CIRCUITS AN WAVEFORMS TEST CIRCUITS FOR A OUTPUTS Pulse Generator VIN R T.U.T. V OUT 0pF C 00Ω 00Ω. MIITARY AN COMMERCIA TEMPERATURE RANGES SWITC POSITION Test Open rain isable ow Enable ow All Other Tests Switch Closed Open EFINITIONS: 203 tbl 0 C = oad capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to OUT of the Pulse Generator. SET-UP, O AN REEASE TIMES PUSE WIT ATA INPUT TIMING INPUT ASYNCRONOUS CONTRO PRESET CEAR ETC. SYNCRONOUS CONTRO PRESET CEAR COCK ENABE ETC. t SU t SU t REM t t OW-IG-OW PUSE IG-OW-IG PUSE t W PROPAGATION EAY ENABE AN ISABE TIMES SAME PASE INPUT TRANSITION OUTPUT OPPOSITE PASE INPUT TRANSITION tp t P t P tp VO VO CONTRO INPUT OUTPUT NORMAY OW OUTPUT NORMAY IG ENABE tp SWITC COSE tp SWITC OPEN 3.V ISABE tp 0. tp 0. 3.V V O V O NOTES 203 drw. iagram shown for input Control Enable-OW and input Control isable-ig. 2. Pulse Generator for All Pulses: Rate.0 Mz; O 0Ω; tf 2.ns; tr 2.ns..3
8 IT4/4FCT34/34/4/A/C FAST CMOS OCTA REGISTERS (3-STATE) MIITARY AN COMMERCIA TEMPERATURE RANGES ORERING INFORMATION IT XX Temp. Range FCT XXXX evice Type X Package X Process Blank B P SO E A 4A 34A 34C 4C 34C 4 4 Commercial MI-ST-3, Class B Plastic IP CERIP Small Outline IC eadless Chip Carrier CERPACK Non-Inverting Octal Register Non-Inverting Octal Register Inverting Octal Register Fast Non-Inverting Octal Register Fast Non-Inverting Octal Register Fast Inverting Octal Register Super Fast Non-Inverting Octal Register Super Fast Non-Inverting Octal Register Super Fast Inverting Octal Register C to +2 C 0 C to +0 C 203 cnv* 4.3
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ata sheet acquired from Harris Semiconductor SCHS183 February 1998 C74HC374, C74HCT374, C74HC574, C74HCT574 High Speed CMOS Logic Octal -Type Flip-Flop, Three-State Positive-Edge Triggered Features escription
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P4C5 UTRA IG SPEED K X 4 RESETTABE STATIC CMOS RAM FEATURES Full CMOS, 6T Cell igh Speed (Equal Access and Cycle Times) //5//5 (Commercial) 5//5/35 (Military) Chip Clear Function ow Power Operation Separate
LOW-VOLTAGE QUADRUPLE BUS SWITCH 11 4B
LOW-VOLTAGE QUADRUPLE BUS ITCH IDT7CBTLV6 FEATURES: Pin-out compatible with standard '6 Logic products Ω A/B bi-directional switch Isolation under power-off conditions Over-voltage tolerant Latch-up performance
DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO TITLE
REVISIONS TR DESCRIPTION DTE PPROVED B Update boilerplate paragraphs to current requirements. - PN Update boilerplate to current MI-PRF-38535 requirements. - PN 11-08-22 Thomas M. ess 16-09-20 Thomas M.
LOW-VOLTAGE 16-BIT BUS SWITCH
LOW-VOLTAGE 16-BIT BUS ITCH IDT74CBTLV1645 FEATURES: 5Ω A/B bi-directional switch Isolation Under Power-Off Conditions Over-voltage tolerant Latch-up performance exceeds 100mA =.3V - 3.6V, normal range
SN54ALS873B, SN54AS873A, SN74ALS873B, SN74AS873A DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS036D APRIL 1982 REVISED AUGUST 1995
3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs
SN54HC165, SN74HC165 8-BIT PARALLEL-LOAD SHIFT REGISTERS
N5465, N465 8-BIT PAAE-OAD IFT EGITE 16C DECEMBE 1982 EVIED MAY 199 Complementary Outputs Direct Overriding oad (Data) Inputs Gated Clock Inputs Parallel-to-erial Data Conversion Package Options Include
SN54HC175, SN74HC175 QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
Contain Four Flip-Flops With Double-Rail Outputs Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators Package Options Include Plastic Small-Outline (D), Thin Shrink Small-Outline
74ACT11374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
Eight D-Type Flip-Flops in a Single Package -State Bus Driving True s Full Parallel Access for Loading Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and
INTEGRATED CIRCUITS. 74LVT V Octal D flip-flop. Product specification Supersedes data of 1994 May 11 IC23 Data Handbook.
INTEGRATE CIRCUITS Supersedes data of 994 May IC23 ata Handbook 998 Feb 9 FEATURES Eight edge-triggered -type flip-flops Buffered common clock Buffered asynchronous Master Reset Output capability: +64mA/
54ACT11109, 74ACT11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and GND Configuratio Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-µm
INTEGRATED CIRCUITS. 74ABT574A Octal D-type flip-flop (3-State) Product specification 1995 May 22 IC23 Data Handbook
INTEGRATE CIRCUITS 995 May 22 IC23 ata Handbook FEATURES is flow-through pinout version of 74ABT374 Inputs and outputs on opposite side of package allow easy interface to microprocessors 3-State outputs
INTEGRATED CIRCUITS. 74F174 Hex D flip-flops. Product specification Oct 07. IC15 Data Handbook
INTEGRATE CIRCUITS Hex flip-flops 1988 Oct 07 IC15 ata Handbook Hex flip-flop FEATURES Six edge-triggered -type flip-flops Buffered common Clock Buffered, asynchronous Master Reset PIN CONFIGURATION MR
SN54AS825A, SN74AS825A 8-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS020B JUNE 1984 REVISED AUGUST 1995
Functionally Equivalent to AMD s AM2982 Improved I OH Specificatio Multiple Output Enables Allow Multiuser Control of the Interface Outputs Have Undershoot-Protection Circuitry Power-Up High-Impedance
LY61L K X 16 BIT HIGH SPEED CMOS SRAM
Y6125616 REVISION HISTORY Revision Description Issue Date Rev. 1.0 Initial Issue May.24.2006 Rev. 1.1 Added Extended Grade Jan.22.2007 Rev. 1.2 Added PKG Type : 48-ball 6mm x 8mm TFBGA Jan.30.2007 Rev.
PI74LPT244. Fast CMOS 3.3V 8-Bit Buffer/Line Driver. Features. Description. Block Diagram. Pin Configuration
Fast CMOS 3.3V 8-Bit Buffer/Line Driver Features Compatible with LCX and LVT families of products Supports 5V Tolerant Mixed Signal Mode Operation Input can be 3V or 5V Output can be 3V or connected to
The data sheets contained in this book were the most current available as of the date of publication, April 1998.
Product Preview This heading on a data sheet indicates that the device is in the formative stages or in design (under development). The disclaimer at the bottom of the first page reads: This document contai
CMOS 16-BIT 3.3V TO 5V LEVEL SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS 2DIR 48 1OE. 3.3V Port. 5V Port
FEATURES: 0.5 MICRON CMOS Technology Typical tsk(o) (Output Skew) < 250ps ESD > 200 per MIL-STD-883, Method 3015; > 20 using machine model (C = 200pF, R = 0) VCCA = 2.7V to 3.6V VCCB = 5V ± 0.5V CMOS power
description V CC 2CLR 2D 2CLK 2PRE 2Q 2Q 1CLR 1D 1CLK 1PRE 1Q 1Q GND 2CLR 1CLR 1CLK NC 1PRE NC 1Q 2CLK 2PRE GND
Package Optio Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs TYPE TYPICAL MAXIMUM CLOCK FREUEY (CL = 0 pf) (MHz) TYPICAL POWER
SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SN54LS373, SN54LS374, SN54S373, SN54S374, Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving s Full Parallel Access for Loading Buffered Control s Clock-Enable Has
SN54ALS873B, SN54AS873A, SN74ALS873B, SN74AS873A DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS036D APRIL 1982 REVISED AUGUST 1995
3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs
LY V 128K X 16 BIT HIGH SPEED CMOS SRAM
Y6112816 REVISION HISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Aug.12.2007 Rev. 1.1 Apr. 17.2009 Revised TEST CONDITION of ICC Revised FEATURES & ORDERING INFORMATION ead free and green
PI74LPT V, 16-Bit Buffer/Line Driver. Features. Description. Block Diagram
Features Compatible with LCX and LVT families of products Supports 5V Tolerant Mixed Signal Mode Operation Input can be 3V or 5V Output can be 3V or connected to 5V bus Advanced Low Power CMOS Operation
SN54HC573A, SN74HC573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS147B DECEMBER 1982 REVISED MAY 1997
High-Current -State s Drive Bus Lines Directly or up to LSTTL Loads Bus-Structured Pinout Package Options Include Plastic Small-Outline (DW) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and
SN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
Package Optio Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs TYPE TYPICAL MAXIMUM CLOCK FREUEY (CL = 0 pf) (MHz) TYPICAL POWER
LY61L25616A 256K X 16 BIT HIGH SPEED CMOS SRAM
REVISION HISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Jul.12.2012 Rev. 1.1 VCC - 0.2V revised as 0.2V for TEST CONDITION Jul.19.2012 of Average Operating Power supply Current ICC1 on
Rev. No. History Issue Date Remark
256K X 8 BIT LOW VOLTAGE CMOS SRAM ocument Title 256K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. History Issue ate Remark 0.0 Initial issue June 24, 2002 Preliminary 0.1 Change VCC range from
INTEGRATED CIRCUITS. 74ALS377 Octal D flip flop with enable. Product specification IC05 Data Handbook Feb 08
INTEGRATE CIRCUITS Octal flip flop with enable IC05 ata Handbook 1991 Feb 08 Octal flip-flop with enable FEATURES Ideal for addressable register applicatio Enable for address and data synchronization applicatio
8-Channel Fault-Protected Analog Multiplexer ADG528F
8-Channel Fault-Protected Analog Multiplexer AG528F FEATURES Low on resistance (300 Ω typical) Fast switching times ton: 250 ns maximum toff: 250 ns maximum Low power dissipation (3.3 mw maximum) Fault
SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS
Single Down/Up Count-Control Line Look-Ahead Circuitry Enhances Speed of Cascaded Counters Fully Synchronous in Count Modes Asynchronously Presettable With Load Control Package Options Include Plastic
SN54/74LS390 SN54/74LS393 DUAL DECADE COUNTER; DUAL 4-STAGE BINARY COUNTER DUAL DECADE COUNTER; DUAL 4-STAGE BINARY COUNTER FAST AND LS TTL DATA 5-544
DUA DECADE ER; DUA -STAGE BINARY ER The SN5/7S and SN5/7S each contain a pair of high-speed -stage ripple counters. Each half of the S is partitioned into a divide-by-two section and a divide-by five section,
SN54ALS688, SN74ALS688 8-BIT IDENTITY COMPARATORS
Compare Two -Bit Words Totem-Pole Outputs () ALS Are Identical to ALS2 Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J)
SN54ALS273, SN74ALS273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SDAS218A APRIL 1982 REVISED DECEMBER 1994
WITH CLEA SDAS2A APIL 2 EVISED DECEMBE 4 Contain Eight Flip-Flops With Single-ail Outputs Buffered Clock and Direct-Clear Inputs Individual Data Input to Each Flip-Flop Applications Include: Buffer/Storage
74ABT377A Octal D-type flip-flop with enable
INTEGRATE CIRCUITS Replaces data sheet 74ABT377 of 1995 Sep 06 IC3 ata Handbook 1997 Feb 6 FEATURES Ideal for addressable register applicatio 8-bit positive edge-triggered register Enable for address and
PHILIPS 74F534 flip-flop datasheet
PHILIPS flip-flop datasheet http://www.manuallib.com/philips/74f534-flip-flop-datasheet.html The is an 8-bit edge-triggered register coupled to eight 3-State output buffers. The two sectio of the device
3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Description OBSOLESCENCE ORDER 71V016SA. Row / Column Decoders. Sense Amps and Write Drivers
3.3V CMOS Static RAM 1 Meg (4K x 1-Bit) IDT71V1 Features 4K x 1 advanced high-speed CMOS Static RAM Commercial ( to +7 C) and Industrial ( 4 C to +5 C) Equal access and cycle times Commercial and Industrial:
QUICKSWITCH PRODUCTS HIGH-SPEED CMOS QUICKSWITCH DUAL 4:1 MUX/DEMUX
QUICKSWITCH PRODUCTS HIGH-SPEED CMOS QUICKSWITCH DUAL :1 MUX/DEMUX IDTQS353 FEATURES: Enhanced N channel FET with no inherent diode to Vcc 5Ω bidirectional switches connect inputs to outputs Pin compatible
M54534P/FP MITSUBISHI SEMICONDUCTOR <TRANSISTOR ARRAY> 6-UNIT 320mA TRANSISTOR ARRAY WITH CLAMP DIODE AND STROBE
MITSUBISI SEMICONDUCTOR MP/FP -UNIT 2 TRANSISTOR ARRAY WIT CAMP DIODE AND STROBE DESCRIPTION MP and MFP are six-circuit transistor arrays. The circuits are made of NPN transistors. Both
Presettable Up/Down Counter High-Voltage Silicon-Gate CMOS
TECNICA DATA IW029B Presettable Up/Down Counter igh-voltage Silicon-Gate CMOS The IW029B coists of a four-stage binary or BCD-decade up/down counter with provisio for look-ahead carry in both counting
8-Bit Bidirectional Universal Shift Register with Parallel I/O High-Performance Silicon-Gate CMOS
TECHNICAL ATA IN74HC299 8-Bit Bidirectional Universal Shift Register with Parallel I/O High-Performance Silicon-Gate CMOS The IN74HC299 is identical in pinout to the LS/ALS299. The device inputs are compatible
SN74ALVCH V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 200 Per MIL-STD-883, Method 3015; Exceeds 20 Using Machine Model (C =
SN54ALS00A, SN54AS00, SN74ALS00A, SN74AS00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES
Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These devices contain four independent 2-input positive-nand
PHILIPS 74LVT16373A transparent D-type latch datasheet
PIIPS traparent -type latch datasheet http://www.manuallib.com/philips/74lvt16373a-traparent-d-type-latch-datasheet.html The is a high-performance BiCMOS product designed for VCC operation at 3.3V. This
CD74HC374, CD74HCT374, CD74HC574, CD74HCT574
ata sheet acquired from Harris Semiconductor SCHS183 February 1998 C74HC374, C74HCT374, C74HC574, C74HCT574 High Speed CMOS Logic Octal -Type Flip-Flop, Three-State Positive-Edge Triggered [ /Title (C74
TPIC6259 POWER LOGIC 8-BIT ADDRESSABLE LATCH
POWER OIC 8-BIT ARESSABE ATC ow r S(on).... Ω Typical Avalanche Energy...75 mj Eight Power MOS Transistor Outputs of 5-mA Continuous Current.5-A Pulsed Current Per Output Output Clamp Voltage at Four istinct
PI3C V/3.3V, High Bandwidth, Hot Insertion 10-Bit, 2-Port, Bus Switch
2.5V/3., High Bandwidth, Hot Insertion Features Near-Zero propagation delay 5-ohm switches connect inputs to outputs High Bandwidth (>400 MHz) Permits Hot Insertion. Rail-to-Rail, 3. or 2.5V ing 5V I/O