8-Channel Fault-Protected Analog Multiplexer ADG528F

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1 8-Channel Fault-Protected Analog Multiplexer AG528F FEATURES Low on resistance (300 Ω typical) Fast switching times ton: 250 ns maximum toff: 250 ns maximum Low power dissipation (3.3 mw maximum) Fault and overvoltage protection ( 40 V to +55 V) All switches off with power supply off Analog output of on channel clamped within power supplies if an overvoltage occurs Latch-up proof construction Break-before-make construction TTL and CMOS compatible inputs APPLICATIONS Existing multiplexer applications (both fault-protected and nonfault-protected) New designs requiring multiplexer functions GERAL ESCRIPTION The AG528F 1 is a CMOS analog multiplexer, with the comprising eight single channels. This multiplexer provides fault protection. Using a series n-channel, p-channel, n-channel MOSFET structure, both device and signal source protection is provided in the event of an overvoltage or power loss. The multiplexer can withstand continuous overvoltage inputs from 40 V to +55 V. uring fault conditions, the multiplexer input (or output) appears as an open circuit and only a few nanoamperes of leakage current will flow. This protects not only the multiplexer and the circuitry driven by the multiplexer, but also protects the sensors or signal sources that drive the multiplexer. The AG528F switches one of eight inputs to a common output as determined by the 3-bit binary address lines,, and. The AG528F has on-chip address and control latches that facilitate microprocessor interfacing. An input on the device is used to enable or disable the device. When disabled, all channels are switched off. FUNCTIONAL BLOCK IAGRAM WR AG528F 1 OF 8 ECOER Figure 1. PROUCT HIGHLIGHTS 1. Fault protection. The AG528F can withstand continuous voltage inputs from 40 V to +55 V. When a fault occurs due to the power supplies being turned off, all the channels are turned off and only a leakage current of a few nanoamperes flows. 2. On channel turns off while fault exists. 3. Low RON. 4. Fast switching times. 5. Break-before-make switching. Switches are guaranteed break-before-make so that input signals are protected against momentary shorting. 6. Trench isolation eliminates latch-up. A dielectric trench separates the p-channel and n-channel MOSFETs thereby preventing latch-up Rev. F Information furnished by Analog evices is believed to be accurate and reliable. However, no responsibility is assumed by Analog evices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog evices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA , U.S.A. Tel: Fax: Analog evices, Inc. All rights reserved.

2 AG528F TABLE OF CONTTS Features... 1 Applications... 1 Functional Block iagram... 1 General escription... 1 Product Highlights... 1 Revision History... 2 Specifications... 3 ual Supply... 3 Truth Table... 4 Timing iagrams... 5 Absolute Maximum Ratings...6 ES Caution...6 Pin Configuration and Function escriptions...7 Typical Performance Characteristics...8 Terminology Theory of Operation Test Circuits Outline imensions Ordering Guide REVISION HISTORY 7/11 Rev. E to Rev. F eleted AG508F/AG509F... Universal Changes to Table Added Table Updated Outline imensions Changes to Ordering Guide /09 Rev. to Rev. E Updated Format... Universal Added TSSOP... Universal Updated Outline imensions Changes to Ordering Guide /01 ata Sheet Changed from Rev. C to Rev.. Changes to Ordering Guide... 1 Changes to Specifications Table... 2 Max Ratings Changed... 4 eleted 16-Lead Cerdip from Outline imensions eleted 18-Lead Cerdip from Outline imensions Rev. F Page 2 of 16

3 AG528F SPECIFICATIONS UAL SUPPLY V = +15 V ± 10%, VSS = 15 V ± 10%, GN = 0 V, unless otherwise noted. Table 1. B Version Parameter +25 C 40 C to +85 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range VSS + 3 V min V 1.5 V max RON Ω typ 10 V VS +10 V, IS = 1 ma; V = +15 V ± 10%, VSS = 15 V ± 10% 400 Ω max 10 V VS +10 V, IS = 1 ma; V = +15 V ± 5%, VSS = 15 V ± 5% RON rift 0.6 %/ C typ VS = 0 V, IS = 1 ma RON Match 5 % max VS = 0 V, IS = 1 ma LEAKAGE CURRTS Source Off Leakage IS (Off) ±0.02 na typ V = ±10 V, VS = +10 V; ±1 ±50 na max See Figure 19 rain Off Leakage I (Off) ±0.04 na typ V = ±10 V, VS = +10 V; ±1 ±60 na max See Figure 20 Channel On Leakage I, IS (On) ±0.04 na typ VS = V = ± 10 V; ±1 ±60 na max See Figure 21 FAULT Output Leakage Current ±0.02 na typ VS = ±33 V, V = 0 V, see Figure 20 (With Overvoltage) ±2 ±2 μa max Input Leakage Current ±0.005 μa typ VS = ±25 V, V = +10 V, see Figure 22 (With Overvoltage) ±2 μa max Input Leakage Current ±0.001 μa typ VS = ±25 V, V = V =,, = 0 V (With Power Supplies Off) ±2 μa max See Figure 23 IGITAL INPUTS Input High Voltage, VINH 2.4 V min Input Low Voltage, VINL 0.8 V max Input Current, IINL or IINH ±1 μa max VIN = 0 or V CIN, igital Input Capacitance 5 pf typ YNAMIC CHARACTERISTICS 1 ttransition 200 ns typ RL = 1 MΩ, CL = 35 pf; ns max V = ±10 V, V = +10 V; see Figure 24 top 50 ns typ RL = 1 kω, CL = 35 pf; ns min VS = 5 V; see Figure 25 ton (, WR) 200 ns typ RL = 1 kω, CL = 35 pf; ns max VS = 5 V; see Figure 26 toff (, ) 200 ns typ RL = 1 kω, CL = 35 pf; tsett, Settling Time ns max VS = 5 V; see Figure % 1 μs typ RL = 1 kω, CL = 35 pf; 0.01% 2.5 μs typ VS = 5 V tw, Write Pulse Width ns min ts, Address, Enable Setup Time 100 ns min th, Address, Enable Hold Time 10 ns min t, Reset Pulse Width 100 ns min Rev. F Page 3 of 16

4 AG528F B Version Parameter +25 C 40 C to +85 C Unit Test Conditions/Comments Charge Injection 4 pc typ VS = 0 V, = 0 Ω, CL= 1 nf; see Figure 29 Off Isolation 68 db typ RL = 1 kω, CL = 15 pf, f = 100 khz; 50 db min VS = 7 V rms; see Figure 30 CS (Off) 5 pf typ C (Off) 50 pf typ POWER REQUIREMTS I ma max VIN = 0 V or 5 V ISS ma max 1 Guaranteed by design, not subject to production test. TRUTH TABLE Table 2. AG528F Truth Table 1 WR On Switch X X X X 1 Retains previous switch condition X X X X X 0 None (address and enable latches cleared) X X X None X = don t care. Rev. F Page 4 of 16

5 AG528F TIMING IAGRAMS Figure 2 shows the timing sequence for latching the switch address and enable inputs. The latches are level sensitive; therefore, while WR is held low, the latches are transparent and the switches respond to the address and enable inputs. This input data is latched on the rising edge of WR. Figure 3 shows the reset pulse width, t, and the reset turnoff time, toff ( ). Note that all digital input signals rise and fall times are measured from 10% to 90% of 3 V. tr = tf = 20 ns. WR 50% 50% t W t S,, 2V t H 0.8V Figure 2. Timing Sequence for Latching the Switch Address and Enable Inputs % 50% t t OFF () SWITCH OUTPUT Figure 3. Reset Pulse Width Rev. F Page 5 of 16

6 AG528F ABSOLUTE MAXIMUM RATINGS TA = 25 C unless otherwise noted. Table 3. Parameter V to VSS V to GN VSS to GN igital Input,, Ax VS, Analog Input Overvoltage with Power On (V = +15 V, VSS = 15 V) VS, Analog Input Overvoltage with Power Off (V = 0 V, VSS = 0 V) Continuous Current, S or 20 ma Peak Current, S or (Pulsed at 1 ms, 10% uty Cycle Max) 40 ma Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature 150 C θja, Thermal Impedance 90 C/W Lead Temperature, Soldering Vapor Phase (60 sec) 215 C Infrared (15 sec) 220 C Rating 44 V 0.3 V to +25 V +0.3 V to 25 V 0.3 V to V + 2 V or 20 ma, whichever occurs first VSS 25 V to V + 40 V 40 V to +55 V 40 C to +85 C 65 C to +150 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ES CAUTION Rev. F Page 6 of 16

7 AG528F PIN CONFIGURATION AN FUNCTION ESCRIPTIONS WR NC S PIN 1 INTFIER AG528F TOP VIEW (Not to Scale) GN S5 S S S4 NC S7 NC = NO CONNECT. O NOT CONNECT TO THIS PIN. Figure 4. Pin Configuration Table 4. Pin Function escriptions Pin No. Mnemonic escription 1 NC No Connect. This pin is open. 2 WR Write. The WR signal latches the state of the address control lines and the enable line. 3 Logic Control Input. 4 Active High igital Input. When low, the device is disabled and all switches are off. When high, Ax logic inputs determine on switches. 5 VSS Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. 6 Source Terminal 1. This pin can be an input or an output. 7 S2 Source Terminal 2. This pin can be an input or an output. 8 S3 Source Terminal 3. This pin can be an input or an output. 9 S4 Source Terminal 4. This pin can be an input or an output. 10 rain Terminal. This pin can be an input or an output. 11 NC No Connect. This pin is open. 12 Source Terminal 8. This pin can be an input or an output. 13 S7 Source Terminal 7. This pin can be an input or an output. 14 S6 Source Terminal 6. This pin can be an input or an output. 15 S5 Source Terminal 5. This pin can be an input or an output. 16 V Most Positive Power Supply Potential. 17 GN Ground (0 V) Reference. 18 Logic Control Input. 19 Logic Control Input. 20 Reset. The signal clears both the address and enable data in the latches resulting in no output (all switches off). Rev. F Page 7 of 16

8 AG528F TYPICAL PERFORMANCE CHARACTERISTICS T A = 25 C 1750 = +15V = 15V R ON (Ω) = +5V = 5V R ON (Ω) = +1 = T A = 85 C T A = 125 C 250 = +15V = 15V V, (V) T A = 25 C V, (V) Figure 5. On Resistance as a Function of V (VS) Figure 8. On Resistance as a Function of V (VS) for ifferent Temperatures 1m 1m 100µ 10µ = = V = 100µ 10µ = +15V = 15V V = I S INPUT LEAKAGE (A) 1µ 100n 10n 1n OPERATING RANGE I S INPUT LEAKAGE (A) 1µ 100n 10n 1n OPERATING RANGE 100p 100p 10p 10p 1p V IN INPUT VOLTAGE (V) Figure 6. Input Leakage Current as a Function of VS (Power Supplies Off) uring Overvoltage Conditions p INPUT VOLTAGE (V) Figure 9. Input Leakage Current as a Function of VS (Power Supplies On) uring Overvoltage Conditions m 0.3 I INPUT LEAKAGE (A) 100µ 10µ 1µ 100n 10n 1n 100p OPERATING RANGE = +15V = 15V V = LEAKAGE CURRTS (na) = +15V = 15V T A = 25 C I S (OFF) I S (OFF) I S (ON) 10p 1p V IN INPUT VOLTAGE (V) Figure 7. Output Leakage Current as a Function of VS (Power Supplies On) uring Overvoltage Conditions ,V (V) Figure 10. Leakage Currents as a Function of V (VS) Rev. F Page 8 of 16

9 AG528F LEAKAGE CURRTS (na) = +15V = 15V V = +1 = 1 I (OFF) I (ON) I S (OFF) SWITCHING TIME (ns) = +15V = 15V V IN = +5V t ON () t TRANSITION 120 t OFF () TEMPERATURE ( C) Figure 11. Leakage Currents as a Function of Temperature TEMPERATURE ( C) Figure 13. Switching Time vs. Temperature V IN = 2V SWITCHING TIME (ns) t TRANSITION t ON () t OFF () POWER SUPPLY (V) Figure 12. Switching Time vs. Power Supply Rev. F Page 9 of 16

10 AG528F TERMINOLOGY V Most positive power supply potential. VSS Most negative power supply potential. GN Ground (0 V) reference. RON Ohmic resistance between and S. RON rift Change in RON when temperature changes by one degree Celsius. RON Match ifference between the RON of any two channels. IS (Off) Source leakage current when the switch is off. I (Off) rain leakage current when the switch is off. I, IS (On) Channel leakage current when the switch is on. V (VS) Analog Voltage on Terminal and Terminal S. CS (Off) Channel input capacitance for off condition. C (Off) Channel output capacitance for off condition. C, CS (On) On switch capacitance. ton () elay time between the 50% and 90% points of the digital input and switch on condition. toff () elay time between the 50% and 90% points of the digital input and switch off condition. ttransition elay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. top Off time measured between 80% points of both switches when switching from one address state to another. VINL Maximum input voltage for Logic 0. VINH Minimum input voltage for Logic 1. IINL (IINH) Input current of the digital input. Off Isolation A measure of unwanted signal coupling through an off channel. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. I Positive supply current. ISS Negative supply current. CIN igital input capacitance. Rev. F Page 10 of 16

11 AG528F THEORY OF OPERATION The AG528F multiplexer is capable of withstanding overvoltages from 40 V to +55 V, irrespective of whether the power supplies are present or not. Each channel of the multiplexer consists of an n-channel MOSFET, a p-channel MOSFET, and an n-channel MOSFET, connected in series. When the analog input exceeds the power supplies, one of the MOSFETs will switch off, limiting the current to submicroamp levels, thereby preventing the overvoltage from damaging any circuitry following the multiplexer. Figure 14 illustrates the channel architecture that enables these multiplexers to withstand continuous overvoltages. When an analog input of VSS + 3 V to V 1.5 V is applied to the AG528F, the multiplexer behaves as a standard multiplexer, with specifications similar to a standard multiplexer, for example, the on-resistance is 400 Ω maximum. However, when an overvoltage is applied to the device, one of the three MOSFETs will turn off. Figure 14 to Figure 17 show the conditions of the three MOSFETs for the various overvoltage situations. When the analog input applied to an on channel approaches the positive power supply line, the n-channel MOSFET turns off because the voltage on the analog input exceeds the difference between V and the n-channel threshold voltage (VTN). When a voltage more negative than VSS is applied to the multiplexer, the p-channel MOSFET will turn off because the analog input is more negative than the difference between VSS and the p-channel threshold voltage (VTP). Because VTN is nominally 1.5 V and VTP is typically 3 V, the analog input range to the multiplexer is limited to 12 V to V when a ±15 V power supply is used. When the power supplies are present but the channel is off, again either the p-channel MOSFET or one of the n-channel MOSFETs will turn off when an overvoltage occurs. Finally, when the power supplies are off, the gate of each MOSFET will be at ground. A negative overvoltage switches on the first n-channel MOSFET but the bias produced by the overvoltage causes the p-channel MOSFET to remain turned off. With a positive overvoltage, the first MOSFET in the series will remain off because the gate to source voltage applied to this MOSFET is negative. uring fault conditions, the leakage current into and out of the AG528F is limited to a few microamps. This protects the multiplexer and succeeding circuitry from over stresses as well as protecting the signal sources, which drive the multiplexer. Also, the other channels of the multiplexer will be undisturbed by the overvoltage and will continue to operate normally. +55V OVERVOLTAGE Q1 Q2 Q3 n-channel MOSFET IS OFF Figure V Overvoltage Input to the On Channel 4 OVERVOLTAGE n-channel MOSFET IS ON Q1 Q2 Q3 p-channel MOSFET IS OFF Figure V Overvoltage on an Off Channel with Multiplexer Power On +55V OVERVOLTAGE n-channel MOSFET IS OFF Q1 Q2 Q3 Figure V Overvoltage with Power Off 4 OVERVOLTAGE n-channel MOSFET IS ON Q1 Q2 Q3 p-channel MOSFET IS OFF Figure V Overvoltage with Power Off Rev. F Page 11 of 16

12 AG528F TEST CIRCUITS I S V1 S S2 I (ON) A V 2.4V R ON = V 1 /I S Figure 18. On Resistance Figure 21. I (On) I S (OFF) A S2 A S2 0.8V 0.8V V Figure 19. IS (Off) Figure 22. Input Leakage Current (with Overvoltage) S2 I (OFF) A 0.8V V AG528F GN WR A Figure 20. I (Off) Figure 23. Input Leakage Current (with Power Supplies Off) Rev. F Page 12 of 16

13 AG528F V IN 50Ω 2.4V S2 TO S7 AG528F GN WR V V R L 1MΩ C L 35pF ARESS RIVE (V IN ) 50% 50% 90% Figure 24. Switching Time of Multiplexer, ttransition t TRANSITION 90% t TRANSITION V IN 50Ω 2.4V S2 TO S7 AG528F GN WR R L 1kΩ C L 35pF ARESS RIVE (V IN ) 80% 80% t OP Figure 25. Break-Before-Make elay, top V IN V S2 TO AG528F GN WR R L 1kΩ C L 35pF ABLE RIVE (V IN ) OUTPUT 50% 0.9 t ON () 50% t OFF () Figure 26. Enable elay, ton (), toff () V 2.4V V WR S2 TO AG528F WR GN R L 1kΩ C L 35pF WR OUTPUT 50% t ON (WR) Figure 27. Write Turn-On Time, ton (WR) Rev. F Page 13 of 16

14 AG528F 2.4V V IN S2 TO AG528F GN WR R L 1kΩ C L 35pF SWITCH OUTPUT 50% 50% t t OFF () Figure 28. Reset Turn-Off Time, toff () R S V IN AG528 S GN WR 2.4V C L 1nF LOGIC INPUT (V IN ) Figure 29. Charge Injection Q INJ = C L AG528F 2.4V GN WR R L 1kΩ Figure 30. Off Isolation V IN Rev. F Page 14 of 16

15 AG528F OUTLINE IMSIONS (1.22) (1.07) (0.51) R (1.22 ) (1.07) PIN 1 18 ITIFIER TOP VIEW (PINS OWN) (9.04) (8.89) SQ (10.03) (9.78) SQ (1.42) (1.07) (1.27) BSC (4.57) (4.19) 0.20 (0.51) MIN (0.53) (0.33) (8.38) (0.81) (7.37) (0.66) (1.14) (0.64) R (3.04) (2.29) (0.50) R COMPLIANT TO JEEC STANA MO-047-AA CONTROLLING IMSIONS ARE IN INCHES; MILLIMETER IMSIONS (IN PARTHESES) ARE ROUNE-OFF INCH EQUIVALTS FOR REFERCE ONLY AN ARE NOT APPROPRIATE FOR USE IN ESIGN. Figure Lead Plastic Leaded Chip Carrier [PLCC] (P-20) imensions shown in inches and (millimeters) BOTTOM VIEW (PINS UP) ORERING GUIE Model 1 Temperature Range Package escription Package Option AG528FBP 40 C to +85 C 20-Lead PLCC P-20 AG528FBPZ 40 C to +85 C 20-Lead PLCC P-20 1 Z = RoHS Compliant Part. Rev. F Page 15 of 16

LC 2 MOS 8-/16-Channel High Performance Analog Multiplexers ADG406/ADG407/ADG426

LC 2 MOS 8-/16-Channel High Performance Analog Multiplexers AG406/AG407/AG426 FEATURES 44 V supply maximum ratings VSS to V analog signal range Low on resistance (80 Ω maximum) Low power Fast switching