Low Capacitance, Low Charge Injection, ±15 V/12 V icmos, Dual SPDT Switch ADG1236

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1 ata Sheet Low Capacitance, Low Charge Injection, ±5 V/2 V icmos, ual SPT Switch FEATURES.3 pf off capacitance 3.5 pf on capacitance pc charge injection 33 V supply range 2 Ω on resistance Fully specified at +2 V, ±5 V No VL supply required 3 V logic-compatible inputs Rail-to-rail operation 6-lead TSSOP and 2-lead LFCSP packages Typical power consumption: <.3 µw APPLICATIONS Automatic test equipment ata acquisition systems Battery-powered systems Sample-and-hold systems Audio/video signal routing Communication systems GENERAL ESCRIPTION The is a monolithic CMOS device containing two independently selectable SPT switches. It is designed on an icmos process. icmos (industrial CMOS) is a modular manufacturing process combining high voltage complementary metal-oxide semiconductor (CMOS) and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage devices has been able to achieve. Unlike analog ICs using conventional CMOS processes, icmos components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. The ultralow capacitance and charge injection of the device make it an ideal solution for data acquisition and sample-andhold applications, where low glitch and fast settling are required. Fast switching speed coupled with high signal bandwidth makes the device suitable for video signal switching. icmos construction ensures ultralow power dissipation, making the device ideally suited for portable and battery-powered instruments. FUNCTIONAL BLOCK IAGRAM SA SB IN IN2 S2A S2B 2 SWITCHES SHOWN FOR A LOGIC INPUT Figure. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. Both switches exhibit break-before-make switching action for use in multiplexer applications. PROUCT HIGHLIGHTS..3 pf off capacitance (±5 V supply). 2. pc charge injection V logic-compatible digital inputs: VIH = 2. V, VIL =.8 V. 4. No VL logic power supply required. 5. Ultralow power dissipation: <.3 µw lead TSSOP and 2-lead 3 mm 3 mm LFCSP packages Rev. A ocument Feedback Information furnished by Analog evices is believed to be accurate and reliable. However, no responsibility is assumed by Analog evices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog evices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA , U.S.A. Tel: Analog evices, Inc. All rights reserved. Technical Support

2 TABLE OF CONTENTS Features... Applications... Functional Block iagram... General escription... Product Highlights... Revision History... 2 Specifications... 3 ual Supply... 3 Single Supply... 5 ata Sheet Absolute Maximum Ratings...6 ES Caution...6 Truth Table for Switches...6 Pin Configurations and Function escriptions...7 Terminology...8 Typical Performance Characteristics...9 Test Circuits... 2 Outline imensions... 4 Ordering Guide... 4 REVISION HISTORY 3/6 Rev. to Rev. A Changes to Figure 2 and Figure Updated Outline imensions... 4 Changes to Ordering Guide /5 Revision : Initial Version Rev. A Page 2 of 6

3 ata Sheet SPECIFICATIONS UAL SUPPLY V = 5 V ± %, VSS = 5 V ± %, GN = V, unless otherwise noted. Table. Y Version Parameters 25 C 4 C to +85 C 4 C to +25 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V to VSS V On Resistance (RON) 2 Ω typ VS = ± V, IS = ma; Figure Ω max V = +3.5 V, VSS = 3.5 V On Resistance Match Between 3.5 Ω typ VS = ± V, IS = ma Channels ( RON) 6 2 Ω max On Resistance Flatness (RFLAT(ON)) 2 Ω typ VS = 5 V, V, +5 V; IS = ma Ω max LEAKAGE CURRENTS V = +6.5 V, VSS = 6.5 V Source Off Leakage, IS (Off) ±.2 na typ VS = ± V, VS = V; Figure 2 ±. ±.6 ± na max rain Off Leakage, I (Off) ±.2 na typ VS = ± V, VS = V; Figure 2 ±. ±.6 ± na max Channel On Leakage, I, IS (On) ±.2 na typ VS = V = ± V; Figure 22 ±.2 ±.6 ± na max IGITAL INPUTS Input High Voltage, VINH 2. V min Input Low Voltage, VINL.8 V max Input Current, IINL or IINH.5 μa typ VIN = VINL or VINH ±. μa max igital Input Capacitance, CIN 2 pf typ YNAMIC CHARACTERISTICS 2 Transition Time, ttrans AOFF BON 25 ns typ RL = 3 Ω, CL = 35 pf 5 2 ns max VS = V; Figure 23 Transition Time, ttrans BOFF AON 7 ns typ RL = 3 Ω, CL = 35 pf 9 5 ns max VS = V; Figure 23 Break-Before-Make Time elay, t 25 ns typ RL = 3 Ω, CL = 35 pf ns min VS = VS2 = V; Figure 24 Charge Injection pc typ VS = V, RS = Ω, CL = nf; Figure 25 Off Isolation 8 db typ RL = 5 Ω, CL = 5 pf, f = MHz; Figure 26 Channel-to-Channel Crosstalk 85 db typ RL = 5 Ω, CL = 5 pf, f = MHz; Figure 27 Total Harmonic istortion + Noise.5 % typ RL = kω, 5 V rms, f = 2 Hz to 2 khz 3 db Bandwidth MHz typ RL = 5 Ω, CL = 5 pf; Figure 28 CS (Off).3 pf typ f = MHz; VS = V.6 pf max f = MHz; VS = V C, CS (On) 3.5 pf typ f = MHz; VS = V 4.3 pf max f = MHz; VS = V Rev. A Page 3 of 6

4 ata Sheet Y Version Parameters 25 C 4 C to +85 C 4 C to +25 C Unit Test Conditions/Comments POWER REQUIREMENTS V = +6.5 V, VSS = 6.5 V I. µa typ igital inputs = V or V. µa max I 7 µa typ igital inputs = 5 V 23 µa max ISS. µa typ igital inputs = V or V. µa max ISS. µa typ igital inputs = 5 V. µa max Temperature range for Y version is 4 C to +25 C. 2 Guaranteed by design; not subject to production test. Rev. A Page 4 of 6

5 ata Sheet SINGLE SUPPLY V = 2 V ± %, VSS = V, GN = V, unless otherwise noted. Table 2. Y Version Parameters 25 C 4 C to +85 C 4 C to +25 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V to V V On Resistance (RON) 3 Ω typ VS = V to V, IS = ma; Figure Ω max V =.8 V, VSS = V On Resistance Match Between 4.5 Ω typ VS = V to V, IS = ma Channels ( RON) Ω max On Resistance Flatness (RFLAT(ON)) 6 Ω typ VS = 3 V, 6 V, 9 V, IS = ma LEAKAGE CURRENTS V = 3.2 V Source Off Leakage, IS (Off ) ±.2 na typ VS = V/ V, V = V/ V; Figure 2 ±. ±.6 ± na max rain Off Leakage, I (Off ) ±.2 na typ VS = V/ V, V = V/ V; Figure 2 ±. ±.6 ± na max Channel On Leakage, I, IS (On) ±.2 na typ VS = V = V or V, Figure 22 ±.2 ±.6 ± na max IGITAL INPUTS Input High Voltage, VINH 2. V min Input Low Voltage, VINL.8 V max Input Current, IINL or IINH. µa typ VIN = VINL or VINH ±. µa max igital Input Capacitance, CIN 3 pf typ YNAMIC CHARACTERISTICS 2 Transition Time, ttrans BOFF AON 5 ns typ RL = 3 Ω, CL = 35 pf 4 75 ns max VS = 8 V; Figure 23 Transition Time, ttrans AOFF BON 55 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 8 V; Figure 23 Break-Before-Make Time elay, t 5 ns typ RL = 3 Ω, CL = 35 pf ns min VS = VS2 = 8 V; Figure 24 Charge Injection.8 pc typ VS = 6 V, RS = Ω, CL = nf; Figure 25 Off Isolation 75 db typ RL = 5 Ω, CL = 5 pf, f = MHz; Figure 26; Channel-to-Channel Crosstalk 85 db typ RL = 5 Ω, CL = 5 pf, f = MHz; Figure 27 3 db Bandwidth 8 MHz typ RL = 5 Ω, CL = 5 pf; Figure 28 CS (Off ).6 pf typ f = MHz; VS = 6 V.9 pf max f = MHz; VS = 6 V C, CS (On) 4 pf typ f = MHz; VS = 6 V 4.9 pf max f = MHz; VS = 6 V POWER REQUIREMENTS V = 3.2 V I. µa typ igital inputs = V or V. µa max I 7 µa typ igital inputs = 5 V 23 µa max Temperature range for Y version is 4 C to +25 C. 2 Guaranteed by design; not subject to production test. Rev. A Page 5 of 6

6 ata Sheet ABSOLUTE MAXIMUM RATINGS TA = 25 C, unless otherwise noted. Table 3. Parameter Rating V to VSS 35 V V to GN.3 V to +25 V VSS to GN +.3 V to 25 V Analog Inputs VSS.3 V to V +.3 V or 3 ma, whichever occurs first igital Inputs GN.3 V to V +.3 V or 3 ma, whichever occurs first Peak Current, S or ma (pulsed at ms, % duty cycle max) Continuous Current per 25 ma Channel, S or Operating Temperature Range Automotive (Y Version) 4 C to +25 C Storage Temperature Range 65 C to +5 C Junction Temperature 5 C 6-Lead TSSOP, θja Thermal 2 C/W Impedance 2-Lead LFCSP, θja Thermal 8 C/W Impedance Reflow Soldering Peak 26 C Temperature, Pb Free Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ES CAUTION TRUTH TABLE FOR SWITCHES Table 4. IN Switch A Switch B Off On On Off Over voltages at IN, S, or are clamped by internal diodes. Current must be limited to the maximum ratings given. Rev. A Page 6 of 6

7 GN IN2 S2A SA IN ata Sheet PIN CONFIGURATIONS AN FUNCTION ESCRIPTIONS IN SA SB S GN NC NC TOP VIEW (Not to Scale) 6 NC 5 NC 4 NC 3 V 2 S2B 2 S2A 9 IN2 NC = NO CONNECT. O NOT CONNECT TO THIS PIN. Figure 2. TSSOP Pin Configuration SB 2 S 3 NC TOP VIEW (Not to Scale) 9 V 8 S2B 7 2 NOTES. NC = NO CONNECT. O NOT CONNECT TO THIS PIN. 2. THE EXPOSE PA MUST BE TIE TO SUBSTRATE, S. Figure 3. LFCSP Pin Configuration Table 5. Pin Function escriptions Pin No. TSSOP LFCSP Mnemonic escription IN Logic Control Input. 2 2 SA Source Terminal. Can be an input or output. 3 rain Terminal. Can be an input or output. 4 2 SB Source Terminal. Can be an input or output. 5 3 VSS Most Negative Power Supply Potential. 6 4 GN Ground ( V) Reference. 7, 8, 4 to 6 NC No Connect. 9 5 IN2 Logic Control Input. 6 S2A Source Terminal. Can be an input or output. 7 2 rain Terminal. Can be an input or output. 2 8 S2B Source Terminal. Can be an input or output. 3 9 V Most Positive Power Supply Potential. Rev. A Page 7 of 6

8 TERMINOLOGY I The positive supply current. ISS The negative supply current. V (VS) The analog voltage on Terminals and S. RON The ohmic resistance between and S. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. IS (Off) The source leakage current with the switch off. I (Off) The drain leakage current with the switch off. I, IS (On) The channel leakage current with the switch on. VINL The maximum input voltage for Logic. VINH The minimum input voltage for Logic. IINL (IINH) The input current of the digital input. CS (Off) The off switch source capacitance, measured with reference to ground. ata Sheet C (Off) The off switch drain capacitance, measured with reference to ground. C, CS (On) The on switch capacitance, measured with reference to ground. CIN The digital input capacitance. ttrans The delay time between the 5% and 9% points of the digital input and switch on condition when switching from one address state to another. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Off Isolation A measure of unwanted signal coupling through an off switch. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Bandwidth The frequency at which the output is attenuated by 3 db. On Response The frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. TH + N The ratio of the harmonic amplitude plus noise of the signal to the fundamental. Rev. A Page 8 of 6

9 ata Sheet TYPICAL PERFORMANCE CHARACTERISTICS ON RESISTANCE (Ω) V = 3.5V S = 3.5V V = 6.5V S = 6.5V V = 5V S = 5V ON RESISTANCE (Ω) T A = +25 C T A = +85 C T A = +25 C T A = 4 C V = 5V S = 5V SOURCE OR RAIN VOLTAGE (V) Figure 4. On Resistance as a Function of V (VS) for ual Supply TEMPERATURE ( C) Figure 7. On Resistance as a Function of V (VS) for ifferent Temperatures, ual Supply ON RESISTANCE (Ω) V = 5.5V S = 5.5V V = 4.5V S = 4.5V V = 5V S = 5V ON RESISTANCE (Ω) T A = 4 C T A = +25 C V = 2V S = V T A = +85 C T A = +25 C SOURCE OR RAIN VOLTAGE (V) Figure 5. On Resistance as a Function of V (VS) for ual Supply TEMPERATURE ( C) Figure 8. On Resistance as a Function of V (VS) for ifferent Temperatures, Single Supply V =.8V S = V.2.5 V = 5V S = 5V V BIAS = +V/ V ON RESISTANCE (Ω) V = 3.2V S = V V = 2V S = V SOURCE OR RAIN VOLTAGE (V) Figure 6. On Resistance as a Function of V (VS) for Single Supply LEAKAGE (na). I S (OFF).5.5 I, I S (ON) TEMPERATURE ( C) Figure 9. Leakage Currents as a Function of Temperature, ual Supply Rev. A Page 9 of 6

10 ata Sheet LEAKAGE (na) V = 2V S = V V BIAS = V/V I, I S (ON) I S (OFF) TEMPERATURE ( C) Figure. Leakage Currents as a Function of Temperature, Single Supply TIME (ns) A OFF B ON 2S 6 A OFF B ON 5V S 4 2 B OFF A ON 2S 8 6 B OFF A ON 5V S TEMPERATURE ( C) Figure 3. ttransition Times vs. Temperature I PER CHANNEL 2 V = 5V S = 5V I (µa) V = 5V S = 5V OFF ISOLATION (db) V = 2V S = V LOGIC, IN X (V) k k M M M G FREQUENCY (Hz) Figure. I vs. Logic Level Figure 4. Off Isolation vs. Frequency CHARGE INJECTIOIN (pc) V = 5V S = 5V V = 2V S = V CROSSTALK (db) V = 5V S = 5V BETWEEN SA AN SB V BIAS (V) Figure 2. Charge Injection vs. Source Voltage k k M M M G FREQUENCY (Hz) Figure 5. Crosstalk vs. Frequency BETWEEN S AN S Rev. A Page of 6

11 ata Sheet 5 V = 5V S = 5V 5 4 V = 5V S = 5V SOURCE/RAIN ON ON RESPONSE (db) 5 2 CAPACITANCE (pf) 3 2 SOURCE OFF 25 3 k k M M M G G FREQUENCY (Hz) Figure 6. On Response vs. Frequency V BIAS (V) Figure 8. Capacitance vs. Source Voltage for ual Supply TH + N (%)... LOA = kω V = 5V, S = 5V, = 3.5Vrms V = 5V, S = 5V, = 5Vrms CAPACITANCE (pf) V = 2V S = V SOURCE/RAIN ON SOURCE OFF. k k k FREQUENCY (Hz) Figure 7. TH + N vs. Frequency V BIAS (V) Figure 9. Capacitance vs. Source Voltage for Single Supply Rev. A Page of 6

12 ata Sheet TEST CIRCUITS V S I S Figure 2. Test Circuit On Resistance I S (OFF) A S I (OFF) A V Figure 2. Test Circuit 2 Off Resistance NC S I (ON) A NC = NO CONNECT V Figure 22. Test Circuit 3 On Leakage V. F S. F 5% 5% V S SB SA 5% 5% IN R L 3 C L 35pF 9% 9% GN t ON t OFF Figure 23. Test Circuit 4 Switching Times V. F S. F V S SB SA IN R L 3 C L 35pF 8% GN t BBM t BBM Figure 24. Test Circuit 5 Break-Before-Make Time elay V. F IN V GN S S SB SA. F C L nf NC (NORMALLY CLOSE SWITCH) (NORMALLY OPEN SWITCH) Figure 25. Test Circuit 6 Charge Injection ON Q INJ = C L OFF Rev. A Page 2 of 6

13 ata Sheet S. FV. F S. FV. F IN V S SA SB GN NC 5 NETWORK ANALYZER 5 R L 5 NETWORK ANALYZER R L 5 IN V S SA SB GN R 5 OFF ISOLATION = 2 log Figure 26. Test Circuit 7 Off Isolation CHANNEL-TO-CHANNEL CROSSTALK = 2 log Figure 28. Test Circuit 9 Bandwidth S. FV. F S. FV. F IN V SA GN S SB NC 5 NETWORK ANALYZER 5 R L 5 WITH SWITCH INSERTION LOSS = 2 log WITHOUT SWITCH IN V S GN S R L k AUIO PRECISION R S Figure 29. Test Circuit TH + Noise V p-p Figure 27. Test Circuit 8 Channel-to-Channel Crosstalk Rev. A Page 3 of 6

14 ata Sheet OUTLINE IMENSIONS BSC PIN.65 BSC.3.9 COPLANARITY..2 MAX SEATING PLANE COMPLIANT TO JEEC STANARS MO-53AB Figure 3. 6-Lead Thin Shrink Small Outline Package [TSSOP] (RU-6) imensions shown in millimeters PIN INICATOR SEATING PLANE SQ 2.9 TOP VIEW.5 BSC MAX.2 NOM COPLANARITY.8.2 REF 6 EXPOSE PA 2 4 BOTTOM VIEW 3 PIN INICATOR.45.3 SQ.5.25 MIN FOR PROPER CONNECTION OF THE EXPOSE PA, REFER TO THE PIN CONFIGURATION AN FUNCTION ESCRIPTIONS SECTION OF THIS ATA SHEET. COMPLIANT TO JEEC STANARS MO-22-WEE. Figure 3. 2-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm 3 mm Body and.75 mm Package Height (CP-2-4) imensions shown in millimeters ORERING GUIE Model Temperature Range Package escription Package Option YRUZ 4 C to +25 C 6-Lead Thin Shrink Small Outline Package [TSSOP] RU-6 YRUZ-REEL 4 C to +25 C 6-Lead Thin Shrink Small Outline Package [TSSOP] RU-6 YRUZ-REEL7 4 C to +25 C 6-Lead Thin Shrink Small Outline Package [TSSOP] RU-6 YCPZ-5RL7 4 C to +25 C 2-Lead Lead Frame Chip Scale Package [LFCSP] CP-2-4 YCPZ-REEL7 4 C to +25 C 2-Lead Lead Frame Chip Scale Package [LFCSP] CP A Z = RoHS Compliant Part. Rev. A Page 4 of 6

15 ata Sheet NOTES Rev. A Page 5 of 6

1.5 Ω On Resistance, ±15 V/12 V/±5 V, 4:1, icmos Multiplexer ADG1404

1.5 Ω On Resistance, ±15 V/12 V/±5 V, 4:1, icmos Multiplexer ADG1404 ata Sheet.5 Ω On Resistance, ±5 V/2 V/±5 V, 4:, icmos Multiplexer AG44 FEATURES.5 Ω on resistance.3 Ω on-resistance flatness. Ω on-resistance match between channels Up to 4 ma continuous current Fully