0.5 Ω CMOS, Dual 2:1 MUX/SPDT Audio Switch ADG884

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1 ata Sheet FEATURES.8 V to 5.5 V operation Ultralow on resistance.28 Ω typical at 5 V supply.4 Ω maximum at 5 V supply Excellent audio performance, ultralow distortion. Ω typical.5 Ω maximum RON flatness High current carrying capability 4 ma continuous 6 ma peak current at 5 V supply Rail-to-rail switching operation Typical power consumption (<. μw) APPLICATIONS Cellular phones PAs MP3 players Power routing Battery-powered systems PCMCIA cards Modems Audio and video signal routing Communications systems GENERAL ESCRIPTION The is a low voltage CMOS device containing two independently selectable single-pole, double-throw (SPT) switches. This device offers ultralow on resistance of.4 Ω over the full temperature range, making the part an ideal solution for applications that require minimal distortion through the switch. The also has the capability of carrying large amounts of current, typically 6 ma at 5 V operation. The is available in a -ball, 2 mm.5 mm WLCSP package, a -lead LFCSP_W package, and a -lead MSOP package. These tiny packages make the the ideal solution for space-constrained applications. When on, each switch conducts equally well in both directions and has an input signal range that extends to the supplies. The exhibits break-before-make switching action..5 Ω CMOS, ual 2: MUX/SPT Audio Switch FUNCTIONAL BLOCK IAGRAM SA SB IN IN2 S2A S2B 2 NOTES:. SWITCHES SHOWN FOR A LOGIC INPUT. Figure. PROUCT HIGHLIGHTS. Single.8 V to 5.5 V operation. 2. High current handling capability (4 ma continuous current) V logic compatible. 4. Low TH + N (.% typical). 5. Tiny 2 mm.5 mm WLCSP, 3 mm 3 mm -lead LFCSP_W, and -lead MSOP packages Rev. Information furnished by Analog evices is believed to be accurate and reliable. However, no responsibility is assumed by Analog evices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog evices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA , U.S.A. Tel: Fax: Analog evices, Inc. All rights reserved.

2 TABLE OF CONTENTS Features... Applications... Functional Block iagram... General escription... Product Highlights... Revision History... 2 Specifications... 3 Absolute Maximum Ratings... 6 ata Sheet ES Caution...6 Pin Configurations and Function escriptions...7 Typical Performance Characteristics...8 Test Circuits... Terminology... 3 Outline imensions... 4 Ordering Guide... 5 REVISION HISTORY 4/2 Rev. C to Rev. Added Exposed Pad Notation to Figure 2 and Table Changes to Figure 3 and Table /8 Rev. B to Rev. C Changes to Temperature Range...Universal Changes to Product Highlights... Changes to Table Updated Outline imensions... 4 Changes to the Ordering Guide /6 Rev. A to Rev. B Changes to Features Section... Changes to Table... 3 Changes to Table Changes to Table Changes to Table Changes to the Ordering Guide /5 Rev. to Rev. A Updated Outline imensions... 4 Changes to Ordering Guide... 5 /4 Revision : Initial Version Rev. Page 2 of 6

3 ata Sheet SPECIFICATIONS V = 5 V ± %, GN = V, unless otherwise noted. Table. Parameter 25 C 4 C to +85 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range to V V On Resistance, RON.28 Ω typ V = 4.5 V, VS = V to V, IS = ma.37.4 Ω max See Figure 8 On-Resistance Match Between Channels, RON. Ω typ V = 4.5 V, VS = 2 V, IS = ma.35.5 Ω max On-Resistance Flatness, RFLAT (On). Ω typ V = 4.5 V, VS = V to V.3.5 Ω max IS = ma LEAKAGE CURRENTS V = 5.5 V Source Off Leakage, IS (Off) ±.2 na typ VS =.6 V/4.5 V, V = 4.5 V/.6 V; see Figure 9 Channel On Leakage, I, IS (On) ±.2 na typ VS = V =.6 V or 4.5 V; see Figure 2 IGITAL INPUTS Input High Voltage, VINH 2. V min Input Low Voltage, VINL.8 V max Input Current, IINL or IINH.5 μa typ VIN = VINL or VINH ±. μa max igital Input Capacitance, CIN 2 pf typ YNAMIC CHARACTERISTICS ton 42 ns typ RL = 5 Ω, CL = 35 pf 5 53 ns max VS = 3 V/ V; see Figure 2 toff 5 ns typ RL = 5 Ω, CL = 35 pf 2 2 ns max VS = 3 V; see Figure 2 Break-Before-Make Time elay, tbbm 6 ns typ RL = 5 Ω, CL = 35 pf ns min VS = VS2 =.5 V; see Figure 22 Charge Injection 25 pc typ VS =.5 V, RS = Ω, CL = nf; see Figure 23 Off Isolation 6 db typ RL = 5 Ω, CL = 5 pf, f = khz; see Figure 24 Channel-to-Channel Crosstalk 2 db typ SA to S2A/SB to S2B, RL = 5 Ω, CL = 5 pf, f = khz; see Figure 27 6 db typ SA to SB/S2A to S2B, RL = 5 Ω, CL = 5 pf, f = khz; see Figure 25 Total Harmonic istortion, TH + N.7 % typ RL = 32 Ω, f = 2 Hz to 2 khz, VS = 3.5 V p-p Insertion Loss.3 db typ RL = 5 Ω, CL = 5 pf; see Figure 26 3 db Bandwidth 8 MHz typ RL = 5 Ω, CL = 5 pf; see Figure 26 CS (Off) 3 pf typ C, CS (On) 295 pf typ POWER REQUIREMENTS V = 5.5 V I.3 μa typ igital inputs = V or 5.5 V μa max Guaranteed by design, not production tested. Rev. Page 3 of 6

4 ata Sheet V = 3.4 V to 4.2 V; GN = V, unless otherwise noted. Table 2. Parameter 25 C 4 C to +85 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range to V V On Resistance, RON.33 Ω typ V = 3.4 V, VS = V to V, IS = ma.4.47 Ω max See Figure 8 On-Resistance Match Between Channels, RON.3 Ω typ V = 3.4 V, VS = 2 V, IS = ma Ω max On-Resistance Flatness, RFLAT (On).3 Ω typ V = 3.4 V, VS = V to V Ω max IS = ma LEAKAGE CURRENTS V = 4.2 V Source Off Leakage, IS (Off) ±.2 na typ VS =.6 V/3.9 V, V = 3.9 V/.6 V; see Figure 9 Channel On Leakage, I, IS (On) ±.2 na typ VS = V =.6 V or 3.9 V; see Figure 2 IGITAL INPUTS Input High Voltage, VINH 2. V min Input Low Voltage, VINL.8 V max Input Current, IINL or IINH.5 μa typ VIN = VINL or VINH ±. μa max igital Input Capacitance, CIN 2 pf typ YNAMIC CHARACTERISTICS ton 42 ns typ RL = 5 Ω, CL = 35 pf 5 54 ns max VS =.5 V/ V; see Figure 2 toff 5 ns typ RL = 5 Ω, CL = 35 pf 2 24 ns max VS =.5 V; see Figure 2 Break-Before-Make Time elay, tbbm 7 ns typ RL = 5 Ω, CL = 35 pf ns min VS = VS2 =.5 V; see Figure 22 Charge Injection pc typ VS =.5 V, RS = Ω, CL = nf; see Figure 23 Off Isolation 6 db typ RL = 5 Ω, CL = 5 pf, f = khz; see Figure 24 Channel-to-Channel Crosstalk 2 db typ SA to S2A/SB to S2B, RL = 5 Ω, CL = 5 pf, f = khz; see Figure 27 6 db typ SA to SB/S2A to S2B, RL = 5 Ω, CL = 5 pf, f = khz; see Figure 25 Total Harmonic istortion, TH + N. % typ RL = 32 Ω, f = 2 Hz to 2 khz, VS = 2 V p-p Insertion Loss.3 db typ RL = 5 Ω, CL = 5 pf; see Figure 26 3 db Bandwidth 8 MHz typ RL = 5 Ω, CL = 5 pf; see Figure 26 CS (Off) pf typ C, CS (On) 3 pf typ POWER REQUIREMENTS V = 4.2 V I.3 μa typ igital inputs = V or 4.2 V μa max Guaranteed by design, not production tested. Rev. Page 4 of 6

5 ata Sheet V = 2.7 V to 3.6 V, GN = V, unless otherwise noted. Table 3. Parameter 25 C 4 C to +85 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range to V V On Resistance, RON.4 Ω typ V = 2.7 V, VS = V to V.5.6 Ω max IS = ma; see Figure 8 On-Resistance Match Between Channels, RON.2 Ω typ V = 2.7 V, VS =.6 V.7. Ω max IS = ma On-Resistance Flatness, RFLAT (On).8 Ω typ V = 2.7 V, VS = V to V.25 Ω max IS = ma LEAKAGE CURRENTS V = 3.6 V Source Off Leakage, IS (Off) ±.2 na typ VS =.6 V/3.3 V, V = 3.3 V/.6 V; see Figure 9 Channel On Leakage, I, IS (On) ±.2 na typ VS = V =.6 V or 3.3 V; see Figure 2 IGITAL INPUTS Input High Voltage, VINH.3 V min Input Low Voltage, VINL.8 V max Input Current, IINL or IINH.5 μa typ VIN = VINL or VINH ±. μa max igital Input Capacitance, CIN 2 pf typ YNAMIC CHARACTERISTICS ton 42 ns typ RL = 5 Ω, CL = 35 pf ns max VS =.5 V/ V; see Figure 2 toff 4 ns typ RL = 5 Ω, CL = 35 pf 9 2 ns max VS =.5 V; see Figure 2 Break-Before-Make Time elay, tbbm 24 ns typ RL = 5 Ω, CL = 35 pf ns min VS = VS2 =.5 V; see Figure 22 Charge Injection 85 pc typ VS =.25 V, RS = Ω, CL = nf; see Figure 23 Off Isolation 6 db typ RL = 5 Ω, CL = 5 pf, f = khz; see Figure 24 Channel-to-Channel Crosstalk 2 db typ SA to S2A/SB to S2B, RL = 5 V, CL = 5 pf, f = khz; see Figure 27 6 db typ SA to SB/S2A to S2B, RL = 5 Ω, CL = 5 pf, f = khz; see Figure 25 Total Harmonic istortion, TH + N.3 % typ RL = 32 Ω, f = 2 Hz to 2 khz, VS =.5 V p-p Insertion Loss.3 db typ RL = 5 Ω, CL = 5 pf; see Figure 26 3 db Bandwidth 8 MHz typ RL = 5 Ω, CL = 5 pf; see Figure 26 CS (Off) pf typ C, CS (On) 3 pf typ POWER REQUIREMENTS V = 3.6 V I.3 μa typ igital inputs = V or 3.6 V μa max Guaranteed by design, not production tested. Rev. Page 5 of 6

6 ata Sheet ABSOLUTE MAXIMUM RATINGS TA = 25 C, unless otherwise noted. Table 4. Parameter Rating V to GN.3 V to +6 V Analog Inputs, igital Inputs.3 V to V +.3 V or 3 ma (whichever occurs first) Peak Current, S or 6 ma (pulsed at ms, % duty cycle maximum) Continuous Current, S or 4 ma Operating Temperature Range 4 C to +85 C Storage Temperature Range 65 C to +5 C Junction Temperature 5 C -Lead MSOP, Thermal Impedance θja 26 C/W θjc 44 C/W -Ball WLCSP (4-Layer Board), Thermal Impedance θja 2 C/W -Lead LFCSP_W (4-Layer Board), Thermal Impedance θja 76 C/W θjc 3.5 C/W Reflow Soldering (Pb-Free) Peak Temperature 26(+ or 5) C Time at Peak Temperature sec to 4 sec Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time. ES CAUTION Overvoltages at IN, S, or pins are clamped by internal diodes. Current should be limited to the maximum ratings given. Rev. Page 6 of 6

7 ata Sheet PIN CONFIGURATIONS AN FUNCTION ESCRIPTIONS 2 3 SA 2 3 IN 4 SB 5 TOP VIEW (Not to Scale) S2A IN2 7 S2B 6 GN NOTES. THE LFCSP_W PACKAGE HAS AN EXPOSE PA THAT SHOUL BE TIE TO GROUN. Figure 2. LFCSP_W and MSOP Pin Configuration A B C SB IN 9 SA GN 2 TOP VIEW (Not to Scale) 8 7 S2B IN2 2 (SOLER BALLS ON OPPOSITE SIE) S2A Figure 3. WLCSP Pin Configuration Table 5. LFCSP_W and MSOP Pin Function escriptions Pin No. Mnemonic escription V Most Positive Power Supply Potential. 2 SA Source Terminal. Can be an input or output. 3 rain Terminal. Can be an input or output. 4 IN Logic Control Input. 5 SB Source Terminal. Can be an input or output. 6 GN Ground ( V) Reference. 7 S2B Source Terminal. Can be an input or output. 8 IN2 Login Control Input. 9 2 rain Terminal. Can be an input or output. S2A Source Terminal. Can be an input or output. EPA The LFCSP_W package has an exposed pad that should be tied to ground. Table 6. WLCSP Package Pin Function escription WLCSP Package Ball Number Location Mnemonic escription A SB Source Terminal. Can be an input or output. 2 A2 GN Ground ( V) Reference. 3 A3 S2B Source Terminal. Can be an input or output. 4 B3 IN2 Login Control Input. 5 C3 2 rain Terminal. Can be an input or output. 6 3 S2A Source Terminal. Can be an input or output. 7 2 V Most Positive Power Supply Potential. 8 SA Source Terminal. Can be an input or output. 9 C rain Terminal. Can be an input or output. B IN Logic Control Input. Table 7. Truth Table Logic (IN/IN2) Switch A/Switch 2A Switch B/Switch 2B Off On On Off Rev. Page 7 of 6

8 ata Sheet TYPICAL PERFORMANCE CHARACTERISTICS ON RESISTANCE (Ω) V 5.5V 4.5V 5V T A = 25 C I S = ma ON RESISTANCE (Ω) C +25 C 4 C = 3.3V I S = ma SIGNAL RANGE (V) Figure 4. On Resistance vs. V (VS), V = 4.2 V to 5.5 V SIGNAL RANGE (V) Figure 7. On Resistance vs. V (VS) for ifferent Temperatures, V = 3.3 V T A = 25 C I S = ma 5 4 = 5V ON RESISTANCE (Ω) V 3.3V 3V LEAKAGE CURRENT (na) I, I S (ON) I S (OFF) SIGNAL RANGE (V) Figure 5. On Resistance vs. V (VS), V = 2.7 V to 3.3 V TEMPERATURE ( C) Figure 8. Leakage Current vs. Temperature, V = 5 V = 5V I S = ma 5 4 = 4.2V ON RESISTANCE (Ω) C +25 C 4 C LEAKAGE CURRENT (na) 3 2 I, I S (ON) SIGNAL RANGE (V) Figure 6. On Resistance vs. V (VS) for ifferent Temperature, V = 5 V I S (OFF) TEMPERATURE ( C) Figure 9. Leakage Current vs. Temperature, V = 4.2 V Rev. Page 8 of 6

9 ata Sheet LEAKAGE CURRENT (na) = 3.3V I, I S (ON) ATTENUATION (db) T A = 25 C = 5V/4.2V/3V.5 I S (OFF) TEMPERATURE ( C) Figure. Leakage Current vs. Temperature, V = 3.3 V FREQUENCY (MHz) Figure 3. Bandwidth, V = 5 V/4.2 V/3 V = 5V T A = 25 C T A = 25 C = 5V/4.2V/3V 2 Q INJ (pc) = 4.2V ATTENUATION (db) = 3V (V) Figure. Charge Injection vs. Source Voltage k k k M M M FREQUENCY (MHz) Figure 4. Off Isolation vs. Frequency TIME (ns) T A = 25 C = 5V = 3V t ON t OFF = 5V = 3V ATTENUATION (db) T A = 25 C = 5V/3V TEMPERATURE ( C) k k k M M M FREQUENCY (MHz) Figure 2. ton/toff Times vs. Temperature Figure 5. Crosstalk vs. Frequency Rev. Page 9 of 6

10 ata Sheet ATTENUATION (db) T A = 25 C = 5V/4.2V/3V TH + N (%) = 3V,.5V p-p = 5V, 3.5V p-p 4 6 k k k M M M FREQUENCY (MHz) = 4.2V, 2V p-p FREQUENCY (khz) Figure 6. AC PSRR Figure 7. TH + N Rev. Page of 6

11 ata Sheet TEST CIRCUITS I S V S R ON = V/I S Figure 8. On Resistance I S (OFF) A S I (OFF) A V Figure 9. Off Leakage NC I (ON) S A Figure 2. On Leakage V µF SB SA V IN 5% 5% IN RL 5Ω C L 35pF 9% 9% GN t ON t OFF Figure 2. Switching Times, ton, toff.µf SB SA V IN V 8% 5% 5% 8% IN R L 5Ω C L 35pF t BBM t BBM GN Figure 22. Break-Before-Make Time elay, tbbm Rev. Page of 6

12 ata Sheet SW ON SW OFF SB SA NC V IN IN nf GN Q INJ = C L Figure 23. Charge Injection.µF.µF NETWORK ANALYZER NETWORK ANALYZER NC SB SA 5Ω 5Ω SB SA 5Ω GN R L 5Ω GN R L 5Ω OFF ISOLATION = 2 LOG WITH SWITCH INSERTION LOSS = 2 LOG WITHOUT SWITCH Figure 24. Off Isolation Figure 26. Bandwidth.µF R L 5Ω 5Ω SA SB GN R L 5Ω NETWORK ANALYZER 5Ω 5Ω S2A S2B SA SB 2 NC NC 5Ω CHANNEL-TO-CHANNEL CROSSTALK = 2 LOG CHANNEL-TO-CHANNEL CROSSTALK = 2 LOG Figure 25. Channel-to-Channel Crosstalk (SA to SB) Figure 27. Channel-to-Channel Crosstalk (SA to S2A) Rev. Page 2 of 6

13 ata Sheet TERMINOLOGY I Positive supply current. V (VS) Analog voltage on Terminal and Terminal S. RON Ohmic resistance between Terminal and Terminal S. RFLAT (On) The difference between the maximum and minimum values of on resistance as measured on the switch. ΔRON On resistance match between any two channels. IS (Off) Source leakage current with the switch off. I (Off) rain leakage current with the switch off. I, IS (On) Channel leakage current with the switch on. VINL Maximum input voltage for Logic. VINH Minimum input voltage for Logic. IINL (IINH) Input current of the digital input. CS (Off) Off switch source capacitance. Measured with reference to ground. C (Off) Off switch drain capacitance. Measured with reference to ground. C, CS (On) On switch capacitance. Measured with reference to ground. CIN igital input capacitance. ton elay time between the 5% and 9% points of the digital input and switch on condition. toff elay time between the 5% and 9% points of the digital input and switch off condition. tbbm On or off time measured between the 8% points of both switches when switching from one to another. Charge Injection Measure of the glitch impulse transferred from the digital input to the analog output during on/off switching. Off Isolation Measure of unwanted signal coupling through an off switch. Crosstalk Measure of unwanted signal that is coupled from one channel to another as a result of parasitic capacitance. 3 db Bandwidth Frequency at which the output is attenuated by 3 db. On Response Frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. Total Harmonic istortion + Noise (TH + N) Ratio of the harmonics amplitude plus noise of a signal to the fundamental. Rev. Page 3 of 6

14 ata Sheet OUTLINE IMENSIONS 3. BSC SQ BSC 6 PIN INEX AREA TOP VIEW.8 MAX.55 NOM MAX.2 NOM 5 EXPOSE PA (BOTTOM VIEW) PIN INICATOR (R.2) SEATING PLANE.2 REF Figure 28. -Lead Lead Frame Chip Scale Package [LFCSP_W] 3 mm x 3 mm Body, Very Very Thin, ual Lead (CP--9) imensions shown in millimeters 328-B PIN.5 BSC COPLANARITY.. MAX SEATING PLANE COMPLIANT TO JEEC STANARS MO-87-BA Figure 29. -Lead Mini Small Outline Package [MSOP] (RM-) imensions shown in millimeters Rev. Page 4 of 6

15 ata Sheet SEATING PLANE 3 2 BALL IENTIFIER BSC BALL PITCH A B C TOP VIEW (BALL SIE OWN) Figure 3. -Ball Wafer Level Chip Scale Package [WLCSP] (CB-) imensions shown in millimeters BOTTOM VIEW (BALL SIE UP) 867-A ORERING GUIE Model Temperature Range Package escription Package Option Branding 2 BRMZ 4 C to +85 C -Lead Mini Small Outline Package [MSOP] RM- S9C BRMZ-REEL 4 C to +85 C -Lead Mini Small Outline Package [MSOP] RM- S9C BRMZ-REEL7 4 C to +85 C -Lead Mini Small Outline Package [MSOP] RM- S9C BCPZ-REEL 4 C to +85 C -Lead Lead Frame Chip Scale Package [LFCSP_W] CP--9 S9C BCPZ-REEL7 4 C to +85 C -Lead Lead Frame Chip Scale Package [LFCSP_W] CP--9 S9C BCBZ-REEL 4 C to +85 C -Ball Wafer Level Chip Scale Package [WLCSP] CB- S9C BCBZ-REEL7 4 C to +85 C -Ball Wafer Level Chip Scale Package [WLCSP] CB- S9C EVAL-EBZ Evaluation Board Z = RoHS Compliant Part. 2 Branding on this package is limited to three characters due to space constraints. Rev. Page 5 of 6

0.5 Ω CMOS 1.65 V to 3.6 V Dual SPDT/2:1 Mux in Mini LFCSP Package ADG824

0.5 Ω CMOS 1.65 V to 3.6 V Dual SPDT/2:1 Mux in Mini LFCSP Package ADG824 ata Sheet.5 Ω CMOS.65 V to 3.6 V ual SPT/2: Mux in Mini LFCSP Package FEATURES.5 Ω typical on resistance.85 Ω maximum on resistance at 85 C.65 V to 3.6 V operation High current carrying capability: 3 ma