High Voltage Latch-Up Proof, Single SPDT Switch ADG5419

Transcription

1 ata Sheet FEATURES Latch-up immune under all circumstances Human body model (HBM) ES rating: 8 kv Low on resistance: 13.5 Ω ±9 V to ±22 V dual-supply operation 9 V to 4 V single-supply operation 48 V supply maximum ratings Fully specified at ±15 V, ±2 V, +12 V, and +36 V V to VSS analog signal range APPLICATIONS High voltage signal routing Automatic test equipment Analog front-end circuits Precision data acquisition Industrial instrumentation Amplifier gain select Relay replacement High Voltage Latch-Up Proof, Single SPT Switch FUNCTIONAL BLOCK IAGRAMS ECOER EN SWITCHES SHOWN FOR A LOGIC PUT. Figure 1. 8-Lead LFCSP SWITCHES SHOWN FOR A LOGIC PUT. Figure 2. 8-Lead MSOP GENERAL ESCRIPTION The is a monolithic industrial, complementary metal oxide semiconductor (CMOS) analog switch containing a latchup immune single-pole/double-throw (SPT) switch. Each switch conducts equally well in both directions when on, and each switch has an input signal range that extends to the power supplies. In the off condition, signal levels up to the supplies are blocked. The exhibits break-before-make switching action for use in multiplexer applications. The ultralow on resistance and on-resistance flatness of these switches make them ideal solutions for data acquisition and gain switching applications where low distortion is critical. The latch-up immune construction and high ES rating make these switches more robust in harsh environments. PROUCT HIGHLIGHTS 1. Trench isolation guards against latch-up. A dielectric trench separates the P channel and N channel transistors, thereby preventing latch-up even under severe overvoltage conditions. 2. Low RON of 13.5 Ω. 3. ual-supply operation. For applications where the analog signal is bipolar, the can be operated from dual supplies up to ±22 V. 4. Single-supply operation. For applications where the analog signal is unipolar, the can be operated from a single-rail power supply up to 4 V V logic compatible digital inputs: VH = 2. V, VL =.8 V. 6. No VL logic power supply required. 7. Available in 8-lead MSOP and 8-lead, 2 mm 3 mm LFCSP packages. Rev. A ocument Feedback Information furnished by Analog evices is believed to be accurate and reliable. However, no responsibility is assumed by Analog evices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog evices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 916, Norwood, MA , U.S.A. Tel: Analog evices, Inc. All rights reserved. Technical Support

2 TABLE OF CONTENTS Features... 1 Applications... 1 Functional Block iagrams... 1 General escription... 1 Product Highlights... 1 Revision History... 2 Specifications... 3 ±15 V ual Supply... 3 ±2 V ual Supply ingle Supply ingle Supply... 6 ata Sheet Continuous Current per Channel, Sx or...7 Absolute Maximum Ratings...8 ES Caution...8 Pin Configurations and Function escriptions...9 Typical Performance Characteristics... 1 Test Circuits Terminology Applications Information Trench Isolation Outline imensions Ordering Guide REVISION HISTORY 3/15 Rev. to Rev. A Added 8-Lead LFCSP... Universal Added Figure 1; Renumbered Sequentially... 1 Changes to Table Changes to Table Changes to Table Changes to Table Changed Continuous Current, Sx or to 8-Lead MSOP, Table Added Figure 3 and Table 8; Renumbered Sequentially... 9 Changes to Table Changes to Figure Added Figure Changes to Figure 24 Caption Added Figure 25 and Figure eleted Figure 27; Renumbered Sequentially Added Figure 32 and Figure Changes to Terminology Section Added Figure 37, Outline imensions Changes to Ordering Guide /13 Revision : Initial Version Rev. A Page 2 of 19

3 ata Sheet SPECIFICATIONS ±15 V UAL SUPPLY V = +15 V ± 1%, VSS = 15 V ± 1%, GN = V, unless otherwise noted. Table 1. Parameter 25 C 4 C to +85 C 4 C to +125 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V to VSS V On Resistance, RON 13.5 Ω typ VS = ±1 V, IS = 1 ma; see Figure Ω max V = V, VSS = 13.5 V On-Resistance Match Between Channels,.1 Ω typ VS = ±1 V, IS = 1 ma RON Ω max On-Resistance Flatness, RFLAT (ON) 1.8 Ω typ VS = ±1 V, IS = 1 ma Ω max LEAKAGE CURRENTS V = V, VSS = 16.5 V Source Off Leakage, IS (Off) ±.1 na typ VS = ±1 V, V = 1 V; see Figure 24 and Figure 25 ±.25 ±1 ±1 na max rain Off Leakage, I (Off) ±.1 na typ VS = ±1 V, V = 1 V; see Figure 25 ±.4 ±4 ±1 na max Channel On Leakage, I (On), IS (On) ±.1 na typ VS = V = ±1 V; see Figure 24 and Figure 26 ±.4 ±4 ±1 na max IGITAL PUTS Input High Voltage, VH 2. V min Input Low Voltage, VL.8 V max Input Current, IL or IH.2 μa typ V = VGN or V ±.1 μa max igital Input Capacitance, C 6 pf typ YNAMIC CHARACTERISTICS 1 Transition Time, ttransition 217 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 1 V; see Figure 32 ton (EN) 179 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 1 V; see Figure 33 toff (EN) 153 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 1 V; see Figure 33 Break-Before-Make Time elay, t 86 ns typ RL = 3 Ω, CL = 35 pf 45 ns min VS = 1 V; see Figure 34 Charge Injection, QJ 13 pc typ VS = V, RS = Ω, CL = 1 nf; see Figure 35 Off Isolation 6 db typ RL = 5 Ω, CL = 5 pf, f = 1 MHz; see Figure 29 Channel-to-Channel Crosstalk 8 db typ RL = 5 Ω, CL = 5 pf, f = 1 MHz; see Figure 28 Total Harmonic istortion + Noise.1 % typ RL = 1 kω, 15 V p-p, f = 2 Hz to 2 khz; see Figure 3 3 db Bandwidth 19 MHz typ RL = 5 Ω, CL = 5 pf; see Figure 31 Insertion Loss.8 db typ RL = 5 Ω, CL = 5 pf, f = 1 MHz; see Figure 31 CS (Off) 12 pf typ VS = V, f = 1 MHz C (Off) 23 pf typ VS = V, f = 1 MHz C (On), CS (On) 55 pf typ VS = V, f = 1 MHz POWER REQUIREMENTS V = V, VSS = 16.5 V I 45 μa typ igital inputs = V or V 55 7 μa max ISS.1 μa typ igital inputs = V or V 1 μa max V/VSS ±9/±22 V min/v max GN = V 1 Guaranteed by design; not subject to production test. Rev. A Page 3 of 19

4 ata Sheet ±2 V UAL SUPPLY V = +2 V ± 1%, VSS = 2 V ± 1%, GN = V, unless otherwise noted. Table 2. Parameter 25 C 4 C to +85 C 4 C to +125 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V to VSS V On Resistance, RON 12.5 Ω typ VS = ±15 V, IS = 1 ma; see Figure Ω max V = +18 V, VSS = 18 V On-Resistance Match Between Channels,.1 Ω typ VS = ±15 V, IS = 1 ma RON Ω max On-Resistance Flatness, RFLAT (ON) 2.3 Ω typ VS = ±15 V, IS = 1 ma Ω max LEAKAGE CURRENTS V = +22 V, VSS = 22 V Source Off Leakage, IS (Off) ±.1 na typ VS = ±15 V, V = 15 V; see Figure 24 and Figure 25 ±.25 ±1 ±1 na max rain Off Leakage, I (Off) ±.1 na typ VS = ±15 V, V = 15 V; see Figure 25 ±.4 ±4 ±1 na max Channel On Leakage, I (On), IS (On) ±.1 na typ VS = V = ±15 V; see Figure 24 and Figure 26 ±.4 ±4 ±1 na max IGITAL PUTS Input High Voltage, VH 2. V min Input Low Voltage, VL.8 V max Input Current, IL or IH.2 μa typ V = VGN or V ±.1 μa max igital Input Capacitance, C 6 pf typ YNAMIC CHARACTERISTICS 1 Transition Time, ttransition 2 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 1 V; see Figure 32 ton (EN) 199 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 1 V; see Figure 33 toff (EN) 157 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 1 V; see Figure 33 Break-Before-Make Time elay, t 77 ns typ RL = 3 Ω, CL = 35 pf 46 ns min VS = 1 V; see Figure 34 Charge Injection, QJ 16 pc typ VS = V, RS = Ω, CL = 1 nf; see Figure 35 Off Isolation 6 db typ RL = 5 Ω, CL = 5 pf, f = 1 MHz; see Figure 29 Channel-to-Channel Crosstalk 8 db typ RL = 5 Ω, CL = 5 pf, f = 1 MHz; see Figure 28 Total Harmonic istortion + Noise.1 % typ RL = 1 kω, 2 V p-p, f = 2 Hz to 2 khz; see Figure 3 3 db Bandwidth 19 MHz typ RL = 5 Ω, CL = 5 pf; see Figure 31 Insertion Loss.7 db typ RL = 5 Ω, CL = 5 pf, f = 1 MHz; see Figure 31 CS (Off) 11 pf typ VS = V, f = 1 MHz C (Off) 22 pf typ VS = V, f = 1 MHz C (On), CS (On) 55 pf typ VS = V, f = 1 MHz POWER REQUIREMENTS V = +22 V, VSS = 22 V I 5 μa typ igital inputs = V or V 7 11 μa max ISS.1 μa typ igital inputs = V or V 1 μa max V/VSS ±9/±22 V min/v max GN = V 1 Guaranteed by design; not subject to production test. Rev. A Page 4 of 19

5 ata Sheet 12 GLE SUPPLY V = 12 V ± 1%, VSS = V, GN = V, unless otherwise noted. Table 3. Parameter 25 C 4 C to +85 C 4 C to +125 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V to V V On Resistance, RON 26 Ω typ VS = V to 1 V, IS = 1 ma; see Figure Ω max V = 1.8 V, VSS = V On-Resistance Match Between Channels,.1 Ω typ VS = V to 1 V, IS = 1 ma RON Ω max On-Resistance Flatness, RFLAT (ON) 5.5 Ω typ VS = V to 1 V, IS = 1 ma Ω max LEAKAGE CURRENTS V = V, VSS = V Source Off Leakage, IS (Off) ±.1 na typ VS = 1 V to 1 V, V = 1 V to 1 V; see Figure 24 and Figure 25 ±.25 ±1 ±1 na max rain Off Leakage, I (Off) ±.1 na typ VS = 1V to1 V, V = 1 V to 1V; see Figure 25 ±.4 ±4 ±1 na max Channel On Leakage, I (On), IS (On) ±.1 na typ VS = V = 1 V to 1 V; see Figure 24 and Figure 26 ±.4 ±4 ±1 na max IGITAL PUTS Input High Voltage, VH 2. V min Input Low Voltage, VL.8 V max Input Current, IL or IH.2 μa typ V = VGN or V ±.1 μa max igital Input Capacitance, C 6 pf typ YNAMIC CHARACTERISTICS 1 Transition Time, ttransition 333 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 8 V; see Figure 32 ton (EN) 327 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 8 V; see Figure 33 toff (EN) 166 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 8 V; see Figure 33 Break-Before-Make Time elay, t 176 ns typ RL = 3 Ω, CL = 35 pf 97 ns min VS = 8 V; see Figure 34 Charge Injection, QJ 55 pc typ VS = 6 V, RS = Ω, CL = 1 nf; see Figure 35 Off Isolation 6 db typ RL = 5 Ω, CL = 5 pf, f = 1 MHz; see Figure 29 Channel-to-Channel Crosstalk 8 db typ RL = 5 Ω, CL = 5 pf, f = 1 MHz; see Figure 28 Total Harmonic istortion + Noise.3 % typ RL = 1 kω, 6 V p-p, f = 2 Hz to 2 khz; see Figure 3 3 db Bandwidth 17 MHz typ RL = 5 Ω, CL = 5 pf; see Figure 31 Insertion Loss 1.7 db typ RL = 5 Ω, CL = 5 pf, f = 1 MHz; see Figure 31 CS (Off) 15 pf typ VS = 6 V, f = 1 MHz C (Off) 29 pf typ VS = V, f = 1 MHz C (On), CS (On) 5 pf typ VS = 6 V, f = 1 MHz POWER REQUIREMENTS V = 13.2 V I 4 μa typ igital inputs = V or V 5 65 μa max V 9/4 V min/v max GN = V, VSS = V 1 Guaranteed by design; not subject to production test. Rev. A Page 5 of 19

6 ata Sheet 36 GLE SUPPLY V = 36 V ± 1%, VSS = V, GN = V, unless otherwise noted. Table 4. Parameter 25 C 4 C to +85 C 4 C to +125 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V to V V On Resistance, RON 14.5 Ω typ VS = V to 3 V, IS = 1 ma; see Figure Ω max V = 32.4 V, VSS = V On-Resistance Match Between Channels,.1 Ω typ VS = V to 3 V, IS = 1 ma RON Ω max On-Resistance Flatness, RFLAT (ON) 3.5 Ω typ VS = V to 3 V, IS = 1 ma Ω max LEAKAGE CURRENTS V = 39.6 V, VSS = V Source Off Leakage, IS (Off) ±.1 na typ VS = 1 V to 3 V, V = 3 V to 1 V; see Figure 24 and Figure 25 ±.25 ±1 ±1 na max rain Off Leakage, I (Off) ±.1 na typ VS = 1V to 3 V, V = 3 V to 1V; see Figure 25 ±.4 ±4 ±1 na max Channel On Leakage, I (On), IS (On) ±.1 na typ VS = V = 1 V to 3 V; see Figure 24 and Figure 26 ±.4 ±4 ±1 na max IGITAL PUTS Input High Voltage, VH 2. V min Input Low Voltage, VL.8 V max Input Current, IL or IH.2 μa typ V = VGN or V ±.1 μa max igital Input Capacitance, C 6 pf typ YNAMIC CHARACTERISTICS 1 Transition Time, ttransition 216 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 18 V; see Figure 32 ton (EN) 199 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 18 V; see Figure 33 toff (EN) 16 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 18 V; see Figure 33 Break-Before-Make Time elay, t 8 ns typ RL = 3 Ω, CL = 35 pf 47 ns min VS = 18 V; see Figure 34 Charge Injection, QJ 135 pc typ VS = 18 V, RS = Ω, CL = 1 nf; see Figure 35 Off Isolation 6 db typ RL = 5 Ω, CL = 5 pf, f = 1 MHz; see Figure 29 Channel-to-Channel Crosstalk 8 db typ RL = 5 Ω, CL = 5 pf, f = 1 MHz; see Figure 28 Total Harmonic istortion + Noise.1 % typ RL = 1 kω, 18 V p-p, f = 2 Hz to 2 khz; see Figure 3 3 db Bandwidth 17 MHz typ RL = 5 Ω, CL = 5 pf; see Figure 31 Insertion Loss 1 db typ RL = 5 Ω, CL = 5 pf, f = 1 MHz; see Figure 31 CS (Off) 14 pf typ VS = 18 V, f = 1 MHz C (Off) 26 pf typ VS = V, f = 1 MHz C (On), CS (On) 5 pf typ VS = 18 V, f = 1 MHz POWER REQUIREMENTS V = 39.6 V I 8 μa typ igital inputs = V or V 1 13 μa max V 9/4 V min/v max GN = V, VSS = V 1 Guaranteed by design; not subject to production test. Rev. A Page 6 of 19

7 ata Sheet CONTUOUS CURRENT PER CHANNEL, Sx OR Table 5. Parameter 25 C 85 C 125 C Unit Test Conditions/Comments 8-LEA MSOP θja = C/W V = 15 V, VSS = 15 V ma maximum V = 2 V, VSS = 2 V ma maximum V = 12 V, VSS = V ma maximum V = 36 V, VSS = V ma maximum 8-LEA LFCSP θja = 6.88 C/W V = 15 V, VSS = 15 V ma maximum V = 2 V, VSS = 2 V ma maximum V = 12 V, VSS = V ma maximum V = 36 V, VSS = V ma maximum Rev. A Page 7 of 19

8 ABSOLUTE MAXIMUM RATGS TA = 25 C, unless otherwise noted. Table 6. Parameter Rating V to VSS 48 V V to GN.3 V to +48 V VSS to GN +.3 V to 48 V Analog Inputs 1 VSS.3 V to V +.3 V or 3 ma, whichever occurs first igital Inputs 1 VSS.3 V to V +.3 V or 3 ma, whichever occurs first Peak Current, Sx or Pins 41 ma (pulsed at 1 ms, 1% duty cycle maximum) Continuous Current, Sx or 2 ata + 15% Temperature Range Operating 4 C to +125 C Storage 65 C to +15 C Junction Temperature 15 C Thermal Impedance, θja 8-Lead MSOP (4-Layer Board) C/W 8-Lead LFCSP 6.88 C/W Reflow Soldering Peak As per JEEC J-ST-2 Temperature, Pb Free Human Body Model (HBM) ES 8 kv 1 Overvoltages at the, Sx, and pins are clamped by internal diodes. Limit current to the maximum ratings given. 2 See Table 5. ata Sheet Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ES CAUTION Rev. A Page 8 of 19

9 ata Sheet P CONFIGURATIONS AN FUNCTION ESCRIPTIONS GN 3 V 4 TOP VIEW (Not to Scale) 7 S 6 5 EN 1 2 GN 3 V 4 TOP VIEW (Not to Scale) S NC NOTES 1. EXPOSE PA TIE TO SUBSTRATE, S. Figure 3. 8-Lead LFCSP Pin Configuration NOTES 1. NC = NO CONNECT. NOT TERNALLY CONNECTE. Figure 4. 8-Lead MSOP Pin Configuration Table 7. Pin Function escriptions Pin No. LFCSP MSOP Mnemonic escription 1 1 rain Terminal. This pin can be an input or output. 2 2 Source Terminal. This pin can be an input or an output. 3 3 GN Ground ( V) Reference. 4 4 V Most Positive Power Supply Potential. 5 EN Active High igital Input. When this pin is low, the device is disabled and all switches are turned off. When this pin is high, the logic input determines the state of the switch. 6 6 Logic Control Input. 7 7 VSS Most Negative Power Supply Potential. 8 8 Source Terminal. This pin can be an input or an output. 5 NC No Connect. Not internally connected. Not applicable EPA Exposed Pad. Exposed pad tied to substrate, VSS. Table 8. LFCSP Truth Table EN Switch A Switch B X 1 Off Off 1 On Off 1 1 Off On 1 X = don t care. Table 9. MSOP Truth Table Switch A Switch B On Off 1 Off On Rev. A Page 9 of 19

10 ata Sheet TYPICAL PERFORMANCE CHARACTERISTICS ON RESISTANCE (Ω) T A = 25 C V = +11V S = 11V V = +9V S = 9V V = +13.5V S = 13.5V V = +15V V = +16.5V S = 15V S = 16.5V V = +1V S = 1V ON RESISTANCE (Ω) T A = 25 C V = 32.4V S = V V = 36V S = V V = 39.6V S = V , V (V) , V (V) Figure 5. On Resistance as a Function of VS, V ual Supply Figure 8. On Resistance as a Function of VS, V (Single Supply) 16 T A = 25 C ON RESISTANCE (Ω) V = +18V S = 18V V = +2V S = 2V V = +22V S = 22V ON RESISTANCE (Ω) T A = +125 C T A = +85 C T A = +25 C T A = 4 C , V (V) V = +15V S = 15V , V (V) Figure 6. On Resistance as a Function of VS, V ual Supply) Figure 9. On Resistance as a Function of VS (V) for ifferent Temperatures, ±15 V ual Supply ON RESISTANCE (Ω) T A = 25 C V = 9V S = V V = 1V S = V V = 13.2V S = V V = 1.8V S = V V = 12V S = V V =11V S = V ON RESISTANCE (Ω) V = +2V S = 2V T A = +125 C T A = +85 C T A = +25 C T A = 4 C , V (V) Figure 7. On Resistance as a Function of VS, V (Single Supply) , V (V) Figure 1. On Resistance as a Function of VS (V) for ifferent Temperatures, ±2 V ual Supply Rev. A Page 1 of 19

11 ata Sheet ON RESISTANCE (Ω) T A = +125 C T A = +85 C T A = +25 C T A = 4 C 5 V = 12V S = V , V (V) Figure 11. On Resistance as a Function of VS (V) for ifferent Temperatures, 12 ingle Supply ON RESISTANCE (Ω) V = 36V S = V T A = +125 C T A = +85 C T A = +25 C T A = 4 C , V (V) Figure 12. On Resistance as a Function of VS (V) for ifferent Temperatures, 36 ingle Supply LEAKAGE CURRENT (na) LEAKAGE CURRENT (na) TEMPERATURE ( C) Figure 14. Leakage Currents as a Function of Temperature, ±2 V ual Supply.1 V = +2V S = 2V V BIAS = +15V/ 15V V = 12V S = V V BIAS = 1V/1V I (OFF) + I, I S (ON) I S (OFF) + I (OFF) + I, I S (ON) + + I S (OFF) + I S (OFF) + I (OFF) + I (OFF) TEMPERATURE ( C) I, I S (ON) + + I, I S (ON) I S (OFF) + Figure 15. Leakage Currents as a Function of Temperature, 12 ingle Supply V = +15V S = 15V V BIAS = +1V/ 1V.4 V = 36V S = V V BIAS = 1V/3V I, I S (ON) + + LEAKAGE CURRENT (na) I, I S (ON) + + I S (OFF) + I (OFF) + I, I S (ON) I S (OFF) + I (OFF) + LEAKAGE CURRENT (na) I, I S (ON) I S (OFF) + I S (OFF) + I (OFF) + I (OFF) TEMPERATURE ( C) Figure 13. Leakage Currents as a Function of Temperature, ±15 V ual Supply TEMPERATURE ( C) Figure 16. Leakage Currents as a Function of Temperature, 36 ingle Supply Rev. A Page 11 of 19

12 ata Sheet OFF ISOLATION (db) T A = 25 C 1 V = +15V S = 15V TH + N (%) T A = 25 C R L = 1kΩ V =12V,S =V, =6V p-p V =36V,S =V, =18V p-p V =15V,S = 15V, =15V p-p V =2V,S = 2V, =2V p-p k 1k 1k 1M 1M 1M 1G FREQUENCY (Hz) Figure 17. Off Isolation vs. Frequency FREQUENCY (khz) Figure 2. TH + N vs. Frequency T A = 25 C V = +15V S = 15V.5 1. T A = 25 C V = +15V S = 15V CROSSTALK (db) SERTION LOSS (db) k 1k 1M 1M 1M 1G FREQUENCY (Hz) Figure 18. Crosstalk vs. Frequency k 1k 1k 1M 1M 1M 1G FREQUENCY (Hz) Figure 21. Bandwidth CHARGE JECTION (pc) V =15V,S = 15V V =2V,S = 2V V =12V,S =V V =36V,S =V TIME (ns) V =12V,S =V V =36V,S =V V =15V,S = 15V V =2V,S = 2V (V) Figure 19. Charge Injection vs. Source Voltage TEMPERATURE ( C) Figure 22. ttransition Times vs. Temperature Rev. A Page 12 of 19

13 ata Sheet ACPSRR (db) T A = 25 C V = +15V S = 15V NO ECOUPLG CAPACITORS ECOUPLG CAPACITORS 12 1k 1k 1k 1M 1M FREQUENCY (Hz) Figure 23. ACPSRR vs. Frequency Rev. A Page 13 of 19

14 ata Sheet TEST CIRCUITS NC A I S (OFF) VS I (ON) A V Figure 24. Channel On and Source Off Leakage (MSOP Only) V Sx R ON = V/I S Figure 27. On Resistance I S S.1µFV.1µF I S (OFF) A A I (OFF) A NETWORK ANALYZER R L 5Ω V GN S R 5Ω V Figure 25. Off Leakage (LFCSP Only) CHANNEL-TO-CHANNEL CROSSTALK = 2 log Figure 28. Channel-to-Channel Crosstalk S.1µFV.1µF V S NC NETWORK ANALYZER 5Ω NC I (ON) A V GN 5Ω R L 5Ω V Figure 26. On Leakage (LFCSP Only) OFF ISOLATION = 2 log Figure 29. Off Isolation Rev. A Page 14 of 19

15 ata Sheet V S.1µFV.1µF V Sx GN S R L 1kΩ AUIO PRECISION R S V p-p V S.1µFV.1µF V GN S NC 5Ω NETWORK ANALYZER 5Ω R L 5Ω V SERTION LOSS = 2 log OUT WITH SWITCH WITHOUT SWITCH Figure 3. TH + Noise Figure 31. Bandwidth V.1µF S.1µF V ( = ) 5% 5% V * * S V ( = ) 5% 5% V GN R L 3Ω C L 35pF V.9.1 t TRANSITION *ALTERNATIVELY, CAN BE CONNECTE TO WITH CONNECTE TO GROUN. t TRANSITION Figure 32. Transition Time, ttransition V S 3V V S ENABLE RIVE (V EN ) V 5% 5% OUTPUT ( ) t ON (EN).9 t OFF (EN) V EN 5Ω EN GN 3Ω 35pF V Figure 33. Enable elay, ton (EN), toff (EN) (LFCSP Only) Rev. A Page 15 of 19

16 ata Sheet V.1µF S.1µF V S V R L 3Ω C L 35pF 8% V GN t t Figure 34. Break-Before-Make elay, t V.1µF S.1µF V S V (NORMALLY CLOSE SWITCH) ON OFF V GN C L 1nF NC V (NORMALLY OPEN SWITCH) Q J =C L Figure 35. Charge Injection Rev. A Page 16 of 19

17 ata Sheet TERMOLOGY I I represents the positive supply current. ISS ISS represents the negative supply current. V, VS V and VS represent the analog voltage on Terminal and Terminal S, respectively. RON RON is the ohmic resistance between Terminal and Terminal S. ΔRON ΔRON represents the difference between the RON of any two channels. RFLAT (ON) The difference between the maximum and minimum value of on resistance as measured over the specified analog signal range is represented by RFLAT (ON). IS (Off) IS (Off) is the source leakage current with the switch off. I (Off) I (Off) is the drain leakage current with the switch off. I (On), IS (On) I (On) and IS (On) represent the channel leakage currents with the switch on. VL VL is the maximum input voltage for Logic. VH VH is the minimum input voltage for Logic 1. IL, IH IL and IH represent the low and high input currents of the digital inputs. C (Off) C (Off) represents the off switch drain capacitance, which is measured with reference to ground. CS (Off) CS (Off) represents the off switch source capacitance, which is measured with reference to ground. C (On), CS (On) C (On) and CS (On) represent on switch capacitances, which are measured with reference to ground. C C represents digital input capacitance. ton (EN) ton represents the delay time between the 5% and 9% points of the digital input and switch on condition. See Figure 33. toff (EN) toff represents the delay time between the 5% and 9% points of the digital input and switch off condition. See Figure 33. ttransition ttransition represents the delay time between the 5% and 9% points of the digital inputs and the switch on condition when switching from one address state to another. t t represents the off time measured between the 8% point of both switches when switching from one address state to another. Off Isolation Off isolation is a measure of unwanted signal coupling through an off channel. Charge Injection Charge injection is a measure of the glitch impulse transferred from the digital input to the analog output during switching. Crosstalk Crosstalk is a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Bandwidth Bandwidth is the frequency at which the output is attenuated by 3 db, from its dc level. Total Harmonic istortion + Noise (TH + N) TH + N is the ratio of the harmonic amplitude plus noise of the signal to the fundamental. AC Power Supply Rejection Ratio (ACPSRR) ACPSRR measures the ability of a device to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of.62 V p-p. The ratio of the amplitude of signal on the output to the amplitude of the modulation is the ACPSRR. See Figure 23. Rev. A Page 17 of 19

18 ata Sheet APPLICATIONS FORMATION The AG54xx family of switches and multiplexers provide a robust solution for instrumentation, industrial, aerospace, and other harsh environments that are prone to latch-up, which is an undesirable high current state that can lead to device failure and persists until the power supply is turned off. The high voltage switch allows single-supply operation from 9 V to 4 V and dual-supply operation from ±9 V to ±22 V. The (as well as other select devices within this family) achieves an 8 kv human body model ES rating, which provides a robust solution, eliminating the need for separate protection circuitry designs in some applications. TRENCH ISOLATION In the, an insulating oxide layer (trench) is placed between the NMOS and the PMOS transistors of each CMOS switch. Parasitic junctions, which occur between the transistors in junction-isolated switches, are eliminated, and the result is a completely latch-up immune switch. In junction isolation, the N and P wells of the PMOS and NMOS transistors form a diode that is reverse-biased under normal operation. However, during overvoltage conditions, this diode can become forward-biased. The two transistors form a silicon-controlled rectifier (SCR) type circuit, causing a significant amplification of the current that, in turn, leads to latch-up. With trench isolation, this diode is removed, and the result is a latch-up immune switch. TRENCH NMOS PMOS P-WELL N-WELL BURIE OXIE LAYER HANLE WAFER Figure 36. Trench Isolation Rev. A Page 18 of 19

19 ata Sheet OUTLE IMENSIONS 2. BSC SEATG PLANE EX AREA.5 TOP VIEW SIE VIEW BSC.2 M REF COPLANARITY.8.5 MAX.2 NOM EXPOSE PA BOTTOM VIEW Figure Lead Lead Frame Chip Scale Package [LFCSP_W] 2 mm 3 mm Body, Very Very Thin, ual Lead (CP-8-4) imensions shown in millimeters P 1 ICATOR FOR PROPER CONNECTION OF THE EXPOSE PA, REFER TO THE P CONFIGURATION AN FUNCTION ESCRIPTIONS SECTION OF THIS ATA SHEET A P 1 IENTIFIER.65 BSC COPLANARITY MAX 6 15 MAX.23.9 COMPLIANT TO JEEC STANARS MO-187-AA Figure Lead Mini Small Outline Package [MSOP] (RM-8) imensions shown in millimeters B ORERG GUIE Model 1 Temperature Range Package escription Package Option Branding BCPZ-RL7 4 C to +125 C 8-Lead Lead Frame Chip Scale Package [LFCSP_W] CP-8-4 BL BRMZ 4 C to +125 C 8-Lead Mini Small Outline Package [MSOP] RM-8 S48 BRMZ-RL7 4 C to +125 C 8-Lead Mini Small Outline Package [MSOP] RM-8 S48 1 Z = RoHS Compliant Part Analog evices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners /15(A) Rev. A Page 19 of 19