PART MAX4503CPA MAX4503CSA. Pin Configurations 1 5 V+ COM N.C. V+ 4 MAX4504 MAX4503 DIP/SO

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1 9-064; Rev ; /07 Low-Voltage, Dual-Supply, SPST, General Description The are low-voltage, dual-supply, single-pole/single-throw (SPST), CMOS analog switches. The is normally open (NO). The is normally closed (NC). These CMOS switches can operate continuously with dual supplies between ±.V and ±6V. Each switch can handle rail-to-rail analog signals. The off-leakage current is only na at +25 C or 0nA at +85 C. The digital input is CMOS-logic compatible when using ±5V supplies. A unique logic input architecture allows this even though the parts have no ground pin. For single-supply operation, use the MAX450/ MAX4502, which are pin-for-pin equivalents. Applications Battery-Operated Equipment Audio and Video Signal Routing Low-Voltage Data-Acquisition Systems Communications Circuits Cellular Phones PCMCIA Cards Modems Features Available in SOT23-5 Package Dual-Supply Operation from ±V to ±6V Guaranteed On-Resistance: 2 with ±5V Supplies Guaranteed Low Off-Leakage Currents: na at +25 C 0nA at +85 C Guaranteed Low On-Leakage Currents: 2nA at +25 C 20nA at +85 C Guaranteed Low Charge Injection: 0pC Max Fast Switching Speed: t ON = 50ns, t OFF = 00ns CMOS-Logic Compatible Input Ordering Information PART CPA CSA CUK TEMP RANGE 0 C to +70 C 0 C to +70 C 0 C to +70 C P-PACKAGE 8 Plastic DIP 8 SO 5 SOT23-5 C/D 0 C to +70 C Dice* EPA -40 C to +85 C 8 Plastic DIP ESA -40 C to +85 C 8 SO EUK -40 C to +85 C 5 SOT23-5 MJA -55 C to +25 C 8 CERDIP** Ordering Information continued at end of data sheet. *Contact factory for dice specifications. **Contact factory for availability. Pin Configurations TOP VIEW 8 NO 8 NC 5 5 N.C. N.C N.C. N.C NO 2 NC 2 4 DIP/SO 5 N.C. 4 DIP/SO 5 N.C. 3 4 SOT SOT23-5 PUT LOW HIGH OFF ON SWITCH STATE ON OFF MARKG FORMATION (SOTs ONLY) LOT SPECIFIC CODE XX XX AC = AD = N.C. = NOT TERNALLY CONNECTED Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at , or visit Maxim s website at

2 ABSOLUTE MAXIMUM RATGS (Voltages Referenced to ) V, +3V Voltage into Any Terminal (Note ) V to ( + 0.3V) or ±0mA (whichever occurs first) Continuous Current into Any Terminal...±0mA Peak Current, NO_ or _ (pulsed at ms,0% duty cycle)...±20ma Continuous Power Dissipation (T A = +70 C) 8-Pin Plastic DIP (derate 9.09mW/ C above +70 C)...727mW 8-Pin SO (derate 5.88mW/ C above +70 C)...47mW Note : Voltages on any signal terminal exceeding or are clamped by internal diodes. Limit forward-diode current to maximum current rating. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS ±5V Supply 5-Pin SOT23-5 (derate 7.mW/ C above +70 C)...57mW 8-Pin CERDIP (derate 8.00mW/ C above +70 C)...640mW Operating Temperature Ranges C /C...0 C to +70 C E /E C to +85 C MJA/MJA C to +25 C Storage Temperature Range C to +50 C Lead Temperature (soldering, 0sec) C ( = +4.5V to +5.5V, = -4.5V to -5.5V, H =3.5V, L =.5V, T A = T M to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER ANALOG SWITCH Analog Signal Range to NO or NC On-Resistance NO or NC Off Leakage Current (Note 3) Off Leakage Current (Note 3) On Leakage Current (Note 3) DIGITAL I/O Input Logic High V IH () -.5 V Input Logic Low V IL () V Input Current Logic High or Low SYMBOL CONDITIONS M TYP MAX (Note 2) V, V NO, V NC V R ON V _ = 3.5V, I = ma T A = +25 C T A = T M to T MAX 350 = 5.5V, = -5.5V, T A = +25 C I NO(OFF), V I _ = ±4.5V, NC(OFF) V NO or V NC = _ T A = T M C, E V to T MAX M = 5.5V, = -5.5V, T A = +25 C I (OFF) V _ = ±4.5V, V NO or V NC = +4.5V _ T A = T M C, E -0 0 to T MAX M = 5.5V, = -5.5V, T A = +25 C I (ON) V = ±4.5V, T A = T M C, E V NO or V NC = ±4.5V to T MAX M I IH, I IL =, 0V µa UNITS Ω na na na 2

3 ELECTRICAL CHARACTERISTICS ±5V Supply (continued) ( = +4.5V to +5.5V, = -4.5V to -5.5V, H = 3.5V, L =.5V, T A = T M to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) Off Isolation PARAMETER Turn-Off Time Charge Injection (Note 4) NO or NC Off Capacitance Off Capacitance On Capacitance POWER SUPPLY, Supply Current SYMBOL Q V ISO C NO(OFF) C OFF() C ON() I+, I- = 3V, R L = kω V NO or V NC = 3V, Figure = 0V or CONDITIONS SWITCH DYNAMIC CHARACTERISTICS V Turn-On Time t = 3V, R L = kω ON V NO or V NC = 3V, Figure t OFF C L = nf, V NO_ = 0V, R S = 0Ω, T A = +25 C, Figure 2 R L =, C L = 5pF, V NO = V RMS, f = 00kHz, T A = +25 C, Figure 3 f = MHz, T A = +25 C, Figure 4 f = MHz, T A = +25 C, Figure 4 f = MHz, T A = +25 C, Figure 4 M TYP MAX (Note 2) T A = +25 C T A = T M to T MAX 240 T A = +25 C T A = T M to T MAX 50 0 <-90 T A = +25 C T A = T M to T MAX UNITS ns ns pc db pf pf pf µa 3

4 ELECTRICAL CHARACTERISTICS ±3V Supply ( = +2.7V to +3.3V, = -2.7V to -3.3V, H = 2.4V, L = 0.8V, T A = T M to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER ANALOG SWITCH Analog Signal Range to NO or NC On-Resistance NO or NC Off Leakage Current (Notes 3, 4) Off Leakage Current (Notes 3, 4) On Leakage Current (Notes 3, 4) DIGITAL I/O Input Logic High H 2.4 V Input Logic Low L 0.4 V Input Current Logic High or Low POWER SUPPLY SYMBOL, Supply Current I+, I- = 0V or CONDITIONS M TYP MAX (Note 2) V, V NO, V NC 0 V R ON V _ =.5V, I = 0.mA T A = +25 C T A = T M to T MAX 500 V - I _ = ±.5V, NO(OFF), V I NO or V NC = _ T A = +25 C +.5V, T NC(OFF) A = T M C, E -0 0 = 3.3V, = -3.3V to T MAX M V T A = +25 C - _ = ±.5V, I (OFF) V NO or V NC = +.5V, _ T A = T M C, E -0 0 = 3.3V, = -3.3V to T MAX M V NO or V NC = ±.5V, T A = +25 C -2 2 I (ON) V _ = ±.5V, T A = T M C, E = 3.3V, = -3.3V to T MAX M I IH, I IL µa T A = +25 C T A = T M to T MAX UNITS Note 2: The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column. Note 4: Guaranteed, not production tested. Note 3: Leakage parameters are 00% tested at maximum rated hot operating temperature, and guaranteed by correlation at +25 C. Note 5: SOT packaged parts are 00% tested at +25 C. Limits at maximum and minimum rated temperature are guaranteed by design and correlation limits at +25 C. Ω na na na µa 4

5 Typical Operating Characteristics ( = +5V, = -5V, T A = +25 C, unless otherwise noted.) RON (Ω) ON-RESISTANCE vs. V AND TEMPERATURE T A = +25 C T A = +85 C T A = +25 C 20 T A = -55 C V (V) -0 R ON (Ω) ON-RESISTANCE vs. V = +2V = -2V = +4V = -4V = +V = -V V (V) = +5V = -5V = +3V = -3V -02 Q (pc) CHARGE JECTION vs. V = +5V = -5V V (V) -03 LEAKAGE CURRENT (na) LEAKAGE CURRENT vs. TEMPERATURE I ON I /NO/NC OFF TEMPERATURE ( C) -04 LOSS (db) FREQUENCY RESPONSE ( AND OUT) ON LOSS ON PHASE OFF ISOLATION FREQUENCY (MHz) PHASE (DEGREES) TOTAL HARMONIC DISTORTION (%) TOTAL HARMONIC DISTORTION vs. FREQUENCY 600Ω /OUT = 5V = -5V -06 LOGIC THRESHOLD (V) LOGIC THRESHOLD vs. AND ,000 00,000 FREQUENCY (Hz) , VOLTAGE (V) 5

6 Pin Description DIP/SO SOT23-5 P DIP/SO SOT23-5 NAME FUNCTION Analog Switch Common Terminal 2, 3, 5 2, 3, 5 N.C. No Connect (not internally connected) Positive (analog and digital) Supply Voltage Input Digital Control Input Negative (analog) Supply Voltage Input 8 2 NO Analog Switch Normally Open Terminal 8 2 NC Analog Switch Normally Closed Terminal Note: NO, NC, and pins are identical and interchangeable. Either may be considered as an input or output; signals pass equally well in both directions. Applications Information Power-Supply Considerations The s construction is typical of most CMOS analog switches, except they have only two supply pins: and. These voltages set the analog voltage limits of the switch. Reverse ESD-protection diodes are internally connected between and each analog signal pin and both and. If any analog signal exceeds or, one of these diodes will conduct. During normal operation, these (and other) reverse-biased ESD diodes leak, forming the only current drawn from. Additional current flows through from the logic-level translator. Virtually all the analog leakage current is provided through the ESD diodes. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either or and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the and pins constitutes the analog-signal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of either the same or opposite polarity. There is no connection between the analog signal paths and or. and also power the internal logic and logic-level translators. Since there is no ground pin, the logic input has a low-current pull-up to and the logic limit is set by an internal comparator referenced to. The logiclevel translators convert the logic levels to switched and signals, to drive the gates of the analog signals. This drive signal is the only connection between the logic supplies (and signals) and the analog supplies., NO, and NC pins have ESD-protection diodes to and. The logic is CMOS compatible when is +5V. CMOS compatibility is maintained with all values, assuming that the CMOS logic is operated from the same supply. Since the have no ground pins, the logic levels are internally referenced to. Do not connect the to +3V and connect the logic-level pins to TTL-logic-level signals. TTL levels can exceed +3V and violate the absolute maximum ratings, damaging the part and/or external circuits. High-Frequency Performance In systems, signal response is reasonably flat up to 50MHz. (see Typical Operating Characteristics). Above 20MHz the on-response has several minor peaks which are highly layout dependent. The problem is not in turning the switch on, but in turning it off. The off-state switch acts like a capacitor, and passes higher frequencies with less attenuation. At 0MHz, off isolation is about -65dB in systems, becoming worse (approximately 20dB per decade) as frequency increases. Higher circuit impedances also make off isolation worse. 6

7 Test Circuits/Timing Diagrams 50% NO V NO 0V 90% 90% 35pF k 0V t ON t OFF 50% NC V NC 0V 90% 90% k 35pF 0V t OFF t ON Figure. Switching Times NO or NC V NO or V NC = 0V 0V C L 000pF IS THE MEASURED VOLTAGE DUE TO CHARGE TRANSFER ERROR Q WHEN THE CHANNEL TURNS OFF. Q = x C L Figure 2. Charge Injection 7

8 Test Circuits/Timing Diagrams (continued) Figure 3. Off Isolation and On Loss 0nF NO or NC MEAS. NETWORK ANALYZER REF OFF ISOLATION = 20log ON LOSS = 20log MEASUREMENTS ARE STANDARDIZED AGAST SHORT AT SOCKET TERMALS. OFF ISOLATION IS MEASURED BETWEEN AND OFF TERMAL ON EACH SWITCH. ON LOSS IS MEASURED BETWEEN AND ON TERMAL ON EACH SWITCH. SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST-VALUES ARE RECORDED. Chip Topography AS REQUIRED NO or NC MHz CAPACITANCE ANALYZER 0.035" (0.889mm) Figure 4. NO, NC, and Capacitance _Ordering Information (continued) PART CPA CSA TEMP. RANGE 0 C to +70 C 0 C to +70 C P-PACKAGE 8 Plastic DIP 8 SO V NO/NC CUK 0 C to +70 C 5 SOT23-5 C/D 0 C to +70 C Dice* EPA -40 C to +85 C 8 Plastic DIP ESA -40 C to +85 C 8 SO EUK -40 C to +85 C 5 SOT23-5 MJA -55 C to +25 C 8 CERDIP** 0.030" (0.762mm) *Contact factory for dice specifications. **Contact factory for availability. TRANSISTOR COUNT: 36 SUBSTRATE IS TERNALLY CONNECTED TO 8

9 Tape-and-Reel Information F E D NOTE: DIMENSIONS ARE MM. AND FOLLOW EIA48- STANDARD. A 0 B 0 D D ±0.02 ± P 0 E F K 0 P P D P 2 A 0 ±0.02 ±0.05 ±0.02 ±0.02 W B 0 t K 0 P ±0.02 P ±0.203 P ±0.05 t ±0.27 W SOT23-5 9

10 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to SOT-23 5L.EPS 0

11 Low Voltage, Dual-Supply, SPST, Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to N TOP VIEW E H CHES MILLIMETERS DIM M MAX M MAX A A B C e BSC.27 BSC E H L VARIATIONS: DIM D D D CHES MILLIMETERS M MAX M MAX N MS AA AB AC SOICN.EPS D A C e B A FRONT VIEW L SIDE VIEW 0-8 PROPRIETARY FORMATION TITLE: PACKAGE OUTLE,.50" SOIC APPROVAL DOCUMENT CONTROL NO. REV B

12 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to PDIPN.EPS 2

13 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to CDIPS.EPS Revision History Changes made at Rev :, 4, 0,, 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 3 Maxim Integrated Products, 20 San Gabriel Drive, Sunnyvale, CA (408) Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.