Low Power, Rail-to-Rail Output, Precision JFET Amplifiers AD8641/AD8642/AD8643

Transcription

1 Data Sheet Low Power, Rail-to-Rail Output, Precision JFET Amplifiers AD864/AD8642/AD8643 FEATURES Low supply current: 25 μa max Very low input bias current: pa max Low offset voltage: 75 μv max Single-supply operation: 5 V to 26 V Dual-supply operation: ±2.5 V to ±3 V Rail-to-rail output Unity-gain stable No phase reversal SC7 package APPLICATIONS Line-/battery-powered instruments Photodiode amplifiers Precision current sensing Medical instrumentation Industrial controls Precision filters Portable audio ATE GENERAL DESCRIPTION The AD864/AD8642/AD8643 are low power, precision JFET input amplifiers featuring extremely low input bias current and rail-to-rail output. The ability to swing nearly rail-to-rail at the input and rail-to-rail at the output enables designers to buffer CMOS DACs, ASICs, and other wide output swing devices in single-supply systems. The outputs remain stable with capacitive loads of more than 5 pf. The AD864/AD8642/AD8643 are suitable for applications utilizing multichannel boards that require low power to manage heat. Other applications include photodiodes, ATE reference level drivers, battery management, and industrial controls. The AD864/AD8642/AD8643 are fully specified over the extended industrial temperature range of 4 C to +25 C. The AD864 is available in 5-lead SC7 and 8-lead SOIC lead-free packages. The AD8642 is available in 8-lead MSOP and 8-lead SOIC lead-free packages. The AD8643 is available in 4-lead SOIC and 6-lead, 3 mm 3 mm, LFCSP lead-free packages. PIN CONFIGURATIONS OUT 5 VCC VEE 2 AD864 TOP VIEW (Not to Scale) +IN 3 4 IN Figure. 5-Lead SC7 (KS-5) NC IN 2 +IN 3 VEE 4 OUT A IN A 2 +IN A 3 V 4 AD864 TOP VIEW (Not to Scale) NC 7 VCC 6 OUT 5 NC NC = NO CONNECT Figure 2. 8-Lead SOIC (R-8) OUT A IN A 2 +IN A 3 V 4 AD8642 TOP VIEW (Not to Scale) V+ 7 OUT B 6 IN B 5 +IN B Figure 3. 8-Lead SOIC (R-8) AD8642 TOP VIEW (Not to Scale) 8 V+ 7 OUT B 6 IN B 5 +IN B Figure 4. 8-Lead MSOP (RM-8) OUT A 4 OUT D IN A 2 3 IN D +IN A 3 AD IN D V+ 4 TOP VIEW V (Not to Scale) +IN B 5 +IN C IN B 6 9 IN C OUT B 7 8 OUT C Figure 5. 4-Lead SOIC (R-4) IN A +IN A 2 V+ 3 +IN B 4 NC OUT A OUT D NC PIN INDICATOR AD8643 TOP VIEW IN D +IN D V 9 +IN C IN B OUT B OUT C IN C NOTES. NC = NO CONNECT. 2. EXPOSED PAD SHOULD BE CONNECTED TO V+. Figure 6. 6-Lead LFCSP (CP-6) (Not Drawn to Scale) Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA , U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 AD864/AD8642/AD8643 TABLE OF CONTENTS Features... Applications... General Description... Pin Configurations... Revision History... 2 Specifications... 3 Electrical Characteristics... 3 Data Sheet Absolute Maximum Ratings...5 Thermal Resistance...5 ESD Caution...5 Typical Performance Characteristics...6 Outline Dimensions... 3 Ordering Guide... 5 REVISION HISTORY 9/ Rev. D to Rev. E Changes to Thermal Resistance Section / Rev. C to Rev. D Changes to Figure 6... / Rev. B to Rev. C Changes to Figure 6... Added Thermal Resistance Section and Table Updated Outline Dimensions... 3 Changes to Ordering Guide /5 Rev. A to Rev. B Added AD Universal Added 4-Lead SOIC...Universal Added 6-Lead LFCSP...Universal Updated Outline Dimensions... 3 Changes to Ordering Guide /5 Rev. to Rev. A Added AD Universal Changes to General Description... Added Figure 3 and Figure 4... Changes to Specifications...3 Changes to Absolute Maximum Ratings...5 Changes to Figure Changes to Figure Changes to Figure Updated Outline Dimensions... 3 Changes to Ordering Guide... 4 /4 Initial Version: Revision Rev. E Page 2 of 6

3 Data Sheet AD864/AD8642/AD8643 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VS = 5. V, VCM = 2.5 V, TA = 25 C, unless otherwise noted. Table. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS 5 75 μv AD8643 LFCSP only mv 4 C < TA < +85 C.5 mv +85 C < TA < +25 C, VCM =.5 V.6 mv Input Bias Current IB.25 pa 4 C < TA < +25 C 8 pa Input Offset Current IOS.5 pa 4 C < TA < +25 C 6 pa Input Voltage Range 3 V Common-Mode Rejection Ratio CMRR VCM = V to 2.5 V db Large Signal Voltage Gain AVO RL = kω, VO =.5 to 4.5 V 8 4 V/mV Offset Voltage Drift VOS/ T 4 C < TA < +25 C 2.5 μv/ C OUTPUT CHARACTERISTICS Output Voltage High VOH 4.95 V IL = ma, 4 C to +25 C 4.94 V Output Voltage Low VOL.5 V IL = ma, 4 C to +25 C..5 V Output Current IOUT ±6 ma POWER SUPPLY Power Supply Rejection Ratio PSRR VS = 5 V to 26 V 9 7 db Supply Current/Amplifier ISY μa 4 C < TA < +25 C 27 μa DYNAMIC PERFORMANCE Slew Rate SR 2 V/μs Gain Bandwidth Product GBP AD864, AD MHz AD MHz Phase Margin Øm 5 Degrees NOISE PERFORMANCE Voltage Noise en p-p f =. Hz to Hz 4. μv p-p Voltage Noise Density en f = khz 28.5 nv/ Hz Current Noise Density in f = khz.5 fa/ Hz Rev. E Page 3 of 6

4 AD864/AD8642/AD8643 Data Sheet VS= ±3 V, VCM = V, TA =25 C, unless otherwise noted. Table 2. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS 7 75 μv AD8643 LFCSP only mv 4 < TA < +25 C.5 mv Input Bias Current IB.25 pa 4 C < TA < +25 C 26 pa Input Offset Current IOS.5 pa 4 C < TA < +25 C 65 pa Input Voltage Range 3 + V Common-Mode Rejection Ratio CMRR VCM = 3 V to + V 9 7 db Large Signal Voltage Gain AVO RL = kω, VO = V to + V V/mV Offset Voltage Drift VOS/ T 4 C < TA < +25 C 2.5 μv/ C OUTPUT CHARACTERISTICS Output Voltage High VOH V IL = ma, 4 C to +25 C V Output Voltage Low VOL 2.95 V IL = ma, 4 C to +25 C 2.94 V Output Current IOUT ±2 ma POWER SUPPLY Power Supply Rejection Ratio PSRR VS = ±2.5 V to ±3 V 9 7 db Supply Current/Amplifier ISY 2 29 μa 4 C < TA < +25 C 33 μa DYNAMIC PERFORMANCE Slew Rate SR 3 V/μs Gain Bandwidth Product GBP 3.5 MHz Phase Margin Øm 6 Degrees NOISE PERFORMANCE Voltage Noise en p-p f =. Hz to Hz 4.2 μv p-p Voltage Noise Density en f = khz 27.5 nv/ Hz Current Noise Density in f = khz.5 fa/ Hz Rev. E Page 4 of 6

5 Data Sheet ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings apply at 25 C, unless otherwise noted. Table 3. Parameter Rating Supply Voltage 27.3 V Input Voltage VS to VS+ Differential Input Voltage ±Supply Voltage Output Short-Circuit Duration Indefinite Storage Temperature Range KS-5, R-8, RM-8, R-4, CP-6 Packages 65 C to +5 C Operating Temperature Range 4 C to +25 C Junction Temperature Range KS-5, R-8, RM-8, R-4, CP-6 Packages 65 C to +5 C Lead Temperature (Soldering, 6 sec) 3 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. AD864/AD8642/AD8643 THERMAL RESISTANCE θja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. This was measured using a standard 4-layer board. For the LFCSP package, solder the exposed pad to a copper plane, which should be connected to V+. Table 4. Package Type θja θjc Unit 5-Lead SC7 (KS) C/W 8-Lead SOIC (R) 2 43 C/W 8-Lead MSOP (RM) C/W 4-Lead SOIC (R) 36 C/W 6-Lead LFCSP (CP) 8 6 C/W ESD CAUTION Rev. E Page 5 of 6

6 AD864/AD8642/AD8643 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS V SY = 5V V CM =.5V FREQUENCY NUMBER OF AMPLIFIERS V OS (mv) T C V OS (μv/ C) Figure 7. Input Offset Voltage Figure. Offset Voltage Drift NUMBER OF AMPLIFIERS INPUT BIAS (pa) T A = 25 C OFFSET VOLTAGE (μv/ C) V CM (V) Figure 8. Offset Voltage Drift Figure. Input Bias Current vs. VCM V SY = ±2.5V.4.3 T A = 25 C FREQUENCY INPUT BIAS (pa) V OS (mv) V CM (V) Figure 9. Input Offset Voltage Figure 2. Input Bias Current vs. VCM Rev. E Page 6 of 6

7 Data Sheet AD864/AD8642/AD V SY = 5V INPUT BIAS CURRENT (pa) V OS (μv) TEMPERATURE ( C) V CM (V) 572- Figure 3. Input Bias Current vs. Temperature Figure 6. Input Offset Voltage vs. VCM..8.6 V SY = +5V OR ±5V M INPUT BIAS (pa) OPEN-LOOP GAIN (V/V) M k V SY = ±2.5V V CM (V) k. LOAD RESISTANCE (kω) Figure 4. Input Bias Current vs. VCM Figure 7. Open-Loop Gain vs. Load Resistance 9 A 8 B 7 6 C D V OS (μv) V CM (V) 572- A VO (V/mV) E A., V O = ±V, R L = kω B., V O = ±V, R L = 2kΩ C. V SY = +5V, V O = +.5V/+4.5V, R L = kω D. V SY = +5V, V O = +.5V/+4.5V, R L = 2kΩ E. V SY = +5V, V O = +.5V/+4.5V, R L = 6Ω TEMPERATURE ( C) Figure 5. Input Offset Voltage vs. VCM Figure 8. Open-Loop Gain vs. Temperature Rev. E Page 7 of 6

8 AD864/AD8642/AD8643 Data Sheet OFFSET VOLTAGE (μv) kω kω kω OUTPUT VOLTAGE (V) Figure 9. Input Error Voltage vs. Output Voltage for Resistive Loads SATURATION VOLTAGE (mv) V SY V OH V SY V OL... LOAD CURRENT (ma) Figure 22. Output Saturation Voltage vs. Load Current V SY = ±5V POS RAIL V SY =5V V SY V OH INPUT VOLTAGE (μv) R L = kω 5 R L = 2kΩ R L = kω R L = kω R L = kω R L = kω R L = kω 3 NEG RAIL R L = 2kΩ OUTPUT VOLTAGE FROM SUPPLY RAIL (mv) SATURATION VOLTAGE (mv) V OL... LOAD CURRENT (ma) Figure 2. Input Error Voltage vs. Output Voltage Within 3 mv of Supply Rails Figure 23. Output Saturation Voltage vs. Load Current R L = 2kΩ C L = 4pF I SY (μa) C +25 C 2 55 C V SY (V) GAIN (db) GAIN 3 35 k k M M PHASE PHASE (Degrees) Figure 2. Quiescent Current vs. Supply Voltage at Different Temperatures Figure 24. Open-Loop Gain and Phase Margin vs. Frequency Rev. E Page 8 of 6

9 Data Sheet AD864/AD8642/AD V SY = 5V R L = 2kΩ C L = 4pF GAIN (db) GAIN PHASE PHASE (Degrees) CMRR (db) k k M M k k k M M Figure 25. Open-Loop Gain and Phase Margin vs. Frequency Figure 28. CMRR vs. Frequency R L = 2kΩ C L = 4pF 4 2 V SY =5V GAIN (db) G = + G = + CMRR (db) G = k k k M M k k k M M Figure 26. Closed-Loop Gain vs. Frequency Figure 29. CMRR vs. Frequency V SY = 5V R L = 2kΩ C L = 4pF 4 2 +PSRR GAIN (db) G = + G = + PSRR (db) PSRR G = k k k M M k k k M M Figure 27. Closed-Loop Gain vs. Frequency Figure 3. PSRR vs. Frequency Rev. E Page 9 of 6

10 AD864/AD8642/AD8643 Data Sheet 4 2 V SY =5V..8 T 8 +PSRR.6.4 V IN PSRR (db) PSRR INPUT BIAS (pa) V OUT 4 6 k k k M M CH 4.V 3 CH2 2.V M4μs 2 A 3CH 4.V5 T.s V CM (V) Figure 3. PSRR vs. Frequency Figure 34. No Phase Reversal G = + 5 V S = ±3V GAIN = +5 TS + (%) Z OUT (Ω) G = + G = + OUTPUT SWING (V) 5 5 TS + (.%) TS (.%). TS (%). k k k M M M SETTLING TIME (μs) Figure 32. Output Impedance vs. Frequency Figure 35. Output Swing and Error vs. Settling Time V SY =5V G = V S = ±3V R L = kω V IN = mv p-p A V = + Z OUT (Ω) G = + G = + OVERSHOOT (%) OS OS+.. k k k M M M CAPACITANCE (pf) Figure 33. Output Impedance vs. Frequency Figure 36. Small Signal Overshoot vs. Load Capacitance Rev. E Page of 6

11 Data Sheet AD864/AD8642/AD8643 OVERSHOOT (%) V S = ±2.5V R L = kω V IN = mv p-p A V = + OS OS+ VOLTAGE NOISE DENSITY (nv/ Hz) k CAPACITANCE (pf) Figure 37. Small Signal Overshoot vs. Load Capacitance k k Figure 4. Voltage Noise Density INPUT BIAS (pa) V S = ±3V G = +M CH p-p = 4.26V VOLTAGE NOISE DENSITY (nv/ Hz) k V SY = 5V.8. 5 CH 4.V 3 2 M.s 2 A CH V5 V CM (V) k k Figure 38.. Hz to Hz Noise Figure 4. Voltage Noise Density..8.6 V S = ±2.5V G = +M CH p-p = 4.6V.4. LOAD = kω GAIN = + 8V p-p INPUT INPUT BIAS (pa) THD + NOISE (%).. 4V p-p INPUT 2V p-p INPUT V p-p INPUT CH 4.V 3 2 M.s 2 A CH V5 V CM (V) k k 2k Figure 39.. Hz to Hz Noise Figure 42. Total Harmonic Distortion + Noise vs. Frequency Rev. E Page of 6

12 AD864/AD8642/AD8643 Data Sheet (db) V IN + 2kΩ 2kΩ V IN = 4.5V p-p V IN = 9V p-p 2kΩ 6 2 k k k Figure 43. Channel Separation + 2kΩ V IN = 8V p-p Rev. E Page 2 of 6

13 Data Sheet AD864/AD8642/AD8643 OUTLINE DIMENSIONS BSC MAX COPLANARITY..3.5 SEATING PLANE.22.8 COMPLIANT TO JEDEC STANDARDS MO-23-AA Figure Lead Thin Shrink Small Outline Transistor Package [SC7] (KS-5) Dimensions shown in millimeters A 5. (.968) 4.8 (.89) 4. (.574) 3.8 (.497) (.244) 5.8 (.2284).25 (.98). (.4) COPLANARITY. SEATING PLANE.27 (.5) BSC.75 (.688).35 (.532).5 (.2).3 (.22) 8.25 (.98).7 (.67).5 (.96).25 (.99).27 (.5).4 (.57) 45 COMPLIANT TO JEDEC STANDARDS MS-2-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure Lead Standard Small Outline Package [SOIC_N] (R-8) Dimensions shown in millimeters and (inches) 247-A Rev. E Page 3 of 6

14 AD864/AD8642/AD8643 Data Sheet PIN IDENTIFIER.65 BSC COPLANARITY MAX 6 5 MAX.23.9 COMPLIANT TO JEDEC STANDARDS MO-87-AA Figure Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters b 8.75 (.3445) 8.55 (.3366) 4. (.575) 3.8 (.496) (.244) 5.8 (.2283).25 (.98). (.39) COPLANARITY..27 (.5) BSC.5 (.2).3 (.22).75 (.689).35 (.53) SEATING PLANE 8.25 (.98).7 (.67).5 (.97).25 (.98).27 (.5).4 (.57) 45 COMPLIANT TO JEDEC STANDARDS MS-2-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure Lead Standard Small Outline Package [SOIC_N] (R-4) Dimensions shown in millimeters and (inches) 666-A PIN INDICATOR 3. BSC SQ TOP VIEW 2.75 BSC SQ.45.6 MAX BOTTOM VIEW 3 2 EXPOSED PAD PIN INDICATOR *.65.5 SQ SEATING PLANE 2 MAX.8 MAX.65 TYP MAX.2 NOM.2 REF.5 BSC.5 REF 4 5 *COMPLIANT TO JEDEC STANDARDS MO-22-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Figure Lead Lead Frame Chip Scale Package [LFCSP_VQ] 3 mm 3 mm Body, Very Thin Quad (CP-6-3) Dimensions shown in millimeters A Rev. E Page 4 of 6

15 Data Sheet AD864/AD8642/AD8643 ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AD864AKSZ-R2 4 C to +25 C 5-Lead SC7 KS-5 A7 AD864AKSZ-REEL7 4 C to +25 C 5-Lead SC7 KS-5 A7 AD864AKSZ-REEL 4 C to +25 C 5-Lead SC7 KS-5 A7 AD864ARZ 4 C to +25 C 8-lead SOIC_N R-8 AD864ARZ-REEL7 4 C to +25 C 8-lead SOIC_N R-8 AD864ARZ-REEL 4 C to +25 C 8-lead SOIC_N R-8 AD8642ARMZ 4 C to +25 C 8-lead MSOP RM-8 AA AD8642ARMZ-REEL 4 C to +25 C 8-lead MSOP RM-8 AA AD8642ARZ 4 C to +25 C 8-lead SOIC_N R-8 AD8642ARZ-REEL7 4 C to +25 C 8-lead SOIC_N R-8 AD8642ARZ-REEL 4 C to +25 C 8-lead SOIC_N R-8 AD8643ARZ 4 C to +25 C 4-lead SOIC_N R-4 AD8643ARZ-REEL7 4 C to +25 C 4-lead SOIC_N R-4 AD8643ARZ-REEL 4 C to +25 C 4-lead SOIC_N R-4 AD8643ACPZ-R2 4 C to +25 C 6-Lead LFCSP_VQ CP-6-3 AUA AD8643ACPZ-REEL7 4 C to +25 C 6-Lead LFCSP_VQ CP-6-3 AUA AD8643ACPZ-REEL 4 C to +25 C 6-Lead LFCSP_VQ CP-6-3 AUA Z = RoHS Compliant Part. Rev. E Page 5 of 6

16 AD864/AD8642/AD8643 Data Sheet NOTES 24 2 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D572--9/(E) Rev. E Page 6 of 6