High Voltage Latch-Up Proof, 4-/8-Channel Multiplexers ADG5408/ADG5409

Transcription

1 ata Sheet FEATURES Latch-up proof 8 kv human body model (HBM) ES rating Low on resistance (3.5 Ω) ±9 V to ±22 V dual-supply operation 9 V to 4 V single-supply operation 48 V supply maximum ratings Fully specified at ±5 V, ±2 V, +2 V, and +36 V VSS to V analog signal range APPLICATIONS Relay replacement Automatic test equipment ata acquisition Instrumentation Avionics Audio and video switching Communication systems GENERAL ESCRIPTION The AG548/AG549 are monolithic CMOS analog multiplexers comprising eight single channels and four differential channels, respectively. The AG548 switches one of eight inputs to a common output, as determined by the 3-bit binary address lines, A, A, and A2. The AG549 switches one of four differential inputs to a common differential output, as determined by the 2-bit binary address lines, A and A. An EN input on both devices enables or disables the device. When EN is disabled, all channels switch off. The on-resistance profile is very flat over the full analog input range, which ensures good linearity and low distortion when switching audio signals. High switching speed also makes the parts suitable for video signal switching. Each switch conducts equally well in both directions when on, and each switch has an input signal range that extends to the power supplies. In the off condition, signal levels up to the supplies are blocked. High Voltage Latch-Up Proof, 4-/8-Channel Multiplexers AG548/AG549 S S8 FUNCTIONAL BLOCK IAGRAMS AG548 -OF-8 ECOER A A A2 EN SA S4A SB S4B Figure. AG549 -OF-4 ECOER A A EN The AG548/AG549 do not have VL pins; rather, the logic power supply is generated internally by an on-chip voltage generator. PROUCT HIGHLIGHTS. Trench isolation guards against latch-up. A dielectric trench separates the P and N channel transistors thereby preventing latch-up even under severe overvoltage conditions. 2. Low RON. 3. ual-supply operation. For applications where the analog signal is bipolar, the AG548/AG549 can be operated from dual supplies up to ±22 V. 4. Single-supply operation. For applications where the analog signal is unipolar, the AG548/AG549 can be operated from a single rail power supply up to 4 V V logic compatible digital inputs: VINH = 2. V, VINL =.8 V. 6. No VL logic power supply required. A B 926- Rev. C ocument Feedback Information furnished by Analog evices is believed to be accurate and reliable. However, no responsibility is assumed by Analog evices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog evices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA , U.S.A. Tel: Analog evices, Inc. All rights reserved. Technical Support

2 AG548/AG549 TABLE OF CONTENTS Features... Applications... Functional Block iagrams... General escription... Product Highlights... Revision History... 2 Specifications... 3 ±5 V ual Supply... 3 ±2 V ual Supply V Single Supply V Single Supply... 6 Continuous Current per Channel, Sx or... 8 ata Sheet Absolute Maximum Ratings...9 ES Caution...9 Pin Configurations and Function escriptions... Typical Performance Characteristics... 2 Test Circuits... 6 Terminology... 8 Trench Isolation... 9 Applications Information... 2 Outline imensions... 2 Ordering Guide REVISION HISTORY 3/3 Rev. B to Rev. C Changes to Table 5 and Table Changed AG548 Peak Current from 37 ma to 435 ma; Changed AG549 Peak Current from 275 ma to 3 ma; Changed Reflow Soldering Peak Temperature, Pb Free from 26(+/ 5) C to As per JEEC J-ST-2; Table Changes to Figure 25, Figure 26, and Figure /2 Rev. A to Rev. B Removed Automotive Information (Throughout)... Changes to Ordering Guide eleted Automotive Products Section / Rev. to Rev. A Change to Features Section... Change to ISS Parameter, Table Changes to Figure 3... Changes to Figure 5... Updated Outline imensions... 2 Changes to Ordering Guide... 2 Added Automotive Products Section / Revision : Initial Version Rev. C Page 2 of 24

3 ata Sheet AG548/AG549 SPECIFICATIONS ±5 V UAL SUPPLY V = +5 V ± %, VSS = 5 V ± %, GN = V, unless otherwise noted. Table. Parameter 25 C 4 C to +85 C 4 C to +25 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V to VSS V On Resistance, RON 3.5 Ω typ VS = ± V, IS = ma; see Figure Ω max V = +3.5 V, VSS = 3.5 V On-Resistance Match Between.3 Ω typ VS = ± V, IS = ma Channels, RON Ω max On-Resistance Flatness, RFLAT (ON).8 Ω typ VS = ± V, IS = ma Ω max LEAKAGE CURRENTS V = +6.5 V, VSS = 6.5 V Source Off Leakage, IS (Off ) ±.5 na typ VS = ± V, V = V; see Figure 29 ±.25 ± ±7 na max rain Off Leakage, I (Off ) ±. na typ VS = ± V, V = V; see Figure 29 ±.4 ±4 ±3 na max Channel On Leakage, I (On), IS (On) ±. na typ VS = V = ± V; see Figure 25 ±.4 ±4 ±3 na max IGITAL INPUTS Input High Voltage, VINH 2. V min Input Low Voltage, VINL.8 V max Input Current, IINL or IINH.2 µa typ VIN = VGN or V ±. µa max igital Input Capacitance, CIN 3 pf typ YNAMIC CHARACTERISTICS Transition Time, ttransition 7 ns typ RL = 3 Ω, CL = 35 pf ns max VS = V; see Figure 32 ton (EN) 4 ns typ RL = 3 Ω, CL = 35 pf ns max VS = V; see Figure 34 toff (EN) 3 ns typ RL = 3 Ω, CL = 35 pf ns max VS = V; see Figure 34 Break-Before-Make Time elay, t 5 ns typ RL = 3 Ω, CL = 35 pf 6 ns min VS = VS2 = V; see Figure 33 Charge Injection, QINJ 5 pc typ VS = V, RS = Ω, CL = nf; see Figure 35 Off Isolation 6 db typ RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 28 Channel-to-Channel Crosstalk 6 db typ RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 27 Total Harmonic istortion + Noise. % typ RL = kω, 5 V p-p, f = 2 Hz to 2 khz; see Figure 3 3 db Bandwidth RL = 5 Ω, CL = 5 pf; see Figure 3 AG548 5 MHz typ AG MHz typ Insertion Loss.9 db typ RL = 5 Ω, CL = 5 pf, f = MHz; Figure 3 CS (Off ) 5 pf typ VS = V, f = MHz C (Off ) AG548 2 pf typ VS = V, f = MHz AG549 5 pf typ VS = V, f = MHz Rev. C Page 3 of 24

4 AG548/AG549 ata Sheet Parameter 25 C 4 C to +85 C 4 C to +25 C Unit Test Conditions/Comments C (On), CS (On) AG pf typ VS = V, f = MHz AG549 8 pf typ VS = V, f = MHz POWER REQUIREMENTS V = +6.5 V, VSS = 6.5 V I 45 µa typ igital inputs = V or V 55 7 µa max ISS. µa typ igital inputs = V or V µa max V/VSS ±9/±22 V min/v max GN = V Guaranteed by design; not subject to production test. ±2 V UAL SUPPLY V = +2 V ± %, VSS = 2 V ± %, GN = V, unless otherwise noted. Table 2. Parameter 25 C 4 C to +85 C 4 C to +25 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V to VSS V On Resistance, RON 2.5 Ω typ VS = ±5 V, IS = ma; see Figure Ω max V = +8 V, VSS = 8 V On-Resistance Match Between.3 Ω typ VS = ±5 V, IS = ma Channels, RON Ω max On-Resistance Flatness, RFLAT (ON) 2.3 Ω typ VS = ±5 V, IS = ma Ω max LEAKAGE CURRENTS V = +22 V, VSS = 22 V Source Off Leakage, IS (Off ) ±. na typ VS = ±5 V, V = 5 V; see Figure 29 ±.25 ± ±7 na max rain Off Leakage, I (Off ) ±.5 na typ VS = ±5 V, V = 5 V; see Figure 29 ±.4 ±4 ±3 na max Channel On Leakage, I (On), IS (On) ±.5 na typ VS = V = ±5 V; see Figure 25 ±.4 ±4 ±3 na max IGITAL INPUTS Input High Voltage, VINH 2. V min Input Low Voltage, VINL.8 V max Input Current, IINL or IINH.2 µa typ VIN = VGN or V ±. µa max igital Input Capacitance, CIN 3 pf typ YNAMIC CHARACTERISTICS Transition Time, ttransition 6 ns typ RL = 3 Ω, CL = 35 pf ns max VS = V; see Figure 32 ton (EN) 4 ns typ RL = 3 Ω, CL = 35 pf ns max VS = V; see Figure 34 toff (EN) 33 ns typ RL = 3 Ω, CL = 35 pf ns max VS = V; see Figure 34 Break-Before-Make Time elay, t 38 ns typ RL = 3 Ω, CL = 35 pf ns min VS = VS2 = V; see Figure 33 Charge Injection, QINJ 55 pc typ VS = V, RS = Ω, CL = nf; see Figure 35 Off Isolation 6 db typ RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 28 Channel-to-Channel Crosstalk 6 db typ RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 27 Rev. C Page 4 of 24

5 ata Sheet AG548/AG549 Parameter 25 C 4 C to +85 C 4 C to +25 C Unit Test Conditions/Comments Total Harmonic istortion + Noise.2 % typ RL = kω, 2 V p-p, f = 2 Hz to 2 khz; see Figure 3 3 db Bandwidth RL = 5 Ω, CL = 5 pf; see Figure 3 AG548 5 MHz typ AG MHz typ Insertion Loss.8 db typ RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 3 CS (Off ) 7 pf typ VS = V, f = MHz C (Off ) AG pf typ VS = V, f = MHz AG pf typ VS = V, f = MHz C (On), CS (On) AG pf typ VS = V, f = MHz AG549 8 pf typ VS = V, f = MHz POWER REQUIREMENTS V = +22 V, VSS = 22 V I 5 µa typ igital inputs = V or V 7 µa max ISS. µa typ igital inputs = V or V µa max V/VSS ±9/±22 V min/v max GN = V Guaranteed by design; not subject to production test. 2 V SINGLE SUPPLY V = 2 V ± %, VSS = V, GN = V, unless otherwise noted. Table 3. Parameter 25 C 4 C to +85 C 4 C to +25 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V to V V On Resistance, RON 26 Ω typ VS = V to V, IS = ma; see Figure Ω max V =.8 V, VSS = V On-Resistance Match Between.3 Ω typ VS = V to V, IS = ma Channels, RON.5.6 Ω max On-Resistance Flatness, RFLAT (ON) 5.5 Ω typ VS = V to V, IS = ma Ω max LEAKAGE CURRENTS V = 3.2 V, VSS = V Source Off Leakage, IS (Off ) ±.2 na typ VS = V/ V, V = V/ V; see Figure 29 ±.25 ± ±7 na max rain Off Leakage, I (Off ) ±.5 na typ VS = V/ V, V = V/ V; see Figure 29 ±.4 ±4 ±3 na max Channel On Leakage, I (On), IS (On) ±.5 na typ VS = V = V/ V; see Figure 25 ±.4 ±4 ±3 na max IGITAL INPUTS Input High Voltage, VINH 2. V min Input Low Voltage, VINL.8 V max Input Current, IINL or IINH.2 µa typ VIN = VGN or V ±. µa max igital Input Capacitance, CIN 3 pf typ Rev. C Page 5 of 24

6 AG548/AG549 ata Sheet Parameter 25 C 4 C to +85 C 4 C to +25 C Unit Test Conditions/Comments YNAMIC CHARACTERISTICS Transition Time, ttransition 23 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 8 V; see Figure 32 ton (EN) 25 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 8 V; see Figure 34 toff (EN) 34 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 8 V; see Figure 34 Break-Before-Make Time elay, t 8 ns typ RL = 3 Ω, CL = 35 pf 55 ns min VS = VS2 = 8 V; see Figure 33 Charge Injection, QINJ 45 pc typ VS = 6 V, RS = Ω, CL = nf; see Figure 35 Off Isolation 6 db typ RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 28 Channel-to-Channel Crosstalk 6 db typ RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 27 Total Harmonic istortion + Noise. % typ RL = kω, 6 V p-p, f = 2 Hz to 2 khz; see Figure 3 3 db Bandwidth RL = 5 Ω, CL = 5 pf; see Figure 3 AG MHz typ AG MHz typ Insertion Loss.8 db typ RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 3 CS (Off ) 22 pf typ VS = 6 V, f = MHz C (Off ) AG548 9 pf typ VS = 6 V, f = MHz AG pf typ VS = 6 V, f = MHz C (On), CS (On) AG pf typ VS = 6 V, f = MHz AG pf typ VS = 6 V, f = MHz POWER REQUIREMENTS V = 3.2 V I 4 µa typ igital inputs = V or V 5 65 µa max V 9/4 V min/v max GN = V, VSS = V Guaranteed by design; not subject to production test. 36 V SINGLE SUPPLY V = 36 V ± %, VSS = V, GN = V, unless otherwise noted. Table 4. Parameter 25 C 4 C to +85 C 4 C to +25 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V to V V On Resistance, RON 4.5 Ω typ VS = V to 3 V, IS = ma; see Figure Ω max V = 32.4 V, VSS = V On-Resistance Match Between.3 Ω typ VS = V to 3 V, IS = ma Channels, RON Ω max On-Resistance Flatness, RFLAT (ON) 3.5 Ω typ VS = V to 3 V, IS = ma Ω max LEAKAGE CURRENTS V =39.6 V, VSS = V Source Off Leakage, IS (Off ) ±. na typ VS = V/3 V, V = 3 V/ V; see Figure 29 ±.25 ± ±7 na max Rev. C Page 6 of 24

7 ata Sheet AG548/AG549 Parameter 25 C 4 C to +85 C 4 C to +25 C Unit Test Conditions/Comments rain Off Leakage, I (Off ) ±.5 na typ VS = V/3 V, V = 3 V/ V; see Figure 29 ±.4 ±4 ±3 na max Channel On Leakage, I (On), IS (On) ±.5 na typ VS = V = V/3 V; see Figure 25 ±.4 ±4 ±3 na max IGITAL INPUTS Input High Voltage, VINH 2. V min Input Low Voltage, VINL.8 V max Input Current, IINL or IINH.2 µa typ VIN = VGN or V ±. µa max igital Input Capacitance, CIN 3 pf typ YNAMIC CHARACTERISTICS Transition Time, ttransition 87 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 8 V; see Figure 32 ton (EN) 6 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 8 V; see Figure 34 toff (EN) 47 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 8 V; see Figure 34 Break-Before-Make Time elay, t 53 ns typ RL = 3 Ω, CL = 35 pf 7 ns min VS = VS2 = 8 V; see Figure 33 Charge Injection, QINJ 5 pc typ VS = 8 V, RS = Ω, CL = nf; see Figure 35 Off Isolation 6 db typ RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 28 Channel-to-Channel Crosstalk 6 db typ RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 27 Total Harmonic istortion + Noise.4 % typ RL = kω, 8 V p-p, f = 2 Hz to 2 khz; see Figure 3 3 db Bandwidth RL = 5 Ω, CL = 5 pf; see Figure 3 AG MHz typ AG MHz typ Insertion Loss db typ RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 3 CS (Off ) 8 pf typ VS = 8 V, f = MHz C (Off ) AG548 2 pf typ VS = 8 V, f = MHz AG549 6 pf typ VS = 8 V, f = MHz C (On), CS (On) AG pf typ VS = 8 V, f = MHz AG549 8 pf typ VS = 8 V, f = MHz POWER REQUIREMENTS V = 39.6 V I 8 µa typ igital inputs = V or V 3 µa max V 9/4 V min/v max GN = V, VSS = V Guaranteed by design; not subject to production test. Rev. C Page 7 of 24

8 AG548/AG549 ata Sheet CONTINUOUS CURRENT PER CHANNEL, Sx OR Table 5. AG548 Parameter 25 C 85 C 25 C Unit CONTINUOUS CURRENT, Sx OR V = +5 V, VSS = 5 V TSSOP (θja = 2.6 C/W) ma maximum LFCSP (θja = 3.4 C/W) ma maximum V = +2 V, VSS = 2 V TSSOP (θja = 2.6 C/W) ma maximum LFCSP (θja = 3.4 C/W) ma maximum V = 2 V, VSS = V TSSOP (θja = 2.6 C/W) ma maximum LFCSP (θja = 3.4 C/W) ma maximum V = 36 V, VSS = V TSSOP (θja = 2.6 C/W) ma maximum LFCSP (θja = 3.4 C/W) ma maximum Table 6. AG549 Parameter 25 C 85 C 25 C Unit CONTINUOUS CURRENT, Sx OR V = +5 V, VSS = 5 V TSSOP (θja = 2.6 C/W) ma maximum LFCSP (θja = 3.4 C/W) ma maximum V = +2 V, VSS = 2 V TSSOP (θja = 2.6 C/W) ma maximum LFCSP (θja = 3.4 C/W) ma maximum V = 2 V, VSS = V TSSOP (θja = 2.6 C/W) ma maximum LFCSP (θja = 3.4 C/W) ma maximum V = 36 V, VSS = V TSSOP (θja = 2.6 C/W) ma maximum LFCSP (θja = 3.4 C/W) ma maximum Rev. C Page 8 of 24

9 ata Sheet ABSOLUTE MAXIMUM RATINGS TA = 25 C, unless otherwise noted. Table 7. Parameter V to VSS V to GN VSS to GN Analog Inputs Rating 48 V.3 V to +48 V +.3 V to 48 V VSS.3 V to V +.3 V or 3 ma, whichever occurs first igital Inputs VSS.3 V to V +.3 V or 3 ma, whichever occurs first Peak Current, Sx or Pins AG ma (pulsed at ms, % duty cycle maximum) AG549 3 ma (pulsed at ms, % duty cycle maximum) Continuous Current, Sx or 2 ata + 5% Temperature Range Operating 4 C to +25 C Storage 65 C to +5 C Junction Temperature 5 C Thermal Impedance, θja 6-Lead TSSOP (4-Layer 2.6 C/W Board) 6-Lead LFCSP (4-Layer 3.4 C/W Board) Reflow Soldering Peak As per JEEC J-ST-2 Temperature, Pb Free Overvoltages at the Ax, EN, Sx, and pins are clamped by internal diodes. Limit current to the maximum ratings given. 2 See Table 5. AG548/AG549 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time. ES CAUTION Rev. C Page 9 of 24

10 S4 S8 S EN 5 A 4 A 3 A2 AG548/AG549 ata Sheet PIN CONFIGURATIONS AN FUNCTION ESCRIPTIONS A 6 A EN 2 5 A2 S S2 S AG548 TOP VIEW (Not to Scale) GN V S5 S6 S S2 S AG548 TOP VIEW (Not to Scale) 2 GN V S5 9 S6 S4 7 S7 8 9 S Figure 2. AG548 Pin Configuration (TSSOP) NOTES. THE EXPOSE PA IS CONNECTE INTERNALLY. FOR INCREASE RELIABILITY OF THE SOLER JOINTS AN MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENE THAT THE PA BE SOLERE TO THE SUBSTRATE,. Figure 3. AG548 Pin Configuration (LFCSP) Table 8. AG548 Pin Function escriptions Pin No. TSSOP LFCSP Mnemonic escription 5 A Logic Control Input. 2 6 EN Active High igital Input. When low, the device is disabled and all switches are off. When high, Ax logic inputs determine on switches. 3 VSS Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. 4 2 S Source Terminal. This pin can be an input or an output. 5 3 S2 Source Terminal 2. This pin can be an input or an output. 6 4 S3 Source Terminal 3. This pin can be an input or an output. 7 5 S4 Source Terminal 4. This pin can be an input or an output. 8 6 rain Terminal. This pin can be an input or an output. 9 7 S8 Source Terminal 8. This pin can be an input or an output. 8 S7 Source Terminal 7. This pin can be an input or an output. 9 S6 Source Terminal 6. This pin can be an input or an output. 2 S5 Source Terminal 5. This pin can be an input or an output. 3 V Most Positive Power Supply Potential. 4 2 GN Ground ( V) Reference. 5 3 A2 Logic Control Input. 6 4 A Logic Control Input. EP Exposed Pad The exposed pad is connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS. Table 9. AG548 Truth Table A2 A A EN On Switch X X X None Rev. C Page of 24

11 S4A A B S4B EN 5 A 4 A 3 GN ata Sheet AG548/AG549 A 6 A EN 2 5 GN SA S2A S3A S4A AG549 TOP VIEW (Not to Scale) V SB S2B S3B S4B SA 2 S2A 3 S3A 4 AG549 TOP VIEW (Not to Scale) 2 V SB S2B 9 S3B A 8 9 B Figure 4. AG549 Pin Configuration (TSSOP) NOTES. THE EXPOSE PA IS CONNECTE INTERNALLY. FOR INCREASE RELIABILITY OF THE SOLER JOINTS AN MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENE THAT THE PA BE SOLERE TO THE SUBSTRATE,. Figure 5. AG549 Pin Configuration (LFCSP) Table. AG549 Pin Function escriptions Pin No. TSSOP LFCSP Mnemonic escription 5 A Logic Control Input. 2 6 EN Active High igital Input. When low, the device is disabled and all switches are off. When high, Ax logic inputs determine on switches. 3 VSS Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. 4 2 SA Source Terminal A. This pin can be an input or an output. 5 3 S2A Source Terminal 2A. This pin can be an input or an output. 6 4 S3A Source Terminal 3A. This pin can be an input or an output. 7 5 S4A Source Terminal 4A. This pin can be an input or an output. 8 6 A rain Terminal A. This pin can be an input or an output. 9 7 B rain Terminal B. This pin can be an input or an output. 8 S4B Source Terminal 4B. This pin can be an input or an output. 9 S3B Source Terminal 3B. This pin can be an input or an output. 2 S2B Source Terminal 2B. This pin can be an input or an output. 3 SB Source Terminal B. This pin can be an input or an output. 4 2 V Most Positive Power Supply Potential. 5 3 GN Ground ( V) Reference. 6 4 A Logic Control Input. EP Exposed Pad The exposed pad is connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS. Table. AG549 Truth Table A A EN On Switch Pair X X None Rev. C Page of 24

12 AG548/AG549 ata Sheet TYPICAL PERFORMANCE CHARACTERISTICS ON RESISTANCE (Ω) T A = 25 C V = +V = V V = +9V = 9V V = +3.5V = 3.5V V = +5V V = +6.5V = 5V = 6.5V V = +V = V ON RESISTANCE (Ω) T A = 25 C V = 32.4V = V V = 36V = V V = 39.6V = V V S, V (V) V S, V (V) Figure 6. RON as a Function of VS, V (ual Supply) Figure 9. RON as a Function of VS, V (Single Supply) 6 T A = 25 C 25 4 ON RESISTANCE (Ω) V = +8V = 8V V = +2V = 2V V = +22V = 22V ON RESISTANCE (Ω) 2 5 T A = +25 C T A = +85 C T A = +25 C T A = 4 C V S, V (V) V = +5V = 5V V S, V (V) Figure 7. RON as a Function of VS, V (ual Supply) Figure. RON as a Function of VS (V) for ifferent Temperatures, ±5 V ual Supply ON RESISTANCE (Ω) T A = 25 C V = 9V = V V = V = V V = 3.2V = V V =.8V = V V = 2V = V V = V = V ON RESISTANCE (Ω) V = +2V = 2V T A = +25 C T A = +85 C T A = +25 C T A = 4 C V S, V (V) Figure 8. RON as a Function of VS, V (Single Supply) V S, V (V) Figure. RON as a Function of VS (V) for ifferent Temperatures, ±2 V ual Supply Rev. C Page 2 of 24

13 ata Sheet AG548/AG V = +2V = 2V V BIAS = +5V/ 5V I, I S (ON) + + I S (OFF) + ON RESISTANCE (Ω) T A = +25 C T A = +85 C T A = +25 C T A = 4 C LEAKAGE CURRENT (na) 2 I (OFF) + I S (OFF) + I, I S (ON) I (OFF) + 5 V = 2V = V V S, V (V) Figure 2. RON as a Function of VS (V) for ifferent Temperatures, 2 V Single Supply TEMPERATURE ( C) Figure 5. Leakage Currents vs. Temperature, ±2 V ual Supply V = 36V = V.5 V = 2V = V V BIAS = V/V I S (OFF) + I, I S (ON) ON RESISTANCE (Ω) 5 T A = +25 C T A = +85 C T A = +25 C T A = 4 C LEAKAGE CURRENT (na).5. I (OFF) + I S (OFF) + I, I S (ON) I (OFF) V S, V (V) TEMPERATURE ( C) Figure 3. RON as a Function of V (VS) for ifferent Temperatures, 36 V Single Supply Figure 6. Leakage Currents vs. Temperature, 2 V Single Supply.5 V = +5V = 5V V BIAS = +V/ V I S (OFF) + I, I S (ON) + + V = +36V = V V BIAS = V/3V I, I S (ON) + + I S (OFF) + LEAKAGE CURRENT (na).5..5 I S (OFF) + I (OFF) + I, I S (ON) I (OFF) + LEAKAGE CURRENT (na) 2 I (OFF) + I S (OFF) + I, I S (ON) I (OFF) TEMPERATURE ( C) Figure 4. Leakage Currents vs. Temperature, ±5 V ual Supply TEMPERATURE ( C) Figure 7. Leakage Currents vs. Temperature, 36 V Single Supply Rev. C Page 3 of 24

14 AG548/AG549 ata Sheet 2 T A = 25 C V = +5V = 5V 2 T A = 25 C V = +5V = 5V OFF ISOLATION (db) ACPSRR (db) NO ECOUPLING CAPACITORS ECOUPLING CAPACITORS k k k M M M G FREQUENCY (Hz) Figure 8. Off Isolation vs. Frequency, ±5 V ual Supply k k k M M FREQUENCY (Hz) Figure 2. ACPSRR vs. Frequency, ±5 V ual Supply CROSSTALK (db) T A = 25 C V = +5V = 5V TH + N (%) LOA = kω T A = 25 C V = 2V, = V, V S = 6V p-p V = 36V, = V, V S = 8V p-p 8 9 k k M M M G FREQUENCY (Hz) Figure 9. Crosstalk vs. Frequency, ±5 V ual Supply V = 5V, = 5V, V S = 5V p-p V = 2V, = 2V, V S = 2V p-p FREQUENCY (khz) Figure 22. TH + N vs. Frequency CHARGE INJECTION (pc) T A = 25 C V = +5V = 5V V = +2V = 2V V = +2V = V V = +36V = V V S (V) INSERTION LOSS (db) k T A = 25 C V = +5V = 5V AG548 k k M M M FREQUENCY (Hz) AG549 G Figure 2. Charge Injection vs. Source Voltage Figure 23. Bandwidth Rev. C Page 4 of 24

15 ata Sheet AG548/AG TIME (ns) V = +2V, = V V = +36V, = V V = +5V, = 5V V = +2V, = 2V TEMPERATURE ( C) Figure 24. ttransition Times vs. Temperature Rev. C Page 5 of 24

16 AG548/AG549 ata Sheet TEST CIRCUITS NC S S2 I (ON) A I S (OFF) A S I (OFF) A S8 A S8 V NC = NO CONNECT V V S V Figure 25. On Leakage Figure 29. Off Leakage.µFV.µF V AUIO PRECISION R S V S V S R ON = V/I S Figure 26. On Resistance I S V IN IN Sx GN R L kω Figure 3. TH + Noise Figure V OUT V S V p-p µFV.µF.µFV.µF NETWORK ANALYZER V OUT R L 5Ω V S S2 R L 5Ω V Sx NETWORK ANALYZER 5Ω V S V S GN GN V OUT R L 5Ω CHANNEL-TO-CHANNEL CROSSTALK = 2 log V OUT V S V OUT WITH SWITCH INSERTION LOSS = 2 log V OUT WITHOUT SWITCH Figure 27. Channel-to-Channel Crosstalk Figure 3. Bandwidth V.µF.µF V NETWORK ANALYZER 5Ω Sx GN 5Ω R L 5Ω V S V OUT OFF ISOLATION = 2 log V OUT V S Figure 28. Off Isolation Rev. C Page 6 of 24

17 ata Sheet AG548/AG549 V 3V ARESS RIVE (V IN ) V 5% 5% t r < 2ns t f < 2ns V IN 5Ω V A A A2 S S2 TO S7 V S t TRANSITION OUTPUT t TRANSITION 9% S8 AG548* 2.4V EN V S8 OUTPUT 9% GN 3Ω 35pF *SIMILAR CONNECTION FOR AG Figure 32. Address to Output Switching Times, ttransition V 3V ARESS RIVE (V IN ) V V IN 5Ω V A A A2 S S2 TO S7 V S OUTPUT 8% 8% S8 AG548* 2.4V EN OUTPUT GN 3Ω 35pF t *SIMILAR CONNECTION FOR AG Figure 33. Break-Before-Make elay, t V 3V V ENABLE RIVE (V IN ) V 5% 5% A A A2 S S2 TO S8 V S OUTPUT t ON (EN).9V O.9V O t OFF (EN) V IN 5Ω EN AG548* GN OUTPUT 3Ω 35pF *SIMILAR CONNECTION FOR AG549. Figure 34. Enable elay, ton (EN), toff (EN) 926- V 3V V A V IN A A2 AG548* V OUT Q INJ = C L V OUT V OUT V S R S V IN Sx EN GN C L nf V OUT Figure 35. Charge Injection Rev. C Page 7 of 24 *SIMILAR CONNECTION FOR AG

18 AG548/AG549 TERMINOLOGY I I represents the positive supply current. ISS ISS represents the negative supply current. V, VS V and VS represent the analog voltage on Terminal and Terminal S, respectively. RON RON is the ohmic resistance between Terminal and Terminal S. RON RON represents the difference between the RON of any two channels. RFLAT (ON) The difference between the maximum and minimum value of on resistance as measured over the specified analog signal range is represented by RFLAT (ON). IS (Off) IS (Off) is the source leakage current with the switch off. I (Off) I (Off) is the drain leakage current with the switch off. I (On), IS (On) I (On) and IS (On) represent the channel leakage currents with the switch on. VINL VINL is the maximum input voltage for Logic. VINH VINH is the minimum input voltage for Logic. IINL, IINH IINL and IINH represent the low and high input currents of the digital inputs. C (Off) C (Off) represents the off switch drain capacitance, which is measured with reference to ground. CS (Off) CS (Off) represents the off switch source capacitance, which is measured with reference to ground. C (On), CS (On) C (On) and CS (On) represent on switch capacitances, which are measured with reference to ground. CIN CIN represents digital input capacitance. ata Sheet ton (EN) ton (EN) represents the delay time between the 5% and 9% points of the digital input and switch on condition. toff (EN) toff (EN) represents the delay time between the 5% and 9% points of the digital input and switch off condition. ttransition elay time between the 5% and 9% points of the digital inputs and the switch on condition when switching from one address state to another. t t represents the off time measured between the 8% point of both switches when switching from one address state to another. Off Isolation Off isolation is a measure of unwanted signal coupling through an off channel. Charge Injection Charge injection is a measure of the glitch impulse transferred from the digital input to the analog output during switching. Crosstalk Crosstalk is a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Bandwidth Bandwidth is the frequency at which the output is attenuated by 3 db. On Response On response is the frequency response of the on switch. Total Harmonic istortion + Noise (TH + N) The ratio of the harmonic amplitude plus noise of the signal to the fundamental is represented by TH + N. AC Power Supply Rejection Ratio (ACPSRR) ACPSRR is a measure of the ability of a part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of.62 V p-p. The ratio of the amplitude of signal on the output to the amplitude of the modulation is the ACPSRR. Rev. C Page 8 of 24

19 ata Sheet AG548/AG549 TRENCH ISOLATION In the AG548/AG549, an insulating oxide layer (trench) is placed between the NMOS and the PMOS transistors of each CMOS switch. Parasitic junctions, which occur between the transistors in junction isolated switches, are eliminated, and the result is a completely latch-up proof switch. In junction isolation, the N and P wells of the PMOS and NMOS transistors form a diode that is reverse-biased under normal operation. However, during overvoltage conditions, this diode can become forward-biased. A silicon controlled rectifier (SCR) type circuit is formed by the two transistors causing a significant amplification of the current that, in turn, leads to latch-up. With trench isolation, this diode is removed, and the result is a latch-up proof switch. TRENCH NMOS PMOS P-WELL N-WELL BURIE OXIE LAYER HANLE WAFER Figure 36. Trench Isolation Rev. C Page 9 of 24

20 AG548/AG549 APPLICATIONS INFORMATION The AG54xx family switches and multiplexers provide a robust solution for instrumentation, industrial, aerospace, and other harsh environments that are prone to latch-up, which is an undesirable high current state that can lead to device failure and persist until the power supply is turned off. The AG548/ AG549 high voltage switches allow single-supply operation ata Sheet from 9 V to 4 V and dual-supply operation from ±9 V to ±22 V. The AG548/AG549 (as well as select devices within the same family) achieve an 8 kv human body model ES rating that provides a robust solution eliminating the need for separate protect circuitry designs in some applications. Rev. C Page 2 of 24

21 ata Sheet AG548/AG549 OUTLINE IMENSIONS BSC PIN.65 BSC.3.9 COPLANARITY..2 MAX SEATING PLANE COMPLIANT TO JEEC STANARS MO-53-AB Figure Lead Thin Shrink Small Outline Package [TSSOP] (RU-6) imensions shown in millimeters PIN INICATOR SEATING PLANE SQ 3.9 TOP VIEW.65 BSC MAX.2 NOM COPLANARITY.8.2 REF EXPOSE PA COMPLIANT TO JEEC STANARS MO-22-WGGC. Figure Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm 4 mm Body, Very Very Thin Quad (CP-6-7) imensions shown in millimeters BOTTOM VIEW PIN INICATOR SQ MIN FOR PROPER CONNECTION OF THE EXPOSE PA, REFER TO THE PIN CONFIGURATION AN FUNCTION ESCRIPTIONS SECTION OF THIS ATA SHEET C Rev. C Page 2 of 24

22 AG548/AG549 ata Sheet ORERING GUIE Model Temperature Range Package escription Package Option AG548BRUZ 4 C to +25 C 6-Lead Thin Shrink Small Outline Package [TSSOP] RU-6 AG548BRUZ-REEL7 4 C to +25 C 6-Lead Thin Shrink Small Outline Package [TSSOP] RU-6 AG548BCPZ-REEL7 4 C to +25 C 6-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-6-7 AG549BRUZ 4 C to +25 C 6-Lead Thin Shrink Small Outline Package [TSSOP] RU-6 AG549BRUZ-REEL7 4 C to +25 C 6-Lead Thin Shrink Small Outline Package [TSSOP] RU-6 AG549BCPZ-REEL7 4 C to +25 C 6-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-6-7 Z = RoHS Compliant Part. Rev. C Page 22 of 24

23 ata Sheet AG548/AG549 NOTES Rev. C Page 23 of 24

24 AG548/AG549 ata Sheet NOTES 2 23 Analog evices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners /3(C) Rev. C Page 24 of 24