0.4 Ω CMOS, Dual DPDT Switch in WLCSP/LFCSP/TSSOP ADG888

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1 FEATURES.8 V to 5.5 V operation Ultralow on resistance.4 Ω typical.6 Ω maximum at 5 V supply Excellent audio performance, ultralow distortion.7 Ω typical.4 Ω maximum RON flatness High current carrying capability 4 ma continuous 6 ma peak current at 5 V Automotive temperature range: 4 C to +25 C Rail-to-rail switching operation Typical power consumption (<. µw) APPLICATIONS Cellular phones PDAs MP3 players Power routing Battery-powered systems PCMCIA cards Modems Audio and video signal routing Communication systems Data switching GENERAL DESCRIPTION The is a low voltage, dual DPDT (double-pole, double-throw) CMOS device optimized for high performance audio switching. With its low power and small physical size, it is ideal for portable devices. This device offers ultralow on resistance of less than.8 Ω over the full temperature range, making it an ideal solution for applications requiring minimal distortion through the switch. The also has the capability of carrying large amounts of current, typically 4 ma at 5 V operation. When on, each switch conducts equally well in both directions and has an input signal range that extends to the supplies. The exhibits break-before-make switching action..4 Ω CMOS, Dual DPDT Switch in WLCSP/LFCSP/TSSOP FUNCTIONAL BLOCK DIAGRAM S2A S2B IN S3A S3B S4A S4B IN2 SWITCHES SHOWN FOR A LOGIC INPUT Figure. The is available in a 6-ball WLCSP, 6-lead LFCSP, and a 6-lead TSSOP. These packages make the the ideal solution for space-constrained applications. PRODUCT HIGHLIGHTS. <.6 Ω over full temperature range of 4 C to +25 C. 2. High current handling capability (4 ma continuous current at 5 V). 3. Low THD + N (.8% typical). 4. Tiny 6-ball WLCSP, 6-lead LFCSP, and 6-lead TSSOP. D D2 D3 D Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA , U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support

2 TABLE OF CONTENTS Features... Applications... Functional Block Diagram... General Description... Product Highlights... Revision History... 2 Specifications... 3 Absolute Maximum Ratings... 5 Data Sheet ESD Caution...5 Pin Configurations and Function Descriptions...6 Typical Performance Characteristics...8 Test Circuits... Terminology... 2 Outline Dimensions... 3 Ordering Guide... 4 REVISION HISTORY 3/27 Rev. B to Rev. C Changes to Figure Changes to Figure 9... Changes to Ordering Guide /26 Rev. A to Rev. B Changed CB-6 to CB-6- and CP-6-4 to CP Throughout Changes to Figure 2 and Table Moved Figure Added Table 5; Renumbered Sequentially... 8 Updated Outline Dimensions... 3 Changes to Ordering Guide /26 Rev. to Rev. A Updated Format... Universal Changes to Table Changes to Table Changes to Ordering Guide /25 Revision : Initial Version Rev. C Page 2 of 7

3 SPECIFICATIONS VDD = 4.2 V to 5.5 V, = V, unless otherwise noted. Table. Parameter +25 C B Version Y Version Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range to VDD V On Resistance (RON).4 Ω typ VDD = 4.2 V, VS = V to VDD, IDS = ma Ω max See Figure 6 On Resistance Match Between Channels ( RON).4 Ω typ VDD = 4.2 V, VS = 2.2 V, IDS = ma Ω max On Resistance Flatness (RFLAT (ON)).7 Ω typ VDD = 4.2 V, VS = V to VDD..3.4 Ω max IDS = ma LEAKAGE CURRENTS VDD = 5.5 V Source Off Leakage IS (Off ) ±.2 na typ VS = V/4.5 V, VD = 4.5 V/ V; see Figure 7 Channel On Leakage ID, IS (On) ±.2 na typ VS = VD = V or 4.5 V; see Figure 8 DIGITAL INPUTS Input High Voltage, VINH 2. V min Input Low Voltage, VINL.8 V max Input Current IINL or IINH.5 µa typ VIN = VINL or VINH ±. µa max CIN, Digital Input Capacitance 2 pf typ DYNAMIC CHARACTERISTICS 2 ton 22 ns typ RL = 5 Ω, CL = 35 pf ns max VS = 3 V/ V; see Figure 9 toff 3 ns typ RL = 5 Ω, CL = 35 pf ns max VS = 3 V/ V; see Figure 9 Break-Before-Make Time Delay (tbbm) 9 ns typ RL = 5 Ω, CL = 35 pf 5 ns min VS = VS2 = 3 V; see Figure 2 Charge Injection 7 pc typ VS = V, RS = Ω, CL = nf; see Figure 2 Off Isolation 67 db typ RL = 5 Ω, CL = 5 pf, f = khz; see Figure 22 Channel-to-Channel Crosstalk 99 db typ Adjacent channel; RL = 5 Ω, CL = 5 pf, f = khz; see Figure db typ Adjacent switch; RL = 5 Ω, CL = 5 pf, f = khz; see Figure 23 Total Harmonic Distortion (THD + N).8 % RL = 32 Ω, f = 2 Hz to 2 khz, VS = 3 V p-p Insertion Loss.3 db typ RL = 5 Ω, CL = 5 pf; see Figure 24 3 db Bandwidth 29 MHz typ RL = 5 Ω, CL = 5 pf; see Figure 24 CS (Off ) 58 pf typ CD, CS (On) pf typ POWER REQUIREMENTS VDD = 5.5 V IDD.3 µa typ Digital inputs = V or 5.5 V 4 µa max Temperature range for the Y version is 4 C to +25 C for the TSSOP and LFCSP; temperature range for the B version is 4 C to +85 C for the WLCSP. 2 Guaranteed by design, not production tested. Rev. C Page 3 of 7

4 Data Sheet VDD = 2.7 V to 3.6 V, = V, unless otherwise noted. Table 2. Parameter +25 C B Version Y Version Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range to VDD V On Resistance (RON).5 Ω typ VDD = 2.7 V, VS = V to VDD Ω max IS = ma; see Figure 6 On Resistance Match Between Channels ( RON).45 Ω typ VDD = 2.7 V, VS = V Ω max IS = ma On Resistance Flatness (RFLAT (ON)).6 Ω typ VDD = 2.7 V, VS = V to VDD.262 Ω max IS = ma LEAKAGE CURRENTS VDD = 3.6 V Source Off Leakage IS (Off ) ±.2 na typ VS = V/2.6 V, VD = 2.6 V/ V; see Figure 7 Channel On Leakage ID, IS (On) ±.2 na typ VS = VD = V or 2.6 V; see Figure 8 DIGITAL INPUTS Input High Voltage, VINH.3 V min Input Low Voltage, VINL.8 V max Input Current IINL or IINH.5 µa typ VIN = VINL or VINH ±. µa max CIN, Digital Input Capacitance 2 pf typ DYNAMIC CHARACTERISTICS 2 ton 28 ns typ RL = 5 Ω, CL = 35 pf; see Figure ns max VS =.5 V/ V toff 3 ns typ RL = 5 Ω, CL = 35 pf; see Figure ns max VS =.5 V/ V Break-Before-Make Time Delay (tbbm) 4 ns typ RL = 5 Ω, CL = 35 pf 5 ns min VS = VS2 =.5 V; see Figure 2 Charge Injection 5 pc typ VS = V, RS = Ω, CL = nf; see Figure 2 Off Isolation 67 db typ RL = 5 Ω, CL = 5 pf, f = khz; see Figure 22 Channel-to-Channel Crosstalk 99 db typ Adjacent channel; RL = 5 V, CL = 5 pf, f = khz; see Figure db typ Adjacent switch; RL = 5 Ω, CL = 5 pf, f = khz; see Figure 23 Total Harmonic Distortion (THD + N). % RL = 32 Ω, f = 2 Hz to 2 khz, VS = V p-p Insertion Loss.4 db typ RL = 5 Ω, CL = 5 pf; see Figure 24 3 db Bandwidth 29 MHz typ RL = 5 Ω, CL = 5 pf; see Figure 24 CS (Off ) 6 pf typ CD, CS (On) 5 pf typ POWER REQUIREMENTS VDD = 3.6 V IDD.3 µa typ Digital inputs = V or 3.6 V 2 µa max Temperature range for the Y version is 4 C to +25 C for the TSSOP and LFCSP; temperature range for the B version is 4 C to +85 C for the WLCSP. 2 Guaranteed by design, not production tested. Rev. C Page 4 of 7

5 ABSOLUTE MAXIMUM RATINGS TA = 25 C, unless otherwise noted. Table 3. Parameter Rating VDD to.3 V to +6 V Analog Inputs, Digital Inputs.3 V to VDD +.3 V or 3 ma, whichever occurs first Peak Current, S or D 5 V operation 6 ma (pulsed at ms, % duty cycle max) Continuous Current, S or D 5 V operation 4 ma Operating Temperature Range Automotive (Y Version) TSSOP and LFCSP 4 C to +25 C Industrial (B version) WLCSP 4 C to +85 C Storage Temperature Range 65 C to +5 C Junction Temperature 5 C Thermal Impedance 6-Lead TSSOP θja (4-Layer Board) 2 C/W θjc 27.6 C/W 6-Lead WLCSP θja (4-Layer Board) 3 C/W 6-Lead LFCSP θja (4-Layer Board) 3.4 C/W Reflow Soldering (RoHS Compliant) Peak Temperature 26(+/ 5) C Time at Peak Temperature sec to 4 sec Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Only one absolute maximum rating can be applied at any one time. ESD CAUTION Overvoltages at IN, S, or D are clamped by internal diodes. Limit current to the maximum ratings given. Rev. C Page 5 of 7

6 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS S4A D 2 S2B 3 TOP VIEW (Not to Scale) 2 D4 S4B S3B D2 4 9 D3 D S2B TOP VIEW (Not to Scale) S4A D4 S4B S3B S2A IN IN2 S3A NOTES. THE EXPOSED PAD MUST BE CONNECTED TO GROUND. Figure 2. 6-Lead LFCSP Pin Configuration D2 S2A IN D3 S3A 9 IN2 Figure 3. 6-Lead TSSOP Pin Configuration Table 4. LFCSP and TSSOP Pin Function Descriptions Pin No. LFCSP TSSOP Mnemonic Description 3 D Drain Terminal. Can be an input or output. 2 4 Source Terminal B. Can be an input or output. 3 5 S2B Source Terminal 2B. Can be an input or output. 4 6 D2 Drain Terminal 2. Can be an input or output. 5 7 S2A Source Terminal 2A. Can be an input or output. 6 8 IN Logic Control Input. 7 9 IN2 Logic Control Input. 8 S3A Source Terminal 3A. Can be an input or output. 9 D3 Drain Terminal 3. Can be an input or output. 2 S3B Source Terminal 3B. Can be an input or output. 3 S4B Source Terminal 4B. Can be an input or output. 2 4 D4 Drain Terminal 4. Can be an input or output. 3 5 S4A Source Terminal 4A. Can be an input or output. 4 6 Ground ( V) Reference. 5 VDD Most Positive Power Supply Potential. 6 2 Source Terminal A. Can be an input or output. Not applicable EP Exposed Pad. The exposed pad must be connected to ground. Rev. C Page 6 of 7

7 A BALL A INDICATOR D S4A D B S4B S3B IN2 IN S2B C D3 S3A S2A D2 D TOP VIEW (BALL SIDE DOWN) Not to Scale (SOLDER BALLS ON OPPOSITE SIDE) Figure 4. 6-Ball WLCSP Pin Configuration Table 5. WLCSP Pin Function Descriptions WLCSP Pin No. Mnemonic Description A D4 Drain Terminal 4. Can be an input or output. B S4A Source Terminal 4A. Can be an input or output. C Source Terminal A. Can be an input or output. D D Drain Terminal. Can be an input or output. 2A S4B Source Terminal 4B. Can be an input or output. 2B Ground ( V) Reference. 2C VDD Most Positive Power Supply Potential. 2D Source Terminal B. Can be an input or output. 3A S3B Source Terminal 3B. Can be an input or output. 3B IN2 Logic Control Input. 3C IN Logic Control Input. 3D S2B Source Terminal 2B. Can be an input or output. 4A D3 Drain Terminal 3. Can be an input or output. 4B S3A Source Terminal 3A. Can be an input or output. 4C S2A Source Terminal 2A. Can be an input or output. 4D D2 Drain Terminal 2. Can be an input or output. Table 6. Truth Table Logic (IN/IN2) Switch A/2A/3A/4A Switch B/2B/3B/4B Off On On Off Rev. C Page 7 of 7

8 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS.4.35 = 4.2V = 4.5V T A = 25 C I DS = ma.7.6 T A = +25 C T A = +85 C = 3V I DS = ma.3.5 R ON ( = 5.5V = 5V R ON ( ).4.3 T A = +25 C T A = 4 C , V D (V) Figure 5. On Resistance vs. VD (VS), VDD = 4.2 V to 5.5 V , V D (V) Figure 8. On Resistance vs. VD (VS) for Different Temperatures, VDD = 3 V = 2.7V = 3V T A = 25 C I DS = ma 4 35 T A = 25 C = 5V R ON (.3.2 = 3.3V = 3.6V Q INJ (pc) ,V D (V) = 3V V D (V) Figure 6. On Resistance vs. VD (VS), VDD = 2.7 V to 3.6 V Figure 9. Charge Injection vs. Source Voltage T A = +25 C = 5V I DS = ma = 3V; SxA CHANNELS = 3V; SxB CHANNELS = 5V; SxA CHANNELS = 5V; SxB CHANNELS.3 T A = +85 C 3 R ON ( ).25.2 T A = +25 C T A = 4 C TIME (ns) 25 2 t ON , V D (V) Figure 7. On Resistance vs. VD (VS) for Different Temperatures, VDD = 5 V t OFF = 3V, 5V; SxB CHANNELS = 3V, 5V; SxA CHANNELS TEMPERATURE ( C) Figure. ton/toff Times vs. Temperature Rev. C Page 8 of 7

9 .25 = 3V, = 2V p-p T A = 25 C ON RESPONSE (db) THD + N (%) = 5V, = 4V p-p = 3V, = V p-p = 5V, = 3V p-p = 3V, =.5V p-p 9 T A = 25 C = 3V, 4.2V, 5V k k M M M FREQUENCY (Hz) Figure. Bandwidth = 5V, = V p-p 2k 4k 6k 8k k 2k 4k 6k 8k 2k FREQUENCY (Hz) Figure 4. Total Harmonic Distortion + Noise (THD + N) T A = 25 C = 3V, 4.2V, 5V 2 T A = 25 C = 3V, 4.2V, 5V NO DECOUPLING ON SUPPLIES ATTENUATION (db) ATTENUATION (db) k k k M M M FREQUENCY (Hz) Figure 2. Off Isolation vs. Frequency k k k M M M FREQUENCY (Hz) Figure 5. AC PSRR ATTENUATION (db) T A = 25 C = 3V, 4.2V, 5V ADJACENT CHANNELS (-S2A) ADJACENT SWITCHES (-) 2 -S4A 4 k k k M M M FREQUENCY (Hz) Figure 3. Crosstalk vs. Frequency Rev. C Page 9 of 7

10 Data Sheet TEST CIRCUITS I DS V S D R ON = V/I DS NC S D I D (ON) A V D Figure 6. On Resistance Figure 8. On Leakage I S (OFF) A S D I D (OFF) A V D Figure 7. Off Leakage.µF D V IN 5% 5% IN R L 5Ω C L 35pF 9% 9% t ON t OFF Figure 9. Switching Times, ton, toff.µf D V IN V 8% 5% 5% 8% IN R L 5Ω C L 35pF t BBM t BBM Figure 2. Break-Before-Make Time Delay, tbbm SW ON SW OFF D NC V IN IN nf Q INJ = CL Figure 2. Charge Injection Rev. C Page of 7

11 . F. F NETWORK ANALYZER NETWORK ANALYZER NC D R L D R L OFF ISOLATION = 2 log VS Figure 22. Off Isolation WITH SWITCH INSERTION LOSS = 2 log WITHOUT SWITCH Figure 24. Bandwidth. F R L 5 5 D R L 5 NETWORK ANALYZER 5 5 NC NC S2A S2B D2 D NC 5 CHANNEL-TO-CHANNEL CROSSTALK = 2 log VS Figure 23. Channel-to-Channel Crosstalk ( to ) CHANNEL-TO-CHANNEL CROSSTALK = 2 log VS Figure 25. Channel-to-Channel Crosstalk ( to S2A) Rev. C Page of 7

12 TERMINOLOGY IDD Positive supply current. VD (VS) Analog voltage on Terminal D and Terminal S. RON Ohmic resistance between Terminal D and Terminal S. RFLAT (ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured. RON On resistance match between any two channels. IS (OFF) Source leakage current with the switch off. ID, IS (ON) Channel leakage current with the switch on. VINL Maximum input voltage for Logic. VINH Minimum input voltage for Logic. IINL (IINH) Input current of the digital input. CS (OFF) Off switch source capacitance. Measured with reference to ground. CD, CS (ON) On switch capacitance. Measured with reference to ground. CIN Digital input capacitance. Data Sheet toff Delay time between the 5% and the 9% points of the digital input and switch off condition. tbbm On or off time measured between the 8% points of both switches when switching from one to another. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during on-off switching. Off Isolation A measure of unwanted signal coupling through an off switch. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. This is specified for two conditions: Adjacent channel, that is, to S2A, to S2B, S3A to S4A, or S3B to S4B. Adjacent switch, that is, to, S2A to S2B, S3A to S3B, or S4A to S4B. 3 db Bandwidth The frequency at which the output is attenuated by 3 db. On Response The frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. THD + N The ratio of the harmonic amplitudes plus signal noise to the fundamental. ton Delay time between the 5% and the 9% points of the digital input and switch on condition. Rev. C Page 2 of 7

13 OUTLINE DIMENSIONS SEATING PLANE BALL A IDENTIFIER SQ.94.5 BALL PITCH A B C D TOP VIEW (BALL SIDE DOWN) BOTTOM VIEW (BALL SIDE UP) B Figure Ball Wafer Level Chip Scale Package [WLCSP] (CB-6-) Dimensions shown in millimeters BSC 8 PIN INDICATOR SEATING PLANE.5.5 PIN.65 BSC.3.9 COPLANARITY..2 MAX SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-53-AB Figure Lead Thin Shrink Small Outline Package [TSSOP] (RU-6) Dimensions shown in millimeters SQ 3.9 TOP VIEW.65 BSC BOTTOM VIEW COMPLIANT TO JEDEC STANDARDS MO-22-WGGC MAX.2 NOM COPLANARITY.8.2 REF 8 EXPOSED PAD 6 Figure Lead Lead Frame Chip Scale Package [LFCSP] 4 mm 4 mm Body and.75 mm Package Height (CP-6-23) Dimensions shown in millimeters 5 4 PIN INDICATOR SQ MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 98-A Rev. C Page 3 of 7

14 Data Sheet ORDERING GUIDE Model Temperature Range Package Description Package Option Branding 2 YRUZ 4 C to +25 C 6-Lead Thin Shrink Small Outline Package [TSSOP] RU-6 YRUZ-REEL 4 C to +25 C 6-Lead Thin Shrink Small Outline Package [TSSOP] RU-6 YRUZ-REEL7 4 C to +25 C 6-Lead Thin Shrink Small Outline Package [TSSOP] RU-6 YCPZ-REEL7 4 C to +25 C 6-Lead Lead Frame Chip Scale Package [LFCSP] CP-6-23 SD BCBZ-REEL7 4 C to +85 C 6-Ball Wafer Level Chip Scale Package [WLCSP] CB-6- S2 EVAL-EBZ Evaluation Board Z = RoHS Compliant Part. 2 Branding on these packages is limited to three characters due to space constraints. Rev. C Page 4 of 7

15 NOTES Rev. C Page 5 of 7

16 Data Sheet NOTES Rev. C Page 6 of 7

0.5 Ω CMOS, 1.8 V to 5.5 V, Dual SPDT/2:1 Mux, Mini LFCSP ADG854

0.5 Ω CMOS, 1.8 V to 5.5 V, Dual SPDT/2:1 Mux, Mini LFCSP ADG854 .5 Ω CMOS, 1.8 V to 5.5 V, Dual SPDT/2:1 Mux, Mini LFCSP ADG854 FEATURES.8 Ω typical on resistance Less than 1 Ω maximum on resistance at 85 C 1.8 V to 5.5 V single supply High current carrying capability: