AD8613/AD8617/AD8619. Low Cost Micropower, Low Noise CMOS Rail-to-Rail, Input/Output Operational Amplifiers PIN CONFIGURATIONS FEATURES APPLICATIONS

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1 Low Cost Micropower, Low Noise CMOS Rail-to-Rail, Input/Output Operational Amplifiers FEATURES Offset voltage: 2.2 mv maximum Low input bias current: pa maximum Single-supply operation:.8 V to 5 V Low noise: 22 nv/ Hz Micropower: 5 μa/amplifier maximum over temperature No phase reversal Unity gain stable Qualified for automotive applications APPLICATIONS Battery-powered instrumentation Multipole filters Current shunt sense Sensors ADC predrivers DAC drivers/level shifters Low power ASIC input or output amplifiers GENERAL DESCRIPTION The are single, dual, and quad micropower, rail-to-rail input and output amplifiers that feature low supply current, as well as low input voltage and current noise. The parts are fully specified to operate from.8 V to 5 V single supply, or ±.9 V and ±2.5 V dual supply. The combination of low noise, very low input bias currents, and low power consumption make the especially useful in portable and loop-powered instrumentation. The ability to swing rail-to-rail at both the input and output enables designers to buffer CMOS ADCs, DACs, ASICs, and other wide output swing devices in low power, single-supply systems. The AD863 is available in a 5-lead SC7 package and a 5-lead TSOT-23 package. The AD867 is available in 8-lead MSOP, 8-lead SOIC, and 8-lead LFCSP packages. The AD869 is available in 4-lead TSSOP and 4-lead SOIC packages. The AD867W is qualified for automotive applications and is available in an 8-lead MSOP package and an 8-lead SOIC package. PIN CONFIGURATIONS OUT V +IN 2 3 AD863 TOP VIEW (Not to Scale) 5 4 V+ IN Figure. 5-Lead SC7 and 5-Lead TSOT-23 OUT A IN A 2 +IN A 3 V 4 AD867 TOP VIEW (Not to Scale) V OUT B IN B +IN B Figure 2. 8-Lead MSOP and 8-Lead SOIC_N OUT A IN A 2 +IN A 3 V 4 AD867 TOP VIEW (Not to Scale) 8V+ 7OUT B 6 IN B 5 +IN B NOTES. PIN 4 AND THE EXPOSED PAD MUST BE CONNECTED TO V. Figure 3. 8-Lead LFCSP_VD OUT A 4 OUT D IN A +IN A V+ +IN B IN B OUT B AD869 TOP VIEW (Not to Scale) IN D +IN D V +IN C IN C OUT C OUT A IN A 2 Figure 4. 4-Lead TSSOP 4 OUT D 3 IN D +IN A 3 AD IN D V+ 4 TOP VIEW V +IN B 5 (Not to Scale) +IN C IN B 6 9 IN C OUT B 7 8 OUT C Figure 5. 4-Lead SOIC_N Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA , U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 TABLE OF CONTENTS Features... Applications... General Description... Pin Configurations... Revision History... 2 Thermal Resistance...5 ESD Caution...5 Typical Performance Characteristics...6 Outline Dimensions... 2 Ordering Guide... 5 Specifications... 3 Absolute Maximum Ratings... 5 REVISION HISTORY 3/ Rev. D to Rev. E Changes to General Description... Changes to Ordering Guide / Rev. C to Rev. D Changes to General Description... Changes to Ordering Guide... 5 /9 Rev. B to Rev. C Added 8-Lead LFCSP Package... Universal Changes to Features Section, Figure 2 Caption, General Description Section, and Figure 3... Changed VS to VSY Throughout... 3 Changes to Input Characteristics, Input Voltage Range Parameter; Dynamic Performance, Settling Time to.% and Phase Margin Parameters; and Noise Performance, Peak-to- Peak Noise Parameter, Table... 3 Changes to Input Characteristics, Input Voltage Range Parameter; Dynamic Performance, Settling Time to.% and Phase Margin Parameters; and Noise Performance, Peak-to- Peak Noise Parameter, Table Changes to Table 3 and Table Changes to Figure 2 to Figure Changes to Figure 8 Caption... 8 Changes to Figure 3 and Figure 3... Updated Outline Dimensions... 2 Added Figure 44; Renumbered Sequentially... 4 Changes to Ordering Guide... 5 /6 Rev. A to Rev. B Added AD Universal Changes to Features... Changes to Table... 3 Changes to Table Updated Outline Dimensions... 2 Changes to Ordering Guide... 3 /5 Rev. to Rev. A Added AD Universal Change to Specifications Section... 3 Updated Outline Dimensions... 2 Changes to Ordering Guide /5 Revision : Initial Version Rev. E Page 2 of 6

3 SPECIFICATIONS Electrical characteristics at VSY = 5 V, VCM = VSY/2, TA = 25 C, unless otherwise noted. Table. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS.3 V < VCM < +5.3 V mv 4 C < TA < +25 C,.3 V < VCM < +5.2 V 2.2 mv Offset Voltage Drift VOS/ T 4 C < TA < +25 C 4.5 μv/ C AD μv/ C Input Bias Current IB.2 pa 4 C < TA < +85 C pa 4 C < TA < +25 C 78 pa Input Offset Current IOS..5 pa 4 C < TA < +85 C 5 pa 4 C < TA < +25 C 25 pa Input Voltage Range IVR 5 V Common-Mode Rejection Ratio CMRR V < VCM < 5 V 95 db 4 C < TA < +25 C 68 db Large Signal Voltage Gain AVO RL = kω,.5 V < VO < 4.5 V V/mV Input Capacitance CDIFF.9 pf CCM 2.5 pf OUTPUT CHARACTERISTICS Output Voltage High VOH IL = ma V 4 C to +25 C 4.9 V IL = ma 4.7 V 4 C to +25 C 4.5 V Output Voltage Low VOL IL = ma 2 3 mv 4 C to +25 C 5 mv IL = ma mv 4 C to +25 C 335 mv Short-Circuit Current ISC ±8 ma Closed-Loop Output Impedance ZOUT f = khz, AV = 5 Ω POWER SUPPLY Power Supply Rejection Ratio PSRR.8 V < VSY < 5 V db 4 C < TA < +25 C 64 db Supply Current/Amplifier ISY VO = VSY/2 38 μa 4 C <TA < +25 C 5 μa DYNAMIC PERFORMANCE Slew Rate SR RL = kω. V/μs Settling Time to.% ts G = ±, VIN = 2 V step, CL = 2 pf, RL = kω 23 μs Gain Bandwidth Product GBP RL = kω 4 khz RL = kω 35 khz Phase Margin ØM RL = kω, RL = kω, CL = 2 pf 7 Degrees NOISE PERFORMANCE Peak-to-Peak Noise en p-p. Hz to Hz μv Voltage Noise Density en f = khz 25 nv/ Hz f = khz 22 nv/ Hz Current Noise Density in f = khz.5 pa/ Hz Rev. E Page 3 of 6

4 Electrical characteristics at VSY =.8 V, VCM = VSY/2, TA = 25 C, unless otherwise noted. Table 2. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS.3 V < VCM < +.9 V mv.3 V < VCM < +.8 V; 4 C < TA < +25 C 2.2 mv Offset Voltage Drift VOS/ T 4 C < TA < +25 C 8.5 μv/ C AD μv/ C Input Bias Current IB.2 pa 4 C < TA < +85 C pa 4 C < TA < +25 C 78 pa Input Offset Current IOS..5 pa 4 C < TA < +85 C 5 pa 4 C < TA < +25 C 25 pa Input Voltage Range IVR.8 V Common-Mode Rejection Ratio CMRR V < VCM <.8 V db 4 C < TA < +25 C 55 db Large Signal Voltage Gain AVO RL = kω,.5 V < VO <.3 V 85 V/mV Input Capacitance CDIFF 2. pf CCM 3.8 pf OUTPUT CHARACTERISTICS Output Voltage High VOH IL = ma V 4 C to +25 C.6 V Output Voltage Low VOL IL = ma 44 6 mv 4 C to +25 C 8 mv Short-Circuit Current ISC ±7 ma Closed-Loop Output Impedance ZOUT f = khz, AV = 5 Ω POWER SUPPLY Power Supply Rejection Ratio PSRR.8 V < VS < 5 V db Supply Current/Amplifier ISY VO = VSY/2 38 μa 4 C <TA < +25 C 5 μa DYNAMIC PERFORMANCE Slew Rate SR RL = kω. V/μs Settling Time to.% ts G = ±, VIN = V step, CL = 2 pf, RL = kω 6.5 μs Gain Bandwidth Product GBP RL = kω 4 khz RL = kω 35 khz Phase Margin ØM RL = kω, RL = kω, CL = 2 pf 7 Degrees NOISE PERFORMANCE Peak-to-Peak Noise en p-p. Hz to Hz μv Voltage Noise Density en f = khz 25 nv/ Hz f = khz 22 nv/ Hz Current Noise Density in f = khz.5 pa/ Hz Rev. E Page 4 of 6

5 ABSOLUTE MAXIMUM RATINGS TA = 25 C, unless otherwise noted. Table 3. Parameter Rating Supply Voltage 6 V Input Voltage VSS.3 V to VDD +.3 V Input Current ± ma Differential Input Voltage ±6 V Output Short-Circuit Duration to GND Indefinite Storage Temperature Range 65 C to +5 C Lead Temperature (Soldering, 6 sec) 3 C Operating Temperature Range 4 C to +25 C Junction Temperature Range 65 C to +5 C THERMAL RESISTANCE θja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Characteristics Package Type θja θjc Unit 5-Lead TSOT-23 (UJ-5) 27 6 C/W 5-Lead SC7 (KS-5) C/W 8-Lead MSOP (RM-8) 2 45 C/W 8-Lead SOIC_N (R-8) C/W 8-Lead LFCSP_VD (CP-8-9) 8 2 C/W 4-Lead SOIC_N (R-4) 2 36 C/W 4-Lead TSSOP (RU-4) 8 35 C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. E Page 5 of 6

6 TYPICAL PERFORMANCE CHARACTERISTICS VSY = 5 V or ±2.5 V, unless otherwise noted. 8 6 V SY = 5.5V.5V < V CM < +5.5V 4 35 V SY = 5V AND.8V NUMBER OF AMPLIFIERS INPUT BIAS CURRENT (pa) INPUT OFFSET VOLTAGE (µv) Figure 6. Input Offset Voltage Distribution TEMPERATURE ( C) Figure 9. Input Bias Current vs. Temperature C < T A < 25 C V CM = 2.5V 5 NUMBER OF AMPLIFIERS SUPPLY CURRENT (µa) TCV OS (µv/ C) SUPPLY VOLTAGE (V) Figure 7. Input Offset Voltage Drift Distribution Figure. Supply Current vs. Supply Voltage 2 5 V SY = 5V 5 V SY = ±2.5V, ±.35V, ±.9V INPUT OFFSET VOLTAGE (µv) INPUT COMMON MODE VOLTAGE (V) Figure 8. Input Offset Voltage vs. Input Common-Mode Voltage SUPPLY CURRENT/AMPLIFIER (μa) TEMPERATURE ( C) Figure. Supply Current vs. Temperature Rev. E Page 6 of 6

7 OUTPUT VOLTAGE TO SUPPLY RAIL (mv) k. V SY = 5V T A = 25ºC SOURCE V OL V SY V OH SINK.... LOAD CURRENT (ma) Figure 2. Output Voltage to Supply Rail vs. Load Current OPEN-LOOP GAIN (db) V SY = ±2.5V AND ±.9V R L = kω C L = 2pF 2 k k k Figure 5. Open-Loop Gain and Phase vs. Frequency ΦM M PHASE (Degrees) OUTPUT VOLTAGE TO SUPPLY RAIL (mv) V SY = 5V V SY V ma V ma TEMPERATURE ( C) Figure 3. Output Voltage to Supply Rail vs. Temperature (IL = ma) CMRR (db) k k k M Figure 6. CMRR vs. Frequency V SY = 5V AND 2.7V OUTPUT VOLTAGE TO SUPPLY RAIL (mv) V SY = 5V V SY V ma V ma TEMPERATURE ( C) PSRR (db) V SY = ±2.5V AND ±.35V k k k M Figure 4. Output Voltage to Supply Rail vs. Temperature (IL = ma) Figure 7. PSRR vs. Frequency Rev. E Page 7 of 6

8 k A V = V SY = 5V A V = R L = kω C L = 2pF OUTPUT IMPEDANCE (Ω) A V = A V = VOLTAGE (V/DIV) V SY = 5V AND.8V k k k M Figure 8. Output Impedance vs. Frequency TIME (2µs/DIV) Figure 2. Large Signal Transient Response V SY = 5V SMALL SIGNAL OVERSHOOT (%) OS +OS LOAD CAPACITANCE (pf) V OUT (V) V IN (mv) 2.5 TIME (2µs/DIV) V SY = ±2.5V A V = Figure 9. Small Signal Overshoot vs. Load Capacitance Figure 22. Positive Overload Recovery VOLTAGE (5mV/DIV) V SY = 5V, 2.7V,.8V A V = R L = kω C L = 2pF V IN (mv) V OUT (V) 2.5 V SY = ±2.5V A V = TIME (4µs/DIV) TIME (2µs/DIV) Figure 2. Small Signal Transient Response Figure 23. Negative Overload Recovery Rev. E Page 8 of 6

9 V IN V SY = 5V T A = 25ºC VOLTAGE (V/DIV) V SY = ±2.5V A V = R L = kω V IN = 6V p-p V OUT TIME (2ms/DIV) INPUT VOLTAGE NOISE (nv/ Hz) /F Hz Figure 24. No Phase Reversal Figure 26. Voltage Noise Density V SY = 5V AND 2.7V 4 2 V SY = 5V VOLTAGE NOISE (µv/div) CHANNEL SEPARATION (db) TIME (s/div) Figure 25.. Hz to Hz Input Voltage Noise k k k M Figure 27. Channel Separation Rev. E Page 9 of 6

10 VSY =.8 V or ±.9 V, unless otherwise noted. NUMBER OF AMPLIFIERS 45 V SY =.8V 4 V < V CM <.8V INPUT OFFSET VOLTAGE (µv) Figure 28. Input Offset Voltage Distribution OUTPUT VOLTAGE TO SUPPLY RAIL (mv) V SY =.8V V SY V ma TEMPERATURE ( C) V ma Figure 3. Output Voltage to Supply Rail vs. Temperature (IL = ma) V SY =.8V V SY =.8V INPUT OFFSET VOLTAGE (µv) INPUT COMMON-MODE VOLTAGE (V) CMRR (db) k k k M Figure 29. Input Offset Voltage vs. Input Common-Mode Voltage Figure 32. CMRR vs. Frequency OUTPUT VOLTAGE TO SUPPLY RAIL (mv). V SY =.8V SOURCE V OL V SY V OH SINK.... LOAD CURRENT (ma) Figure 3. Output Voltage to Supply Rail vs. Load Current PSRR (db) V SY =.8V k k M Figure 33. PSRR vs. Frequency Rev. E Page of 6

11 4 V SY =.8V V SY =.8V SMALL SIGNAL OVERSHOOT (%) 3 2 OS +OS VOLTAGE (µv/div) k LOAD CAPACITANCE (pf) Figure 34. Small Signal Overshoot vs. Load Capacitance TIME (s/div) Figure 36.. Hz to Hz Input Voltage Noise V SY =.8V A V = R L = kω C L = 2pF Hz) k V SY =.8V VOLTAGE (5mV/DIV) INPUT VOLTAGE NOISE (nv/ /F Hz TIME (2µs/DIV) Figure 35. Large Signal Transient Response k k Figure 37. Voltage Noise Density Rev. E Page of 6

12 OUTLINE DIMENSIONS (.968) 4.8 (.89) (.574) 3.8 (.497) (.244) 5.8 (.2284) PIN IDENTIFIER COPLANARITY..65 BSC MAX 6 5 MAX.23.9 COMPLIANT TO JEDEC STANDARDS MO-87-AA Figure Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters B.25 (.98). (.4) COPLANARITY. SEATING PLANE.27 (.5) BSC.75 (.688).35 (.532).5 (.2).3 (.22).25 (.98).7 (.67).5 (.96).25 (.99).27 (.5).4 (.57) COMPLIANT TO JEDEC STANDARDS MS-2-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) A 8.75 (.3445) 8.55 (.3366) 4. (.575) 3.8 (.496) (.244) 5.8 (.2283).25 (.98). (.39) COPLANARITY..27 (.5) BSC.5 (.2).3 (.22).75 (.689).35 (.53) SEATING PLANE 8.25 (.98).7 (.67).5 (.97).25 (.98).27 (.5).4 (.57) 45 COMPLIANT TO JEDEC STANDARDS MS-2-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 4. 4-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-4) Dimensions shown in millimeters and (inches) 666-A Rev. E Page 2 of 6

13 BSC 7 PIN BSC COPLANARITY.9..2 MAX SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-53-AB- Figure 4. 4-Lead Thin Shrink Small Outline Package [TSSOP] (RU-4) Dimensions shown in millimeters A BSC MAX COPLANARITY..3.5 SEATING PLANE.22.8 COMPLIANT TO JEDEC STANDARDS MO-23-AA Figure Lead Thin Shrink Small Outline Transistor Package [SC7] (KS-5) Dimensions shown in millimeters A Rev. E Page 3 of 6

14 2.9 BSC BSC 2.8 BSC BSC *.9 MAX.7 MIN.9 BSC. MAX.5.3 *. MAX SEATING PLANE *COMPLIANT TO JEDEC STANDARDS MO-93-AB WITH THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS. Figure Lead Thin Small Outline Transistor Package [TSOT-23] (UJ-5) Dimensions shown in millimeters 78-A SQ MAX.6 MAX.5 BSC PIN INDICATOR SQ EXPOSED PAD TOP VIEW 2 MAX.7 MAX MAX.65 TYP.85 NOM.5 MAX. NOM SEATING PLANE REF 4 BOTTOM VIEW PIN INDICATOR FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Figure Lead Lead Frame Chip Scale Package [LFCSP_VD] 3 mm 3 mm Body, Very Thin, Dual Lead (CP-8-9) Dimensions shown in millimeters 599-A Rev. E Page 4 of 6

15 ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AD863AKSZ-R2 4 C to +25 C 5-Lead SC7 KS-5 AY AD863AKSZ-REEL 4 C to +25 C 5-Lead SC7 KS-5 AY AD863AKSZ-REEL7 4 C to +25 C 5-Lead SC7 KS-5 AY AD863AUJZ-R2 4 C to +25 C 5-Lead TSOT-23 UJ-5 AY AD863AUJZ-REEL 4 C to +25 C 5-Lead TSOT-23 UJ-5 AY AD863AUJZ-REEL7 4 C to +25 C 5-Lead TSOT-23 UJ-5 AY AD867ACPZ-R2 4 C to +25 C 8-Lead LFCSP_VD CP-8-9 AT AD867ACPZ-R7 4 C to +25 C 8-Lead LFCSP_VD CP-8-9 AT AD867ACPZ-RL 4 C to +25 C 8-Lead LFCSP_VD CP-8-9 AT AD867ARMZ 4 C to +25 C 8-Lead MSOP RM-8 AT AD867ARMZ-REEL 4 C to +25 C 8-Lead MSOP RM-8 AT AD867ARZ 4 C to +25 C 8-Lead SOIC_N R-8 AD867ARZ-REEL 4 C to +25 C 8-Lead SOIC_N R-8 AD867ARZ-REEL7 4 C to +25 C 8-Lead SOIC_N R-8 AD867WARMZ-REEL 2 4 C to +25 C 8-Lead MSOP RM-8 A23 AD867WARZ-R7 2 4 C to +25 C 8-Lead SOIC_N R-8 AD867WARZ-RL 2 4 C to +25 C 8-Lead SOIC_N R-8 AD869ARUZ 4 C to +25 C 4-Lead TSSOP RU-4 AD869ARUZ-REEL 4 C to +25 C 4-Lead TSSOP RU-4 AD869ARZ 4 C to +25 C 4-Lead SOIC_N R-4 AD869ARZ-REEL 4 C to +25 C 4-Lead SOIC_N R-4 AD869ARZ-REEL7 4 C to +25 C 4-Lead SOIC_N R-4 Z = RoHS Compliant Part. 2 Qualified for automotive applications. Rev. E Page 5 of 6

16 NOTES 25 2 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D /(E) Rev. E Page 6 of 6

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