1.5 Ω On Resistance, ±15 V/12 V/±5 V, icmos, Dual SPDT Switch ADG1436

Size: px

Start display at page:

Download "1.5 Ω On Resistance, ±15 V/12 V/±5 V, icmos, Dual SPDT Switch ADG1436"

Corey Moore
5 years ago
Views:

1 Data Sheet.5 Ω On Resistance, ±5 V/2 V/±5 V, icmos, Dual SPDT Switch ADG436 FEATURES.5 Ω on resistance.3 Ω on-resistance flatness. Ω on-resistance match between channels Continuous current per channel LFCSP package: up to 4 ma TSSOP package: up to 26 ma Fully specified at +2 V, ±5 V, and ±5 V No VL supply required 3 V logic-compatible inputs Rail-to-rail operation 6-lead TSSOP and 4 mm 4 mm, 6-lead LFCSP packages APPLICATIONS Automatic test equipment Data acquisition systems Battery-powered systems Sample-and-hold systems Audio signal routing Communication systems Relay replacement FUNCTIONAL BLOCK DIAGRAMS ADG436 SA D SB IN IN2 S2A D2 S2B SWITCHES SHOWN FOR A ONE-INPUT LOGIC. Figure. TSSOP Package ADG436 SA S2A D D2 SB S2B 687- LOGIC GENERAL DESCRIPTION The ADG436 is a monolithic CMOS device containing two independently selectable SPDT switches. An EN input on the LFCSP package enables or disable the device. When disabled, all channels are switched off. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. Both switches exhibit break-beforemake switching action for use in multiplexer applications. The ADG436 is designed on an icmos process. icmos (industrial-cmos) is a modular manufacturing process combining high voltage CMOS (complementary metal-oxide semiconductor) and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage parts has been able to achieve. Unlike analog ICs using conventional IN IN2 EN SWITCHES SHOWN FOR A ONE-INPUT LOGIC. Figure 2. LFCSP Package CMOS processes, icmos components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. The on-resistance profile is very flat over the full analog input range, ensuring excellent linearity and low distortion when switching audio signals. icmos construction ensures ultralow power dissipation, making the part ideally suited for portable and battery-powered instruments. PRODUCT HIGHLIGHTS. 2.6 Ω maximum on resistance over temperature. 2. Minimum distortion. 3. Ultralow power dissipation: <.3 μw lead TSSOP and 6-lead 4 mm 4 mm LFCSP packages Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA , U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support

2 ADG436 TABLE OF CONTENTS Features... Applications... Functional Block Diagrams... General Description... Product Highlights... Revision History... 2 Specifications V Dual Supply ingle Supply V Dual Supply... 5 Data Sheet Continuous Current per Channel...6 Absolute Maximum Ratings...7 ESD Caution...7 Pin Configurations and Function Descriptions...8 Truth Table For Switches...8 Typical Performance Characteristics...9 Terminology... 2 Test Circuits... 3 Outline Dimensions... 6 Ordering Guide... 6 REVISION HISTORY 9/26 Rev. A to Rev. B Changes to Figure Updated Outline Dimensions... 6 Changes to Ordering Guide /29 Rev. to Rev. A Change to IDD Parameter, Table... 3 Change to IDD Parameter, Table /28 Revision : Initial Version Rev. B Page 2 of 6

3 Data Sheet ADG436 SPECIFICATIONS 5 V DUAL SUPPLY VDD = 5 V ± %, VSS = 5 V ± %, = V, unless otherwise noted. Table. Parameter 25 C 4 C to +85 C 4 C to +25 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range VDD to VSS V On Resistance (RON).5 Ω typ VS = ± V, IS = ma; see Figure Ω max VDD = +3.5 V, VSS = 3.5 V On-Resistance Match. Ω typ VS = ± V, IS = ma Between Channels ( RON) Ω max On-Resistance Flatness (RFLAT(ON)).28 Ω typ VS = ± V, IS = ma Ω max LEAKAGE CURRENTS VDD = +6.5 V, VSS = 6.5 V Source Off Leakage, IS (Off) ±.4 na typ VS = ± V, VS = ± V; see Figure 24 ±.55 ±2 ±2.5 na max Drain Off Leakage, ID (Off) ±.4 na typ VS = ± V, VS = ± V; see Figure 24 ±.55 ±2 ±2.5 na max Channel On Leakage, ID, IS (On) ±. na typ VS = VD = ± V; see Figure 25 ±2 ±4 ±35 na max DIGITAL INPUTS Input High Voltage, VINH 2. V min Input Low Voltage, VINL.8 V max Input Current, IINL or IINH.5 µa typ VIN = V or VDD ±. µa max Digital Input Capacitance, CIN 3.5 pf typ DYNAMIC CHARACTERISTICS Transition Time, ttransition 25 ns typ RL = 3 Ω, CL = 35 pf ns max VS = + V; see Figure 3 ton (EN) 95 ns typ RL = 3 Ω, CL = 35 pf ns max VS = V; see Figure 3 toff (EN) 5 ns typ RL = 3 Ω, CL = 35 pf ns max VS = V; see Figure 3 Break-Before-Make Time Delay, tbbm 2 ns typ RL = 3 Ω, CL = 35 pf ns min VS = VS2 = + V; see Figure 3 Charge Injection 2 pc typ VS = V, RS = Ω, CL = nf; see Figure 33 Off Isolation 8 db typ RL = 5 Ω, CL = 5 pf, f = khz; see Figure 26 Channel-to-Channel Crosstalk 8 db typ RL = 5 Ω, CL = 5 pf, f = khz; see Figure 27 Total Harmonic Distortion + Noise. % typ RL = Ω, 5 V p-p, f = 2 Hz to 2 khz; see Figure 29 3 db Bandwidth MHz typ RL = 5 Ω, CL = 5 pf; see Figure 28 Insertion Loss.8 db typ RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 28 CS (Off) 23 pf typ f = MHz, VS = V CD (Off) 5 pf typ f = MHz, VS = V CD, CS (On) 2 pf typ f = MHz, VS = V POWER REQUIREMENTS VDD = +6.5 V, VSS = 6.5 V IDD. µa typ Digital Inputs = V or VDD µa max IDD 7 µa typ Digital Input = 5 V 285 µa max ISS. µa typ Digital Inputs = V, 5 V, or VDD. µa max VDD/VSS ±4.5/±6.5 V min/max = V Guaranteed by design, not subject to production test. Rev. B Page 3 of 6

4 ADG436 Data Sheet 2 INGLE SUPPLY VDD = 2 V ± %, VSS = V, = V, unless otherwise noted. Table 2. Parameter 25 C 4 C to +85 C 4 C to +25 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V to VDD V On Resistance (RON) 2.8 Ω typ VS = V to V, IS = ma; see Figure Ω max VDD = +.8 V, VSS = V On-Resistance Match.3 Ω typ VS = V to V, IS = ma Between Channels ( RON) Ω max On-Resistance Flatness (RFLAT(ON)).6 Ω typ VS = V to V, IS = ma..2.3 Ω max LEAKAGE CURRENTS VDD = 3.2 V, VSS = V Source Off Leakage, IS (Off) ±.4 na typ VS = V/ V, VD = V/ V; see Figure 24 ±.55 ±2 ±2.5 na max Drain Off Leakage, ID (Off) ±.4 na typ VS = V/ V, VD = V/ V; see Figure 24 ±.55 ±2 ±2.5 na max Channel On Leakage, ID, IS (On) ±. na typ VS = VD = V or V; see Figure 25 ± ±4 ±35 na max DIGITAL INPUTS Input High Voltage, VINH 2. V min Input Low Voltage, VINL.8 V max Input Current, IINL or IINH. µa typ VIN = V or VDD ±. µa max Digital Input Capacitance, CIN 3.5 pf typ DYNAMIC CHARACTERISTICS Transition Time, ttransition 2 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 8 V; see Figure 3 ton (EN) 75 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 8 V; see Figure 3 toff (EN) 5 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 8 V; see Figure 3 Break-Before-Make Time Delay, tbbm 7 ns typ RL = 3 Ω, CL = 35 pf ns min VS = VS2 = 8 V; see Figure 3 Charge Injection 3 pc typ VS = 6 V, RS = Ω, CL = nf; see Figure 33 Off Isolation 8 db typ RL = 5 Ω, CL = 5 pf, f = khz; see Figure 26; Channel-to-Channel Crosstalk 8 db typ RL = 5 Ω, CL = 5 pf, f = khz; see Figure 27 3 db Bandwidth 78 MHz typ RL = 5 Ω, CL = 5 pf; see Figure 28 Insertion Loss.3 db typ RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 28 CS (Off) 4 pf typ f = MHz, VS = 6 V CD (Off) 8 pf typ f = MHz, VS = 6 V CD, CS (On) 4 pf typ f = MHz, VS = 6 V POWER REQUIREMENTS VDD = 3.2 V IDD. µa typ Digital inputs = V or VDD. µa max IDD 7 µa typ Digital inputs = 5 V 285 µa max VDD 5/6.5 V min/max = V, VSS = V Guaranteed by design, not subject to production test. Rev. B Page 4 of 6

5 Data Sheet ADG436 5 V DUAL SUPPLY VDD = 5 V ± %, VSS = 5 V ± %, = V, unless otherwise noted. Table 3. Parameter 25 C 4 C to +85 C 4 C to +25 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range VDD to VSS V On Resistance (RON) 3.3 Ω typ VS = ±4.5 V, IS = ma; see Figure Ω max VDD = +4.5 V, VSS = 4.5 V On-Resistance Match.3 Ω typ VS = ±4.5 V, IS = ma Between Channels ( RON) Ω max On-Resistance Flatness (RFLAT(ON)).9 Ω typ VS = ±4.5 V, IS = ma Ω max LEAKAGE CURRENTS VDD = +5.5 V, VSS = 5.5 V Source Off Leakage, IS (Off) ±.3 na typ VS = ±4.5 V, VD = 4.5 V; see Figure 24 ±.2 ± ±2.5 na max Drain Off Leakage, ID (Off) ±.3 na typ VS = ±4.5 V, VD = 4.5 V; see Figure 24 ±.2 ± ±2.5 na max Channel On Leakage, ID, IS (On) ±.5 na typ VS = VD = ±4.5V; see Figure 25 ±.25 ±.5 ±35 na max DIGITAL INPUTS Input High Voltage, VINH 2. V min Input Low Voltage, VINL.8 V max Input Current, IINL or IINH. µa typ VIN = V or VDD ±. µa max Digital Input Capacitance, CIN 3.5 pf typ DYNAMIC CHARACTERISTICS Transition Time, ttransition 3 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 3 V; see Figure 3 ton (EN) 255 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 3 V; see Figure 3 toff (EN) 25 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 3 V; see Figure 3 Break-Before-Make Time Delay, tbbm 8 ns typ RL = 3 Ω, CL = 35 pf ns min VS = VS2 = 3 V; see Figure 3 Charge Injection 3 pc typ VS = V, RS = Ω, CL = nf; see Figure 33 Off Isolation 8 db typ RL = 5 Ω, CL = 5 pf, f = khz; see Figure 26 Channel-to-Channel Crosstalk 8 db typ RL = 5 Ω, CL = 5 pf, f = khz; see Figure 27 Total Harmonic Distortion + Noise.3 % typ RL = Ω, 2.5 V pp, f = 2 Hz to 2 khz; see Figure 29 3 db Bandwidth 85 MHz typ RL = 5 Ω, CL = 5 pf; see Figure 28 Insertion Loss.28 db typ RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 28 CS (Off) 33 pf typ VS = V, f = MHz CD (Off) 65 pf typ VS = V, f = MHz CD, CS (On) 45 pf typ VS = V, f = MHz POWER REQUIREMENTS VDD = +5.5 V, VSS = 5.5 V IDD. µa typ Digital inputs = V or VDD. µa max ISS. µa typ Digital inputs = V or VDD. µa max VDD/VSS ±4.5/±6.5 V min/max = V Guaranteed by design, not subject to production test. Rev. B Page 5 of 6

6 ADG436 Data Sheet CONTINUOUS CURRENT PER CHANNEL Table 4. Parameter 25 C 85 C 25 C Unit Test Conditions/Comments CONTINUOUS CURRENT PER CHANNEL 5 V Dual Supply VDD = +3.5 V, VSS = 3.5 V ADG436 TSSOP 26 7 ma max ADG436 LFCSP ma max 2 ingle Supply VDD =.8 V, VSS = V ADG436 TSSOP 24 6 ma max ADG436 LFCSP ma max 5 V Dual Supply VDD = +4.5 V, VSS = 4.5 V ADG436 TSSOP 24 6 ma max ADG436 LFCSP ma max Guaranteed by design, not subject to production test. Rev. B Page 6 of 6

7 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25 C, unless otherwise noted. Table 5. Parameter Ratings VDD to VSS 35 V VDD to.3 V to +25 V VSS to +.3 V to 25 V Analog Inputs VSS.3 V to VDD +.3 V or 3 ma, whichever occurs first Digital Inputs.3 V to VDD +.3 V or 3 ma, whichever occurs first Peak Current, S or D 6 ma (pulsed at ms, % duty cycle maximum) Continuous Current per Data + 5% Channel, S or D 2 Operating Temperature Range Automotive (Y Version) 4 C to +25 C Storage Temperature Range 65 C to +5 C Junction Temperature 5 C 6-Lead TSSOP, θja Thermal 2 C/W Impedance (4-Layer Board) 6-Lead LFCSP, θja Thermal 3.4 C/W Impedance Reflow Soldering Peak 26(+/ 5) C Temperature, Pb Free ADG436 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION Over voltages at IN, S, and D are clamped by internal diodes. Current must be limited to the maximum ratings given. 2 See data given in Table 4. Rev. B Page 7 of 6

8 ADG436 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS SA IN NC NC IN SA 2 D 3 6 NC 5 NC 4 NC ADG436 SB 4 3 TOP VIEW S 5 (Not to Scale) 2 S2B 6 D2 NC 7 S2A NC 8 9 IN2 NC = NO CONNECT Figure 3.TSSOP Pin Configuration D SB S 2 EN 2 ADG436 TOP VIEW 3 (Not to Scale) S2B 4 9 D2 NC IN2 NC S2A NOTES. EXPOSED PAD TIED TO SUBSTRATE, S. 2. NC = NO CONNECT. Figure 4. LFCSP Pin Configuration Table 6. Pin Function Descriptions Pin No. TSSOP LFCSP Mnemonic Function 5 IN Logic Control Input. 2 6 SA Source Terminal. Can be an input or output. 3 D Drain Terminal. Can be an input or output. 4 2 SB Source Terminal. Can be an input or output. 5 3 VSS Most Negative Power Supply Potential. 6 4 Ground ( V) Reference. 7, 8, 4 to 6 5, 7, 3, 4 NC No Connect. 9 6 IN2 Logic Control Input. 8 S2A Source Terminal. Can be an input or output. 9 D2 Drain Terminal. Can be an input or output. 2 S2B Source Terminal. Can be an input or output. 3 VDD Most Positive Power Supply Potential. N/A 2 EN Active High Digital Input. When this pin is low, the device is disabled and all switches are off. When this pin is high, INx logic inputs determine the on switches. TRUTH TABLE FOR SWITCHES Table 7. ADG436 TSSOP Truth Table INx SxA SxB Off On On Off Table 8. ADG436 LFCSP Truth Table EN INx SxA SxB X Off Off Off On On Off Rev. B Page 8 of 6

9 Data Sheet ADG436 TYPICAL PERFORMANCE CHARACTERISTICS ON RESISTANCE (Ω) = +V, S = V = +3.5V, S = 3.5V = +2V, S = 2V = +5V, S = 5V = +6.5V, S = 6.5V ON RESISTANCE (Ω) T A = +25 C T A = +85 C T A = +25 C T A = 4 C.5 I S = ma OR V D (V) Figure 5. On Resistance vs. VD or VS, Dual Supply = +5V S = 5V I S = ma OR V D (V) Figure 8. On Resistance vs. VD or VS for Different Temperatures, 5 V Dual Supply ON RESISTANCE (Ω) = +4.5V, S = 4.5V = +5V, S = 5V.5 I S = ma OR V D (V) = +5.5V, S = 5.5V Figure 6. On Resistance vs. VD or VS, Dual Supply = +7V, S = 7V ON RESISTANCE (Ω) T A = +25 C T A = +85 C T A = +25 C T A = 4 C.5 = +5V S = 5V I S = ma OR V D (V) Figure 9. On Resistance vs. VD or VS for Different Temperatures, 5 V Dual Supply = 5V, S = V ON RESISTANCE (Ω) = 8V, S = V = 3.2V, S = V I S = ma OR V D (V) =.8V, S = V = 2V, S = V = 5V, S = V ON RESISTANCE (Ω) T A = +25 C T A = +85 C T A = +25 C T A = 4 C..5 = 2V S = V I S = ma OR V D (V) Figure 7. On Resistance vs. VD or VS, Single Supply Figure. On Resistance vs. VD or VS for Different Temperatures, Single Supply Rev. B Page 9 of 6

10 ADG436 Data Sheet I DD PER LOGIC INPUT 6 LEAKAGE (na) I S (OFF) + I D (OFF) + I S (OFF) + I D (OFF) + I D, I S (ON) + + I D, I S (ON) I DD (µa) = +2V S = V = +5V S = 5V 5 2 V 6 DD = +5V S = 5V V BIAS = +V/ V TEMPERATURE ( C) Figure. Leakage Currents vs. Temperature, 5 V Dual Supply 687- = +5V S = 5V LOGIC, Ax (V) Figure 4. IDD vs. Logic Level LEAKAGE (na) I S (OFF) + I D (OFF) + I S (OFF) + I D (OFF) + I D, I S (ON) + + I D, I S (ON) CHARGE INJECTION (pc) = +5V, S = 5V = +5V, S = 5V = +2V, S = V 2. = +5V S = 5V V BIAS = +4.5V/ 4.5V TEMPERATURE ( C) Figure 2. Leakage Currents vs. Temperature, 5 V Dual Supply (V) Figure 5. Charge Injection vs. Source Voltage LEAKAGE (na) I S (OFF) + I D (OFF) + I S (OFF) + I D (OFF) + I D, I S (ON) + + I D, I S (ON) = 2V S = V V BIAS = V/V TEMPERATURE ( C) Figure 3. Leakage Currents vs. Temperature, 2 ingle Supply TIME (ns) = +5V S = 5V = +2V S = V TEMPERATURE ( C) = +5V S = 5V Figure 6. ttransition Time vs. Temperature Rev. B Page of 6

11 Data Sheet ADG436 2 = +5V S = 5V 2 = +5V S = 5V V p-p =.63V OFF ISOLATION (db) ACPSRR (db) NO DECOUPLING CAPACITORS DECOUPLING CAPACITORS ON SUPPLIES k k k M M M G FREQUENCY (Hz) Figure 7. Off Isolation vs. Frequency k k k M M FREQUENCY (Hz) Figure 2. ACPSRR vs. Frequency = +5V S = 5V = +5V S = 5V = 2V p-p CROSSTALK (db) CHANNEL-TO-CHANNEL (SxA TO SxB) MUX-TO-MUX (Sx TO S2x) THD + N (%) = 5V p-p = V p-p.4 2 k k k M FREQUENCY (Hz) M M k k k FREQUENCY (Hz) Figure 8. Crosstalk vs. Frequency Figure 2. THD + N vs. Frequency, 5 V Dual Supply.5. = +5V S = 5V = +5V S = 5V = V p-p INSERTION LOSS (db) THD + N (%).. = 5V p-p = 2.5V p-p k k k M M FREQUENCY (Hz) M G k k k FREQUENCY (Hz) Figure 9. On Response vs. Frequency Figure 22. THD + N vs. Frequency, 5 V Dual Supply Rev. B Page of 6

12 ADG436 TERMINOLOGY IDD The positive supply current. ISS The negative supply current. VD, VS The analog voltage on Terminal D and Terminal S. RON The ohmic resistance between Terminal D and Terminal S. RFLAT(ON) Flatness that is defined as the difference between the maximum and minimum value of on resistance measured over the specified analog signal range. IS (Off) The source leakage current with the switch off. ID (Off) The drain leakage current with the switch off. ID, IS (On) The channel leakage current with the switch on. VINL The maximum input voltage for Logic. VINH The minimum input voltage for Logic. IINL, IINH The input current of the digital input. CS (Off) The off-switch source capacitance, which is measured with reference to ground. Data Sheet CD (Off) The off-switch drain capacitance, which is measured with reference to ground. CD, CS (On) The on-switch capacitance, which is measured with reference to ground. CIN The digital input capacitance. ttransition The delay time between the 5% and 9% points of the digital input and switch on condition when switching from one address state to another. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Off Isolation A measure of unwanted signal coupling through an off switch. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Bandwidth The frequency at which the output is attenuated by 3 db. On Response The frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. THD + N The ratio of the harmonic amplitude plus noise of the signal to the fundamental. Rev. B Page 2 of 6

13 Data Sheet ADG436 TEST CIRCUITS DD S.µFV.µF S NC NETWORK ANALYZER 5Ω INx SxA SxB 5Ω SxA/SxB V R L 5Ω I DS Figure 23. On Resistance OFF ISOLATION = 2 log Figure 26. Off Isolation DD S.µFV.µF S NC NETWORK ANALYZER 5Ω INx SxA SxB 5Ω I S (OFF) A SxA/SxB I D (OFF) A R L 5Ω V D WITH SWITCH INSERTION LOSS = 2 log WITHOUT SWITCH Figure 24. Off Leakage Figure 27. Channel-to-Channel Crosstalk DD S.µFV.µF NETWORK ANALYZER R L 5Ω SxA SxB S R 5Ω INx NC SxA/SxB I D (ON) A NC = NO CONNECT Figure 25. On Leakage V D CHANNEL-TO-CHANNEL CROSSTALK = 2 log Figure 28. Bandwidth Rev. B Page 3 of 6

14 ADG436 Data Sheet DD S.µFV.µF INx SxA/SxB S R L Ω Figure 29. THD + Noise AUDIO PRECISION R S V p-p µF S.µF 5% 5% SxB SxA S 5% 5% INx R L 3Ω C L 35pF 9% 9% t ON t OFF Figure 3. Switching Times.µF S.µF S SxB SxA INx R L 3Ω C L 35pF 8% t BBM t BBM Figure 3. Break-Before-Make Time Delay Rev. B Page 4 of 6

15 Data Sheet ADG436 S 3V S ENABLE DRIVE ( ) 5% 5% INx SxA V SxB t ON (EN) t OFF (EN).9.9 EN OUTPUT OUTPUT 5Ω 3Ω 35pF Figure 32. Enable Delay, ton (EN), toff (EN) µF S.µF S SxB SxA INx C L nf NC (NORMALLY CLOSED SWITCH) (NORMALLY OPEN SWITCH) ON Q INJ = C L OFF Figure 33. Charge Injection Rev. B Page 5 of 6

16 ADG436 Data Sheet OUTLINE DIMENSIONS BSC PIN.65 BSC.3.9 COPLANARITY..2 MAX SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-53-AB Figure Lead Thin Shrink Small Outline Package [TSSOP] (RU-6) Dimensions shown in millimeters PIN INDICATOR SQ BSC PIN INDICATOR EXPOSED PAD SQ SEATING PLANE TOP VIEW MAX.2 NOM COPLANARITY.8.2 REF BOTTOM VIEW COMPLIANT TO JEDEC STANDARDS MO-22-WGGC. Figure Lead Lead Frame Chip Scale Package [LFCSP] 4 mm 4 mm Body and.75 mm Package Height (CP-6-26) Dimensions shown in millimeters FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. ORDERING GUIDE Model Temperature Range Package Description Package Option ADG436YRUZ 4 C to +25 C 6-Lead Thin Shrink Small Outline Package [TSSOP] RU-6 ADG436YRUZ-REEL7 4 C to +25 C 6-Lead Thin Shrink Small Outline Package [TSSOP] RU-6 ADG436YCPZ-REEL 4 C to +25 C 6-Lead Lead Frame Chip Scale Package [LFCSP] CP-6-26 ADG436YCPZ-REEL7 4 C to +25 C 6-Lead Lead Frame Chip Scale Package [LFCSP] CP-6-26 Z = RoHS Compliant Part A Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D687--9/6(B) Rev. B Page 6 of 6

1 Ω Typical On Resistance, ±5 V, +12 V, +5 V, and +3.3 V Dual SPDT Switches ADG1636

1 Ω Typical On Resistance, ±5 V, +12 V, +5 V, and +3.3 V Dual SPDT Switches ADG1636 FEATURES Ω typical on resistance.2 Ω on resistance flatness ±3.3 V to ±8 V dual supply operation 3.3 V to 6 V single supply operation No VL supply required 3 V logic-compatible inputs Rail-to-rail operation