CMOS 3 V/5 V, Wide Bandwidth Quad 2:1 Mux ADG774
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1 a FEATURES Low Insertion Loss and On Resistance: 2.2 Typical On Resistance Flatness.5 Typical Automotive Temperature Range 4 C to +125 C 3 db Bandwidth = 24 MHz Single 3 V/5 upply Operation Rail-to-Rail Operation Very Low Distortion:.5% Low Quiescent Supply Current (1 na Typical) Fast Switching Times t ON 7 ns t OFF 4 ns TTL/CMOS Compatible APPLICATIONS USB 1.1 Signal Switching Circuits Cell Phones PDAs Battery-Powered Systems Communications Systems Data Acquisition Systems Token Ring 4 Mbps/16 Mbps Audio and Video Switching Relay Replacement CMOS 3 V/5 V, Wide Bandwidth Quad 2:1 Mux ADG774 FUNCTIONAL BLOCK DIAGRAM S1A S1B S2A S2B S3A S3B S4A S4B ADG774 1 OF 2 DECODER D1 D2 D3 D4 GERAL DESCRIPTION The ADG774 is a monolithic CMOS device comprising four 2:1 multiplexer/demultiplexers with high impedance outputs. The CMOS process provides low power dissipation yet gives high switching speed and low on resistance. The on resistance variation is typically less than.5 Ω with an input signal ranging from V to 5 V. The bandwidth of the ADG774 is greater than 2 MHz; this, coupled with low distortion (typically.5%), makes the part suitable for switching USB 1.1 data signals and fast Ethernet signals. The on resistance profile is very flat over the full analog input range ensuring excellent linearity and low distortion when switching audio signals. Fast switching speed, coupled with high signal bandwidth, also makes the parts suitable for video signal switching. CMOS construction ensures ultralow power dissipation, making the parts ideally suited for portable and batterypowered instruments. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. The ADG774 operates from a single 3.3 V/5 V supply and is TTL logic compatible. The control logic for each switch is shown in the Truth Table. These switches conduct equally well in both directions when ON, and have an input signal range that extends to the supplies. In the OFF condition, signal levels up to the supplies are blocked. The ADG774 switches exhibit break-before-make switching action. PRODUCT HIGHLIGHTS 1. Wide 3 db Bandwidth, 24 MHz. 2. Ultralow Power Dissipation. 3. Extended Signal Range. The ADG774 is fabricated on a CMOS process giving an increased signal range that fully extends to the supply rails. 4. Low Leakage Over Temperature. 5. Break-Before-Make Switching. This prevents channel shorting when the switches are configured as a multiplexer. 6. Crosstalk Typically 7 3 MHz. 7. Off Isolation Typically 6 1 MHz. One Technology Way, P.O. Box 916, Norwood, MA , U.S.A. Tel: 781/ Fax: 781/ Analog Devices, Inc. All rights reserved.
2 SPECIFICATIONS SGLE SUPPLY ( = 5 V 1%, GND = V. All specifications T M to T MAX unless otherwise noted.) B Version 1 4 C to 4 C to Parameter +25 C +85 C +125 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V to V On Resistance (R ON ) 2.2 Ω typ V D = V to, I S = 1 ma 5 7 Ω max On Resistance Match between Channels ( R ON ).15 Ω typ V D = V to, I S = 1 ma.5.5 Ω max On Resistance Flatness (R FLAT(ON) ).5 Ω typ V D = V to, I S = 1 ma 1 1 Ω max LEAKAGE CURRTS Source OFF Leakage I S (OFF) ±.1 na typ V D = 4.5 V, = 1 V; V D = 1 V, = 4.5 V; ±.5 ± 1 ±1.5 na max Test Circuit 2 Drain OFF Leakage I D (OFF) ±.1 na typ V D = 4.5 V, = 1 V; V D = 1 V, = 4.5 V; ±.5 ± 1 ±1.5 na max Test Circuit 2 Channel ON Leakage I D, I S (ON) ±.1 na typ V D = = 4.5 V; V D = = 1 V; Test Circuit 3 ±.5 ± 1 ±1.5 na max DIGITAL PUTS Input High Voltage, V H 2. V min Input Low Voltage, V L.8 V max Input Current I L or I H.1 µa typ V = V L or V H ±.5 µa max DYNAMIC CHARACTERISTICS 2 t ON 7 ns typ R L = 1 Ω, C L = 35 pf, 15 2 ns max = +3 V; Test Circuit 4 t OFF 4 ns typ R L = 1 Ω, C L = 35 pf, 8 9 ns max = +3 V; Test Circuit 4 Break-Before-Make Time Delay, t D 5 ns typ R L = 1 Ω, C L = 35 pf, 1 ns min 1 = 2 = +5 V; Test Circuit 5 Off Isolation 65 db typ R L = 1 Ω, f = 1 MHz; Test Circuit 7 Channel-to-Channel Crosstalk 75 db typ R L = 1 Ω, f = 1 MHz; Test Circuit 8 Bandwidth 3 db 24 MHz typ R L = 1 Ω; Test Circuit 6 Distortion.5 % typ R L = 1 Ω Charge Injection 1 pc typ C L = 1 nf; Test Circuit 9 C S (OFF) 1 pf typ f = 1 khz C D (OFF) 2 pf typ f = 1 khz C D, C S (ON) 3 pf typ f = 1 MHz POWER REQUIREMTS = +5.5 V Digital Inputs = V or I DD 1 1 µa max.1 µa typ I 1 1 µa typ V = +5 V I O 1 ma max /V D = V NOTES 1 Temperature range: B Version, 4 C to +125 C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice. 2 REV. C
3 SGLE SUPPLY ADG774 B Version 1 4 C to 4 C to Parameter +25 C +85 C +125 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V to V On Resistance (R ON ) 4 Ω typ V D = V to, I S = 1 ma 8 9 Ω max On Resistance Match between Channels ( R ON ).15 Ω typ V D = V to, I S = 1 ma.5.5 Ω max On Resistance Flatness (R FLAT(ON) ) 2 Ω typ V D = V to, I S = 1 ma 4 4 Ω max LEAKAGE CURRTS Source OFF Leakage I S (OFF) ±.1 na typ V D = 3 V, = 1 V; V D = 1 V, = 3 V; ±.5 ± 1 ±1.5 na max Test Circuit 2 Drain OFF Leakage I D (OFF) ±.1 na typ V D = 3 V, = 1 V; V D = 1 V, = 3 V; ±.5 ± 1 ±1.5 na max Test Circuit 2 Channel ON Leakage I D, I S (ON) ±.1 na typ V D = = 3 V; V D = = 1 V; Test Circuit 3 ±.5 ± 1 ±1.5 na max DIGITAL PUTS Input High Voltage, V H 2. V min Input Low Voltage, V L.8 V max Input Current I L or I H.1 µa typ V = V L or V H ±.5 µa max DYNAMIC CHARACTERISTICS 2 t ON 8 ns typ R L = 1 Ω, C L = 35 pf, ns max = +1.5 V; Test Circuit 4 t OFF 5 ns typ R L = 1 Ω, C L = 35 pf, 1 11 ns max = +1.5 V; Test Circuit 4 Break-Before-Make Time Delay, t D 5 ns typ R L = 1 Ω, C L = 35 pf, 1 ns min 1 = 2 = 3 V; Test Circuit 5 Off Isolation 65 db typ R L = 5 Ω, f = 1 MHz; Test Circuit 7 Channel-to-Channel Crosstalk 75 db typ R L = 5 Ω, f = 1 MHz; Test Circuit 8 Bandwidth 3 db 24 MHz typ R L = 5 Ω; Test Circuit 6 Distortion 2 % typ R L = 5 Ω Charge Injection 3 pc typ C L = 1 nf; Test Circuit 9 C S (OFF) 1 pf typ f = 1 khz C D (OFF) 2 pf typ f = 1 khz C D, C S (ON) 3 pf typ f = 1 MHz POWER REQUIREMTS = +3.3 V Digital Inputs = V or I DD 1 1 µa max.1 µa typ I 1 1 µa typ V = +3 V I O 1 ma max /V D = V NOTES 1 Temperature range: B Version, 4 C to +125 C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice. ( = 3 V 1%, GND = V. All specifications T M to T MAX unless otherwise noted.) Table I. Truth Table D1 D2 D3 D4 Function 1 X Hi-Z Hi-Z Hi-Z Hi-Z DISABLE S1A S2A S3A S4A = 1 S1B S2B S3B S4B = 1 REV. C 3
4 ABSOLUTE MAXIMUM RATGS 1 (T A = 25 C unless otherwise noted.) to GND V to +6 V Analog, Digital Inputs V to +.3 V or 3 ma, Whichever Occurs First Continuous Current, S or D ma Peak Current, S or D ma (Pulsed at 1 ms, 1% Duty Cycle max) Operating Temperature Range Industrial (B Version) C to +125 C Storage Temperature Range C to +15 C Junction Temperature C SOIC Package, Power Dissipation mw JA Thermal Impedance C/W QSOP Package, Power Dissipation mw JA Thermal Impedance C/W Lead Temperature, Soldering (1 sec) C I R Reflow, Peak Temperature (<2 sec) C ESD kv NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 Overvoltages at, S, or D will be clamped by internal diodes. Current should be limited to the maximum ratings given. ORDERG GUIDE Model Temperature Range Package Descriptions Package Options ADG774BR 4 C to +125 C Standard Small Outline Package (SOIC) R-16 ADG774BR-REEL 4 C to +125 C Standard Small Outline Package (SOIC) R-16 ADG774BR-REEL7 4 C to +125 C Standard Small Outline Package (SOIC) R-16 ADG774BRZ* 4 C to +125 C Standard Small Outline Package (SOIC) R-16 ADG774BRZ-REEL* 4 C to +125 C Standard Small Outline Package (SOIC) R-16 ADG774BRZ-REEL7* 4 C to +125 C Standard Small Outline Package (SOIC) R-16 ADG774BRQ 4 C to +125 C Shrink Small Outline Package (QSOP) RQ-16 ADG774BRQ-REEL 4 C to +125 C Shrink Small Outline Package (QSOP) RQ-16 ADG774BRQ-REEL7 4 C to +125 C Shrink Small Outline Package (QSOP) RQ-16 ADG774BRQZ* 4 C to +125 C Shrink Small Outline Package (QSOP) RQ-16 ADG774BRQZ-REEL* 4 C to +125 C Shrink Small Outline Package (QSOP) RQ-16 ADG774BRQZ-REEL7* 4 C to +125 C Shrink Small Outline Package (QSOP) RQ-16 *Z = Pb-free part. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG774 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. 4 REV. C
5 P CONFIGURATION (SOIC/QSOP) S1A S1B D1 S2A S2B D2 GND ADG774 TOP VIEW 5 (Not to Scale) S4A S4B D4 S3A S3B D3 TERMOLOGY Most Positive Power Supply Potential. GND Ground ( V) Reference. S Source Terminal. May be an input or output. D Drain Terminal. May be an input or output. Logic Control Input. Logic Control Input. R ON Ohmic Resistance between D and S. R ON On Resistance Match between any Two Channels, i.e., R ON max R ON min. R FLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. I S (OFF) Source Leakage Current with the Switch OFF. I D (OFF) Drain Leakage Current with the Switch OFF. I D, I S (ON) Channel Leakage Current with the Switch ON. V D ( ) Analog Voltage on Terminals D, S. C S (OFF) OFF Switch Source Capacitance. C D (OFF) OFF Switch Drain Capacitance. C D, C S (ON) ON Switch Capacitance. t ON Delay between Applying the Digital Control Input and the Output Switching on. See Test Circuit 4. t OFF Delay between Applying the Digital Control Input and the Output Switching Off. t D OFF Time or ON Time Measured between the 9% Points of Both Switches, When Switching from One Address State to Another. See Test Circuit 5. Crosstalk A Measure of Unwanted Signal that is Coupled through from One Channel to Another as a Result of Parasitic Capacitance. Off Isolation A Measure of Unwanted Signal Coupling through an OFF Switch. Bandwidth Frequency Response of the Switch in the ON State Measured at 3 db Down. Distortion R FLAT(ON) /R L REV. C 5
6 Typical Performance Characteristics = 2.7V T A = 25 C = 5V R ON = 3.V = 4.5V = 5.V ON RESPONSE db OR V D DRA OR SOURCE VOLTAGE V 6 1k 1k 1M 1M 1M FREQUCY Hz TPC 1. On Resistance as a Function of V D ( ) for Various Single Supplies TPC 4. On Response vs. Frequency = 5V 1 2 = 5V R L = 1 R ON C +25 C 4 C ATTUATION db OR V O DRA OR SOURCE VOLTAGE V 1 1k 1M 1M 1M FREQUCY Hz 1G TPC 2. On Resistance as a Function of V D ( ) for Different Temperatures with 5 ingle Supplies TPC 5. Off Isolation vs. Frequency = 3V +85 C 1 2 = 5V R L = 1 V P-P =.316V R ON C 4 C ATTUATION db OR V D DRA OR SOURCE VOLTAGE V 1 1k 1M 1M 1M FREQUCY Hz 1G TPC 3. On Resistance as a Function of V D ( ) for Different Temperatures with 3 ingle Supplies TPC 6. Crosstalk vs. Frequency 6 REV. C
7 2 15 = 5V T A = 25 C TX1 CHARGE JECTION pc 1 5 RX1 Figure 1. Loop Back SOURCE VOLTAGE V 12 1 TPC 7. Charge Injection vs. Source Voltage Figure 2. Line Termination Figure 3. Line Clamp REV. C 7
8 Test Circuits I DS S V1 D I S (OFF) A S D I D (OFF) A S D I D (ON) A R ON = V1/I DS V D V D Test Circuit 1. On Resistance Test Circuit 2. Off Leakage Test Circuit 3. On Leakage 5V.1 F V 3V 5% 5% S D V OUT 9% 9% R L 1 C L 35pF V OUT GND t ON t OFF Test Circuit 4. Switching Times.1 F 5V 3V S1A V V 5% 5% D1 OUT S1B V V R L C L V 5% 5% S OUT 1 35pF DECODER t D t D GND Test Circuit 5. Break-Before-Make Time Delay 8 REV. C
9 5V 5V.1 F.1 F 5V.1 F D1 R L 1 V OUT S1A D1 1 S1A S1B D1 R L 1 V OUT V V GND GND NC S2A D2 V OUT Test Circuit 6. Bandwidth GND R L 1 Test Circuit 8. Off Isolation V CHANNEL-TO-CHANNEL CROSSTALK = 2 LOG /V OUT Test Circuit 7. Channel-to-Channel Crosstalk 5V ADG774 R S S1A S1B S2A C L 1nF D1 V OUT V 3V S2B S3A C L 1nF D2 V OUT V OUT V OUT S3B S4A C L 1nF D3 V OUT Q J = C L V OUT S4B C L 1nF D4 V OUT 1 OF 2 DECODER Test Circuit 9. Charge Injection REV. C 9
10 OUTLE DIMSIONS 16-Lead Standard Small Outline Package [SOIC] Narrow Body (R-16) Dimensions shown in millimeters and (inches) 1. (.3937) 9.8 (.3858) 4. (.1575) 3.8 (.1496) (.2441) 5.8 (.2283).25 (.98).1 (.39) COPLANARITY (.5) BSC.51 (.21).31 (.122) 1.75 (.689) 1.35 (.531) SEATG PLANE.25 (.98).17 (.67) COMPLIANT TO JEDEC STANDARDS MS-12AC CONTROLLG DIMSIONS ARE MILLIMETERS; CH DIMSIONS ( PARTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALTS FOR REFERCE ONLY AND ARE NOT APPROPRIATE FOR USE DESIGN 8.5 (.197) (.98) 1.27 (.5).4 (.157) 16-Lead Shrink Small Outline Package [QSOP] (RQ-16) Dimensions shown in inches.193 BSC BSC.236 BSC P COPLANARITY.4.25 BSC.12.8 SEATG PLANE.1.6 COMPLIANT TO JEDEC STANDARDS MO-137AB REV. C
11 Revision History Location Page 3/4 Data Sheet changed from REV. B to REV. C. Added APPLICATIONS Changes to ORDERG GUIDE /3 Data Sheet changed from REV. A to REV. B. Updated formatting universal Renumbered TPCs amd Figures Universal Changes to FEATURES Changes to APPLICATIONS Changes to PRODUCT HIGHLIGHTS Changes to SPECIFICATIONS Changes to ABSOLUTE MAXIMUM RATGS Updated ORDERG GUIDE Delete Figure Updated OUTLE DIMSIONS /3 Data Sheet changed from REV. to REV. A. Renumbered TPCs and Figures Universal Updated OUTLE DIMSIONS REV. C 11
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