1 pc Charge Injection, 100 pa Leakage, CMOS, ±5 V/+5 V/+3 V Dual SPDT Switch ADG636

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1 pc Charge Injection, pa Leakage, CMOS, ±5 V/+5 V/+3 V Dual SPDT Switch ADG636 FEATURES pc charge injection ±2.7 V to ±5.5 V dual supply +2.7 V to +5.5 V single supply Automotive temperature range: 4 C to +25 C pa (maximum at 25 C) leakage currents 85 Ω typical on resistance Rail-to-rail operation Fast switching times Typical power consumption (<. μw) TTL-/CMOS-compatible inputs 4-lead TSSOP package APPLICATIONS Automatic test equipment Data acquisition systems Battery-powered instruments Communication systems Sample-and-hold systems Remote-powered equipment Audio and video signal routing Relay replacement Avionics GENERAL DESCRIPTION The ADG636 is a monolithic device, comprising two independently selectable CMOS single pole, double throw (SPDT) switches. When on, each switch conducts equally well in both directions. The ADG636 operates from a dual ±2.7 V to ±5.5 V supply, or from a single supply of +2.7 V to +5.5 V. This switch offers ultralow charge injection of ±.5 pc over the entire signal range and leakage current of pa typical at 25 C. In addition, it offers on resistance of 85 Ω typical, which is matched to within 2 Ω between channels. The ADG636 also has low power dissipation yet is capable of high switching speeds. The ADG636 exhibits break-before-make switching action and is available in a 4-lead TSSOP package. FUNCTIONAL BLOCK DIAGRAM SA SB 4 5 S2A S2B ADG636 LOGIC 4 2 A A EN Figure. PRODUCT HIGHLIGHTS. Ultralow charge injection. QINJ: ±.5 pc typical over the full signal range. 2. Leakage current <.25 na maximum at 85 C. 3. Dual ±2.7 V to ±5 V or single +2.7 V to +5.5 V supply. 4. Automotive temperature range: 4 C to +25 C. 5. Small 4-lead TSSOP package. 6 9 D D Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA , U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 TABLE OF CONTENTS Features... Applications... Functional Block Diagram... General Description... Product Highlights... Revision History... 2 Specifications... 3 Dual Supply... 3 Single Supply... 5 Absolute Maximum Ratings...9 ESD Caution...9 Pin Configuration and Function Descriptions... Typical Performance Characteristics... Test Circuits... 3 Terminology... 5 Outline Dimensions... 6 Ordering Guide... 6 REVISION HISTORY 9/9 Rev. A to Rev. B Changes to Table /8 Rev. to Rev. A Updated Format... Universal Changes to Analog Switch Parameter... 3 Changes to Analog Switch Parameter... 5 Changes to Analog Switch Parameter... 7 Change to IDD Parameter... 8 Changes to Absolute Maximum Ratings... 9 Added Table 5; Renumbered Sequentially... Moved Truth Table... Added Endnote to Table 6... Changes to... 3 Updated Outline Dimensions... 6 Changes to Ordering Guide... 6 /2 Revision : Initial Version Rev. B Page 2 of 6

3 SPECIFICATIONS DUAL SUPPLY VDD = 5 V ± %, VSS = 5 V ± %, GND = V. All specifications 4 C to +25 C, unless otherwise noted. Table. Parameter +25 C 4 C to +85 C 4 C to +25 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range VSS to VDD V VDD = +4.5 V, VSS = 4.5 V On Resistance, RON 85 Ω typ VS = ±3 V, IDS = ma, Figure Ω max VS = ±3 V, IDS = ma, Figure 4 On-Resistance Match Between 2 Ω typ VS = ±3 V, IDS = ma Channels, ΔRON Ω max VS = ±3 V, IDS = ma On-Resistance Flatness, RFLAT(ON) 25 Ω typ VS = ±3 V, IDS = ma Ω max VS = ±3 V, IDS = ma LEAKAGE CURRENTS VDD = +5.5 V, VSS = 5.5 V Source Off Leakage, IS (Off) ±. na typ VS = ±4.5 V, VD = 4.5 V, Figure 5 ±. ±.25 ±2 na max VS = ±4.5 V, VD = 4.5 V, Figure 5 Drain Off Leakage, ID (Off) ±. na typ VS = ±4.5 V, VD = 4.5 V, Figure 5 ±. ±.25 ±2 na max VS = ±4.5 V, VD = 4.5 V, Figure 5 Channel On Leakage, ID (On), IS (On) ±. na typ VS = VD = ±4.5 V, Figure 6 ±. ±.25 ±6 na max VS = VD = ±4.5 V, Figure 6 DIGITAL INPUTS Input High Voltage, VINH 2.4 V min Input Low Voltage, VINL.8 V max Input Current, IINL or IINH.5 μa typ VIN = VINL or VINH ±. μa max VIN = VINL or VINH Digital Input Capacitance, CIN 2 pf typ DYNAMIC CHARACTERISTICS Transition Time 7 ns typ VSA = +3 V, VSB = 3 V, RL = 3 Ω, CL = 35 pf, Figure ns max VSA = +3 V, VSB = 3 V, RL = 3 Ω, CL = 35 pf, Figure 7 ton Enable ns typ RL = 3 Ω, CL = 35 pf, VS = 3 V, ns max RL = 3 Ω, CL = 35 pf, VS = 3 V, toff Enable 55 ns typ RL = 3 Ω, CL = 35 pf, VS = 3 V, 8 9 ns max RL = 3 Ω, CL = 35 pf, VS = 3 V, Break-Before-Make Time Delay, tbbm 2 ns typ RL = 3 Ω, CL = 35 pf, VS = 3 V, Figure 8 ns min RL = 3 Ω, CL = 35 pf, VS = 3 V, Figure 8 Charge Injection.2 pc typ VS = V, RS = Ω, CL = nf, Figure 2 Off Isolation 65 db typ RL = 5 Ω, CL = 5 pf, f = MHz, Figure 2 Channel-to-Channel Crosstalk 65 db typ RL = 5 Ω, CL = 5 pf, f = MHz, Figure 23 Bandwidth 3 db 6 MHz typ RL = 5 Ω, CL = 5 pf, Figure 22 Rev. B Page 3 of 6

4 Parameter +25 C 4 C to +85 C 4 C to +25 C Unit Test Conditions/Comments CS (Off) 5 pf typ f = MHz CD (Off) 8 pf typ f = MHz CD (On), CS (On) 8 pf typ f = MHz POWER REQUIREMENTS VDD = +5.5 V, VSS = 5.5 V IDD. μa typ Digital inputs = V or 5.5 V. μa max Digital inputs = V or 5.5 V ISS. μa typ Digital inputs = V or 5.5 V. μa max Digital inputs = V or 5.5 V Guaranteed by design; not subject to production test. Rev. B Page 4 of 6

5 SINGLE SUPPLY VDD = 5 V ± %, VSS = V, GND = V. All specifications 4 C to +25 C, unless otherwise noted. Table 2. Parameter +25 C 4 C to +85 C 4 C to +25 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V to VDD V VDD = 4.5 V, VSS = V On Resistance, RON 2 Ω typ VS = 3.5 V, IDS = ma, Figure Ω max VS = 3.5 V, IDS = ma, Figure 4 On Resistance Match Between Channels, ΔRON 3 Ω typ VS = 3.5 V, IDS = ma 2 3 Ω max VS = 3.5 V, IDS = ma LEAKAGE CURRENTS VDD = 5.5 V Source Off Leakage, IS (Off) ±. na typ VS = V/4.5 V, VD = 4.5 V/ V, Figure 5 ±. ±.25 ±2 na max VS = V/4.5 V, VD = 4.5 V/ V, Figure 5 Drain Off Leakage, ID (Off) ±. na typ VS = V/4.5 V, VD = 4.5 V/ V, Figure 5 ±. ±.25 ±2 na max VS = V/4.5 V, VD = 4.5 V/ V, Figure 5 Channel On Leakage, ID (On), IS (On) ±. na typ VS = VD = 4.5 V/ V, Figure 6 ±. ±.25 ±6 na max VS = VD = 4.5 V/ V, Figure 6 DIGITAL INPUTS Input High Voltage, VINH 2.4 V min Input Low Voltage, VINL.8 V max Input Current, IINL or IINH.5 μa typ VIN = VINL or VINH ±. μa max VIN = VINL or VINH Digital Input Capacitance, CIN 2 pf typ DYNAMIC CHARACTERISTICS Transition Time 9 ns typ VSA = 3 V, VSB = V, RL = 3 Ω, CL = 35 pf, Figure ns max VSA = 3 V, VSB = V, RL = 3 Ω, CL = 35 pf, Figure 7 ton Enable 35 ns typ RL = 3 Ω, CL = 35 pf, VS = 3 V, ns max RL = 3 Ω, CL = 35 pf, VS = 3 V, toff Enable 7 ns typ RL = 3 Ω, CL = 35 pf, VS = 3 V, ns max RL = 3 Ω, CL = 35 pf, VS = 3 V, Break-Before-Make Time Delay, tbbm 3 ns typ RL = 3 Ω, CL = 35 pf, VS = 3 V, Figure 8 ns min RL = 3 Ω, CL = 35 pf, VS = 3 V, Figure 8 Charge Injection.3 pc typ VS = V, RS = Ω, CL = nf, Figure 2 Off Isolation 6 db typ RL = 5 Ω, CL = 5 pf, f = MHz, Figure 2 Channel-to-Channel Crosstalk 65 db typ RL = 5 Ω, CL = 5 pf, f = MHz, Figure 23 Bandwidth 3 db 53 MHz typ RL = 5 Ω, CL = 5 pf, Figure 22 CS (Off) 5 pf typ f = MHz CD (Off) 8 pf typ f = MHz CD (On), CS (On) 8 pf typ f = MHz Rev. B Page 5 of 6

6 Parameter +25 C 4 C to +85 C 4 C to +25 C Unit Test Conditions/Comments POWER REQUIREMENTS VDD = 5.5 V IDD. μa typ Digital inputs = V or 5.5 V. μa max Digital inputs = V or 5.5 V Guaranteed by design; not subject to production test. Rev. B Page 6 of 6

7 VDD = 3 V ± %, VSS = V, GND = V. All specifications 4 C to +25 C, unless otherwise noted. Table 3. Parameter +25 C 4 C to +85 C 4 C to +25 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V to VDD V VDD = 2.7 V, VSS = V On Resistance, RON Ω typ VS =.5 V, IDS = ma, Figure 4 On Resistance Match Between Channels, ΔRON 5 Ω typ VS =.5 V, IDS = ma LEAKAGE CURRENTS VDD = 3.3 V Source Off Leakage, IS (Off) ±. na typ VS = V/3 V, VD = 3 V/ V, Figure 5 ±. ±.25 ±2 na max VS = V/3 V, VD = 3 V/ V, Figure 5 Drain Off Leakage, ID (Off) ±. na typ VS = V/3 V, VD = 3 V/ V, Figure 5 ±. ±.25 ±2 na max VS = V/3 V, VD = 3 V/ V, Figure 5 Channel On Leakage, ID (On), IS (On) ±. na typ VS = VD = V/3 V, Figure 6 ±. ±.25 ±6 na max VS = VD = V/3 V, Figure 6 DIGITAL INPUTS Input High Voltage, VINH 2. V min Input Low Voltage, VINL.8 V max Input Current, IINL or IINH.5 μa typ VIN = VINL or VINH ±. μa max VIN = VINL or VINH Digital Input Capacitance, CIN 2 pf typ DYNAMIC CHARACTERISTICS Transition Time 7 ns typ VSA = 2 V, VSB = V, RL = 3 Ω, CL = 35 pf, Figure ns max VSA = 2 V, VSB = V, RL = 3 Ω, CL = 35 pf, Figure 7 ton Enable 25 ns typ RL = 3 Ω, CL = 35 pf, VS = 2 V, ns max RL = 3 Ω, CL = 35 pf, VS = 2 V, toff Enable ns typ RL = 3 Ω, CL = 35 pf, VS = 2 V, ns max RL = 3 Ω, CL = 35 pf, VS = 2 V, Break-Before-Make Time Delay, tbbm 8 ns typ RL = 3 Ω, CL = 35 pf, VS = 2 V, Figure 8 ns min RL = 3 Ω, CL = 35 pf, VS = 2 V, Figure 8 Charge Injection.6 pc typ VS = V, RS = Ω, CL = nf, Figure 2 Off Isolation 6 db typ RL = 5 Ω, CL = 5 pf, f = MHz, Figure 2 Channel-to-Channel Crosstalk 65 db typ RL = 5 Ω, CL = 5 pf, f = MHz, Figure 23 Bandwidth 3 db 53 MHz typ RL = 5 Ω, CL = 5 pf, Figure 22 CS (Off) 5 pf typ f = MHz CD (Off) 8 pf typ f = MHz CD (On), CS (On) 8 pf typ f = MHz Rev. B Page 7 of 6

8 Parameter +25 C 4 C to +85 C 4 C to +25 C Unit Test Conditions/Comments POWER REQUIREMENTS VDD = 3.3 V IDD. μa typ Digital inputs = V or 3.3 V. μa max Digital inputs = V or 3.3 V Guaranteed by design; not subject to production test. Rev. B Page 8 of 6

9 ABSOLUTE MAXIMUM RATINGS TA = 25 C, unless otherwise noted. Table 4. Parameter Rating VDD to VSS 3 V VDD to GND.3 V to +6.5 V VSS to GND +.3 V to 6.5 V Analog Inputs VSS.3 V to VDD +.3 V Digital Inputs.3 V to VDD +.3 V or 3 ma, whichever occurs first Peak Current, S or D (Pulsed at ms, 2 ma % Duty Cycle Maximum) Continuous Current, S or D ma Operating Temperature Range 4 C to +25 C Storage Temperature Range 65 C to +5 C Junction Temperature 5 C TSSOP Package θja Thermal Impedance 5 C/W θjc Thermal Impedance 27 C/W Lead Soldering Lead Temperature, Soldering ( sec) 3 C IR Reflow, Peak Temperature (<2 sec) 22 C Pb-Free Soldering Reflow, Peak Temperature 26(+/ 5) C Time at Peak Temperature 2 sec to 4 sec Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. ESD CAUTION Overvoltages at EN, A, A, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given. Rev. B Page 9 of 6

10 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS A EN SA SB D NC ADG636 TOP VIEW (Not to Scale) 4 A 3 GND 2 S2A S2B 9 D2 8 NC NC = NO CONNECT Figure 2. Pin Configuration Table 5. Pin Function Descriptions Pin number Mnemonic Description A Digital Input (LSB). 2 EN Active High Digital Input. 3 VSS Negative Power Supply. For single-supply operation, connect this pin to GND. 4 SA Source Terminal. Can be an input or output. 5 SB Source Terminal. Can be an input or output. 6 D Drain Terminal. Can be an input or output. 7 NC Not Electrically Connected. 8 NC Not Electrically Connected. 9 D2 Drain Terminal. Can be an input or output. S2B Source Terminal. Can be an input or output. S2A Source Terminal. Can be an input or output. 2 VDD Positive Power Supply. 3 GND Ground ( V) Power Supply. 4 A Digital Input (MSB) Table 6. Truth Table A A EN On Switch X X None SA, S2A SB, S2A SA, S2B SB, S2B X = logic state doesn t matter; it can be either or. Rev. B Page of 6

11 TYPICAL PERFORMANCE CHARACTERISTICS 25 T A = 25 C, = ±3V = 5V = V ON RESISTANCE (Ω) 5 5, = ±2.5V, = ±3.3V, = ±5V, = ±4.5V ON RESISTANCE (Ω) T A = +25 C TA = +85 C T A = +25 C T A = 4 C V D, (V) Figure 3. On Resistance vs. VD (VS), Dual Supply V D, (V) Figure 6. On Resistance vs. VD (VS) for Different Temperatures, Single Supply ON RESISTANCE (Ω) T A = 25 C = V = 2.7V = 3V = 3.3V = 4.5V V D, (V) = 5V Figure 4. On Resistance vs. VD (VS), Single Supply CURRENT (na) I S (OFF) 3 = +5V = 5V TEMPERATURE ( C) I D (OFF) I D (ON), I S (ON) 2 Figure 7. Leakage Currents vs. Temperatures, Dual Supply = +5V = 5V 5 3 I S (OFF) 4 ON RESISTANCE (Ω) 2 T A = +25 C TA = +85 C T A = +25 C T A = 4 C V D, (V) Figure 5. On Resistance vs. VD (VS) for Different Temperatures, Dual Supply CURRENT (na) I D (OFF) I D (ON), I S (ON) 3 = 5V = V TEMPERATURE ( C) Figure 8. Leakage Currents vs. Temperature, Single Supply Rev. B Page of 6

12 CHARGE INJECTION (pc) T A = 25 C = +3V = V = +5V = 5V = +5V = V ATTENUATION (db) T A = 25 C = +5V = V = +5V = 5V (V) Figure 9. Charge Injection vs. Source Voltage FREQUENCY (MHz) Figure 2. Crosstalk vs. Frequency T A = 25 C 2 T A = 25 C = +5V = 5V TIME (ns) 2 5 t ON = +5V = 5V t OFF = +5V = V ATTENUATION (db) = +5V = V 5 = +5V V = +5V SS = V = 5V TEMPERATURE ( C) 2 Figure. ton/toff Enable Timing vs. Temperature FREQUENCY (MHz) Figure 3. On Response vs. Frequency T A = 25 C 2 ATTENUATION (db) = +5V = V = +5V = 5V FREQUENCY (MHz) Figure. Off Isolation vs. Frequency Rev. B Page 2 of 6

13 TEST CIRCUITS I DS V S D I S (OFF) A S D I D (OFF) A NC S D I D (ON) A R ON = V/I DS V D V D NC = NO CONNECT Figure 4. On Resistance Figure 5. Off Leakage Figure 6. On Leakage A A SA SB A B ADDRESS DRIVE (V IN ) 3V V 5% 5% 9% 9% D t TRANSITION 2.4V EN GND R L 3Ω C L 35pF t TRANSITION Figure 7. Transition Time, ttransition A A SA SB ADDRESS DRIVE (V IN ) 3V V 8% 8% 2.4V EN GND D R L 3Ω C L 35pF t BBM Figure 8. Break-Before-Make Delay, tbbm A A SA SB ENABLE DRIVE (V IN ) 3V V 5% 5% EN GND D R L 3Ω C L 35pF OUTPUT V t ON (EN) 9% 9% t OFF (EN) Enable Delay, ton (EN), toff (EN) Rev. B Page 3 of 6

14 Δ Q INJ = C L Δ R S S D DECODER C L nf V IN SW OFF SW ON SW OFF GND SW ON A A2 EN W OFF IN CHARGE INJECTION = Δ C L Figure 2. Charge Injection SW OFF NETWORK ANALYZER S GND D R L OFF ISOLATION = 2 log Figure 2. Off Isolation NETWORK ANALYZER S GND D R L WITH SWITCH INSERTION LOSS = 2 log WITHOUT SWITCH Figure 22. Bandwidth NETWORK ANALYZER R L S S2 D R L GND CHANNEL-TO-CHANNEL CROSSTALK = 2 log Figure 23. Channel-to-Channel Crosstalk Rev. B Page 4 of 6

15 TERMINOLOGY VDD Most positive supply potential. VSS Most negative power supply in a dual-supply application. In single-supply applications, this should be tied to ground at the device. GND Ground ( V) reference. IDD Positive supply current. ISS Negative supply current. S Source terminal. May be an input or output. D Drain terminal. May be an input or output. RON Ohmic resistance between Terminal D and Terminal S. ΔRON On resistance match between any two channels (that is, RON max RON min). RFLAT(ON) Flatness is defined as the difference between the maximum and minimum values of on resistance as measured over the specified analog signal range. IS (Off) Source leakage current with the switch off. ID (Off) Drain leakage current with the switch off. ID (On), IS (On) Channel leakage current with the switch on. VD, VS Analog voltage on Terminal D and Terminal S. VINL Maximum input voltage for Logic. IINL(IINH) Input current of the digital input. CS (Off) Channel input capacitance for the off condition. CD (Off) Channel output capacitance for the off condition. CD (On), CS (On) On switch capacitance. CIN Digital input capacitance. ton (EN) Delay time between the 5% and 9% points of the digital input and the switch on condition. toff (EN) Delay time between the 5% and 9% points of the digital input and the switch off condition. ttransition Delay time between the 5% and 9% points of the digital input and the switch on condition when switching from one address state to another. tbbm Off time or on time measured between the 8% points of both switches when switching from one address state to another. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Off Isolation A measure of unwanted signal coupling through an off switch. Bandwidth The frequency response of the on switch. Insertion Loss Loss due to the on resistance of the switch. VINH Minimum input voltage for Logic. Rev. B Page 5 of 6

16 OUTLINE DIMENSIONS 5. (.2) 5. (.97) 4.9 (.93) (.77) 4.4 (.73) 4.3 (.69) (.252) BSC PIN.5 (.4). (.39).8 (.3).65 (.25) BSC.5 (.6).5 (.2).3 (.2) COPLANARITY.9 (.7). (.4).2 (.47) MAX.2 (.8).9 (.3) SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-53-AB- CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure Lead Thin Shrink Small Outline Package [TSSOP] (RU-4) Dimensions shown in millimeters and (inches) 8.75 (.29).6 (.23).45 (.8) ORDERING GUIDE Model Temperature Range Package Description Package Option ADG636YRU 4 C to +25 C 4-Lead Thin Shrink Small Outline Package [TSSOP] RU-4 ADG636YRU-REEL 4 C to +25 C 4-Lead Thin Shrink Small Outline Package [TSSOP] RU-4 ADG636YRUZ 4 C to +25 C 4-Lead Thin Shrink Small Outline Package [TSSOP] RU-4 ADG636YRUZ-REEL 4 C to +25 C 4-Lead Thin Shrink Small Outline Package [TSSOP] RU-4 ADG636YRUZ-REEL7 4 C to +25 C 4-Lead Thin Shrink Small Outline Package [TSSOP] RU-4 Z = RoHS Compliant Part. 698-A Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D /9(B) Rev. B Page 6 of 6