2.5 Ω CMOS Low Power Dual 2:1 Mux/Demux USB 1.1 Switch ADG787

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Cuthbert Chase
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2.5 Ω CMOS Low Power ual 2: Mux/emux USB. Switch AG787 FEATURES USB. signal switching compliant 3 db bandwidth 5 MHz Tiny -lead LFCSP, WLCSP, MSOP packages Single-supply.8 V to 5.

1 2.5 Ω CMOS Low Power ual 2: Mux/emux USB. Switch AG787 FEATURES USB. signal switching compliant 3 db bandwidth 5 MHz Tiny -lead LFCSP, WLCSP, MSOP packages Single-supply.8 V to 5.5 V operation Low on resistance 2.5 Ω typ 3.35 max at 85 C Typical power consumption: <. µw APPLICATIONS USB. signal switching circuits Cellular phones PAs MP3 players Battery-powered systems Headphone switching Audio and video signal routing Communications systems FUNCTIONAL BLOCK IAGRAM SA SB IN IN2 S2A S2B AG787 SWITCHES SHOWN FOR A LOGIC INPUT Figure GENERAL ESCRIPTION The AG787 is a low voltage, CMOS device that contains two independently selectable, single-pole, double-throw (SPT) switches. It is designed as a general analog/digital switch and can also be used for routing USB. signals. MASK: FS (2Mbps) This device offers low on resistance of typically 2.5 Ω, making the part an attractive solution for applications that require low distortion through the switch. The AG787 comes in a tiny 3 4 bump,.5 mm 2. mm WLCSP, a tiny -lead LFCSP, and a -lead MSOP. These packages make the AG787 the ideal solution for spaceconstrained applications. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. The AG787 exhibits break-before-make switching action. 2.ns/IV V IN = 3V p-p Figure 2. Eye Pattern; 2 Mbps, V = 4.2 V, PRBS Rev. Information furnished by Analog evices is believed to be accurate and reliable. However, no responsibility is assumed by Analog evices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog evices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA , U.S.A. Tel: Fax: Analog evices, Inc. All rights reserved.

2 TABLE OF CONTENTS Specifications... 3 Absolute Maximum Ratings... 5 Truth Table... 5 ES Caution... 5 Pin Configurations and Function escriptions... 6 Terminology...7 Typical Performance Characteristics...8 Test Circuits... 2 Outline imensions... 4 Ordering Guide... 5 REVISION HISTORY /5 Revision : Initial Version Rev. Page 2 of 6

3 SPECIFICATIONS V = 4.2 V to 5.5 V, GN = V, unless otherwise noted. AG787 Table. Parameter +25 C 4 C to +85 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range to V V On Resistance (RON) 2.5 Ω typ V = 4.2 V, VS = V to V, IS = ma Ω max See Figure 28 On Resistance Match Between Channels ( RON).2 Ω typ V = 4.2 V, VS = 3.5 V, IS = ma. Ω max On Resistance Flatness (RFLAT (ON)).65 Ω typ V = 4.2 V, VS = V to V.8.95 Ω max IS = ma LEAKAGE CURRENTS V = 5.5 V Source Off Leakage IS(OFF) ±.5 na typ VS = V/4.5 V, V = 4.5 V/ V; see Figure 29 Channel On Leakage I, IS(ON) ±.5 na typ VS = V = V or 4.5 V; see Figure 3 IGITAL INPUTS Input High Voltage, VINH 2. V min Input Low Voltage, VINL.8 V max Input Current IINL or IINH.5 µa typ VIN = VINL or VINH ±. µa max CIN, igital Input Capacitance 2.5 pf typ YNAMIC CHARACTERISTICS 2 ton 3 ns typ RL = 5 Ω, CL = 35 pf 9 22 ns max VS = 3 V; See Figure 3 toff 3 ns typ RL = 5 Ω, CL = 35 pf 5 6 ns max VS = 3 V; See Figure 3 Propagation elay Skew, tskew.6 ns typ CL = 5 pf; VS = 3 V.5 ns max Break-Before-Make Time elay (tbbm) ns typ RL = 5 Ω, CL = 35 pf 5 ns min VS = VS2 = 3 V; See Figure 32 Charge Injection 4 pc typ V = V, RS = Ω, CL = nf; See Figure 33 Off Isolation 63 db typ RL = 5 Ω, CL = 5 pf, f = MHz; See Figure 34 Channel-to-Channel Crosstalk db typ SA to S2A/SB to S2B; RL = 5 Ω, CL = 5 pf, f = MHz; see Figure db typ SA to SB/S2A to S2B; RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 36 Total Harmonic istortion (TH + N).3 % RL = 32 Ω, f = 2 Hz to 2 khz, VS = 2 V p-p Insertion Loss.2 db typ RL = 5 Ω, CL = 5 pf; see Figure 35 3 db Bandwidth 45 MHz typ RL = 5 Ω, CL = 5 pf; see Figure 35 CS (OFF) 6 pf typ C, CS (ON) 4 pf typ POWER REQUIREMENTS V = 5.5 V I.5 µa typ igital inputs = V or 5.5 V µa max Temperature range for B version: 4 C to +85 C. 2 Guaranteed by design, not subject to production test. Rev. Page 3 of 6

4 V = 2.7 V to 3.6 V, GN = V, unless otherwise noted. Table 2. Parameter +25 C 4 C to +85 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V On Resistance (RON) 4 Ω typ V = 2.7 V, VS = V to V Ω max IS = ma; see Figure 28 On Resistance Match Between Channels ( RON).7 Ω typ V = 2.7 V, VS =.5 V.3.35 Ω max IS = ma On Resistance Flatness (RFLAT (ON)).6 Ω typ V = 2.7 V, VS = V to V Ω max IS = ma LEAKAGE CURRENTS V = 3.6 V Source Off Leakage IS(OFF) ±. na typ VS =.6 V/3.3 V, V = 3.3 V/.6 V; see Figure 29 Channel On Leakage I, IS(ON) ±. na typ VS = V =.6 V or 3.3 V; see Figure 3 IGITAL INPUTS Input High Voltage, VINH.3 V min Input Low Voltage, VINL.8 V max Input Current IINL or IINH.5 µa typ VIN = VINL or VINH ±. µa max CIN, igital Input Capacitance 2 pf typ YNAMIC CHARACTERISTICS 2 ton 8 ns typ RL = 5 Ω, CL = 35 pf 3 35 ns max VS =.5 V; see Figure 3 toff 4 ns typ RL = 5 Ω, CL = 35 pf 6 7 ns max VS =.5 V; see Figure 3 Propagation elay Skew, tskew.4 ns typ CL = 5 pf; VS =.5 V.2 ns max Break-Before-Make Time elay (tbbm) 5 ns typ RL = 5 Ω, CL = 35 pf 5 ns min VS = VS2 =.5 V; see Figure 32 Charge Injection pc typ V =.25 V, RS = Ω, CL = nf; see Figure 33 Off Isolation 63 db typ RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 34 Channel-to-Channel Crosstalk db typ SA to S2A/SB to S2B; RL = 5 Ω, CL = 5 pf, f = MHz; see Figure db typ SA to SB/S2A to S2B; RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 35 Total Harmonic istortion (TH + N).7 % RL = 32 Ω, f = 2 Hz to 2 khz, VS =.5 V p-p Insertion Loss.24 db typ RL = 5 Ω, CL = 5 pf; see Figure 35 3 db Bandwidth 45 MHz typ RL = 5 Ω, CL = 5 pf; see Figure 35 CS (OFF) 6 pf typ C, CS (ON) 4 pf typ POWER REQUIREMENTS V = 3.6 V I.5 µa typ igital Inputs = V or 3.6 V µa max Temperature range for B version: 4 C to +85 C. 2 Guaranteed by design, not subject to production test. Rev. Page 4 of 6

5 ABSOLUTE MAXIMUM RATINGS TA = 25 C, unless otherwise noted. Table 3. Parameter Rating V to GN.3 V to +6 V Analog Inputs.3 V to V +.3 V igital Inputs.3 V to +6 V or ma, whichever occurs first Peak Current, S or 5 V Operation 3 ma 3.3 V Operation 2 ma (pulsed at ms, % duty cycle max) Continuous Current, S or 5 V Operation ma 3.3 V Operation 8 ma Operating Temperature Range Industrial (B Version) 4 C to +85 C Storage Temperature Range 65 C to +5 C Junction Temperature 5 C WLCSP Package (4-Layer Board) θja Thermal Impedance 2 C/W LFCSP Package (4-Layer Board) θja Thermal Impedance 6 C/W MSOP Package (4-Layer Board) θja Thermal Impedance 42 C/W θjc Thermal Impedance 43.7 C/W Lead-Free Temperature Soldering IR Reflow, Peak Temperature 26 C ± 5 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. TRUTH TABLE Table 4. Logic (IN/IN2) Switch A/2A Switch B/2B Off On On Off Overvoltages at IN, S, or are clamped by internal diodes. Current should be limited to the maximum ratings given. ES CAUTION ES (electrostatic discharge) sensitive device. Electrostatic charges as high as 4 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ES protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ES precautions are recommended to avoid performance degradation or loss of functionality. Rev. Page 5 of 6

6 PIN CONFIGURATIONS AN FUNCTION ESCRIPTIONS S2A a b c SA 2 3 IN 4 SB 5 AG787 TOP VIEW (Not to Scale) IN2 S2B GN SB IN GN S2B IN2 2 Figure 3. -Lead LFCSP (CP-)/MSOP (RM-) 4 SA S2A Figure 4. -Ball WLCSP (CB-) Top View (Bumps at the Bottom) Table 5. -Lead LFCSP/MSOP Pin Function escriptions Pin No. Mnemonic escription V Most Positive Power Supply Potential. 2 SA Source Terminal. May be an 3 rain Terminal. May be an 4 IN Logic Control Input. 5 SB Source Terminal. May be an 6 GN Ground ( V) Reference. 7 S2B Source Terminal. May be an 8 IN2 Logic Control Input. 9 2 rain Terminal. May be an S2A Source Terminal. May be an Table 6. -Lead WLCSP Pin Function escriptions Ball Mnemonic escription Location a SB Source Terminal. May be an b GN Ground ( V) Reference. c S2B Source Terminal. May be an 2a IN Source Terminal. May be an 2c IN2 Logic Control Input. 3a rain Terminal. May be an 3c 2 rain Terminal. May be an 4a SA Logic Control Input. 4b V Most Positive Power Supply Potential. 4c S2A Source Terminal. May be an Rev. Page 6 of 6

7 TERMINOLOGY I Positive supply current. V (VS) Analog voltage on terminals and S. RON Ohmic resistance between and S. RFLAT (ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured ΔRON On resistance match between any two channels. IS (OFF) Source leakage current with the switch off. I (OFF) rain leakage current with the switch off. I, IS (ON) Channel leakage current with the switch on. VINL Maximum input voltage for Logic. VINH Minimum input voltage for Logic. IINL (IINH) Input current of the digital input. CS (OFF) Off switch source capacitance. Measured with reference to ground. C (OFF) Off switch drain capacitance. Measured with reference to ground. C, CS (ON) On switch capacitance. Measured with reference to ground. CIN igital input capacitance. ton elay time between the 5% and the 9% points of the digital input and switch on condition. tbbm On or off time measured between the 8% points of both switches when switching from one to another. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during on-off switching. Off Isolation A measure of unwanted signal coupling through an off switch. Crosstalk A measure of unwanted signal that is coupled from one channel to another as a result of parasitic capacitance. 3 db Bandwidth The frequency at which the output is attenuated by 3 db. On Response The frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. TH + N The ratio of the harmonic amplitudes plus noise of a signal, to the fundamental. TSKEW The measure of the variation in propagation delay between each channel. Rise Time elay The rise time of a signal is a measure of the time for the signal to rise from % of the ON level to 9% of the ON level. Rise time delay is the difference between the rise time, measured at the input, and the rise time, measured at the output. Fall Time elay The fall time of a signal is a measure of the time for the signal to fall from 9% of the ON level to % of the ON level. Fall time delay is the difference between the fall time, measured at the input, and the fall time, measured at the output. Rise-Time-to-Fall-Time Mismatch This is the absolute value between the variation in the fall time and the rise time, measured at the output. toff elay time between the 5% and the 9% points of the digital input and switch off condition. Rev. Page 7 of 6

8 TYPICAL PERFORMANCE CHARACTERISTICS ON RESISTANCE (Ω) = 4.5V = 4.2V = 5V = 5.5V I S = ma ON RESISTANCE (Ω) T A = +85 C T A = +25 C T A = 4 C = 4.2V I S = ma SIGNAL RANGE SIGNAL RANGE Figure 5. On Resistance vs. V (VS), V = 4.2 V to 5.5 V Figure 8. On Resistance vs. V (VS) for ifferent Temperatures, V = 4.2 V ON RESISTANCE (Ω) I S = ma = 3.3V = 3V = 2.7V = 3.6V ON RESISTANCE (Ω) T A = +25 C T A = +85 C T A = 4 C = 3V I S = ma SIGNAL RANGE Figure 6. On Resistance vs. V (VS), V = 2.7 V to 3.6 V SIGNAL RANGE Figure 9. On Resistance vs. V (VS) for ifferent Temperatures, V = 3 V ON RESISTANCE (Ω) T A = +85 C T A = +25 C T A = 4 C = 5V I S = ma CURRENT (na) I S, I (ON) I S (OFF) SIGNAL RANGE Figure 7. On Resistance vs. V (VS) for ifferent Temperatures, V = 5 V TEMPERATURE ( C) Figure. Leakage Current vs. Temperatures, V = 5.5 V Rev. Page 8 of 6

9 CURRENT (na)..5.5 I S (OFF) I S, I (ON) TIME (ns) 2 5 = 3V T ON = 5V TEMPERATURE ( C) T OFF = 3V 5 = 5V TEMPERATURE ( C) Figure. Leakage Current vs. Temperature, V = 3.3 V Figure 4. ton/toff Times vs. Temperature 2. LOGIC THRESHOL POINT (V) V IN RISING V IN FALLING ATTENUATION (db) = 3V/4.2V/5V SUPPLY VOLTAGE (V) k k k M M M G FREQUENCY (Hz) Figure 2. Threshold Voltage vs. Supply Figure 5. Bandwidth 25 = 5V = 3V/4.2V/5V 2 2 Q-INJ (pc) 5 = 3V ATTENUATION (db) V (V) Figure 3. Charge Injection vs. Source Voltage k k k M M M G FREQUENCY (Hz) Figure 6. Off Isolation vs. Frequency Rev. Page 9 of 6

10 2 = 3V/4.2V/5V INPUT RISE/FALL TIME = 5ns ATTENUATION (db) SA SB SA S2A ELAY (ns) RISE ELAY.5 2 k k k M M M G FREQUENCY (Hz) Figure 7. Crosstalk vs. Frequency FALL ELAY SUPPLY VOLTAGE (V) Figure 2. Rise/Fall Time elay vs. Supply Voltage = 3V/4.2V/5V NO SUPPLY ECOUPLING INPUT RISE/FALL TIME = 5ns = 4.2V PSRR (db) k k k M M M G FREQUENCY (Hz) Figure 8. AC Power Supply Rejection Ratio (PSRR) ELAY (ns).4.2. RISE ELAY.8.6 FALL ELAY TEMPERATURE ( C) Figure 2. Rise/Fall Time elay vs. Temperature INPUT RISE/FALL TIME = 5ns.8.7 = 3V, = 2V p-p.5 TH+N (%) = 5V, = 2V p-p MISMATCH (ns)..5. k k k FREQUENCY (Hz) Figure 9. Total Harmonic istortion + Noise SUPPLY (V) Figure 22. Rise-Time-to-Fall-Time Mismatch vs. Supply Voltage Rev. Page of 6

.2. INPUT RISE/FALL TIME = 5ns = 4.2V MASK: FS (2Mbps) MISMATCH (ns).8.6.4.2 4 5 35 6 85 TEMPERATURE ( C) Figure 23. Rise-Time-to-Fall-Time Mismatch vs. Temperature 525-47 2.ns/IV 2.

11 .2. INPUT RISE/FALL TIME = 5ns = 4.2V MASK: FS (2Mbps) MISMATCH (ns) TEMPERATURE ( C) Figure 23. Rise-Time-to-Fall-Time Mismatch vs. Temperature ns/IV 2.5GS/s 4ps/pt Figure 26. Eye Pattern, 2 Mbps, V = 4.2 V, TA = 85 C, PRBS INPUT RISE/FALL TIME = 5ns MASK: FS (2Mbps) T PROP SKEW (ps) SUPPLY (V) Figure 24. Propagation elay Skew (tskew) vs. Supply Voltage ns/IV 2.5GS/s 4ps/pt Figure 27. Eye Pattern, 2 Mbps, V = 4.2 V, TA = 4 C, PRBS INPUT RISE/FALL TIME = 5ns = 4.2V T SKEW (ps) TEMPERATURE ( C) Figure 25. Propagation elay Skew (tskew) vs. Temperature Rev. Page of 6

12 TEST CIRCUITS S I S V I S (OFF) A S Figure 29. Off Leakage I (OFF) A V NC I (ON) S A Figure 3. On Leakage V R ON = V/I S Figure 28. On Resistance µF SB SA V IN 5% 5% IN R L 5Ω C L 35pF 9% 9% GN t ON t OFF Figure 3. Switching Times, ton, toff.µf V IN V 5% 5% SB SA 8% 8% IN R L 5Ω C L 35pF t BBM t BBM GN Figure 32. Break-Before-Make Time elay, tbbm SW ON SW OFF SB SA NC V IN IN nf GN Q INJ = CL Figure 33. Charge Injection Rev. Page 2 of 6

13 .µf.µf NETWORK ANALYZER NETWORK ANALYZER NC SB SA 5Ω 5Ω SB SA 5Ω GN R L 5Ω GN R L 5Ω OFF ISOLATION = 2 LOG VS Figure 34. Off Isolation WITH SWITCH INSERTION LOSS = 2 LOG WITHOUT SWITCH Figure 36. Bandwidth.µF NETWORK ANALYZER R L 5Ω 5Ω SA SB R L 5Ω 5Ω 5Ω S2A S2B SA SB 2 NC NC 5Ω GN CHANNEL-TO-CHANNEL CROSSTALK = 2 LOG VS CHANNEL-TO-CHANNEL CROSSTALK = 2 LOG VS Figure 37. Channel-to-Channel Crosstalk (SA to S2A) Figure 35. Channel-to-Channel Crosstalk (SA to SB) Rev. Page 3 of 6

14 OUTLINE IMENSIONS INEX AREA 3. BSC SQ PIN INICATOR.5 BCS SQ TOP VIEW.5 BSC EXPOSE PA (BOTTOM VIEW) SIE VIEW.8 MAX.55 TYP MAX.2 NOM SEATING PLANE REF Figure 38. -Lead Lead Frame Chip Scale Package [W_LFCSP] 3 mm 3 mm Body, Very, Very Thin, ual Lead (CP--9) imensions shown in millimeters 3. BSC 3. BSC BSC 5 PIN.5 BSC COPLANARITY.. MAX SEATING PLANE COMPLIANT TO JEEC STANARS MO-87BA Figure 39. -Lead Mini Small Outline Package [MSOP] (RM-) imensions shown in millimeters SEATING PLANE C B A BUMP IENTIFIER TOP VIEW (BALL SIE OWN) BSC BALL PITCH BOTTOM VIEW Figure 4. -Ball Wafer Level Chip Scale Package [WLCSP] (CB-) imensions shown in millimeters Rev. Page 4 of 6

15 ORERING GUIE Model Temperature Range Package escription Package Option Branding AG787BRMZ 2 4 C to +85 C -Lead Mini Small Outline Package (MSOP) RM- S4 AG787BRMZ-5RL7 2 4 C to +85 C -Lead Mini Small Outline Package (MSOP) RM- S4 AG787BRMZ-REEL 2 4 C to +85 C -Lead Mini Small Outline Package (MSOP) RM- S4 AG787BCBZ-5RL7 2, 3 4 C to +85 C -Ball Wafer Level Chip Scale Package (WLCSP) CB- S4 AG787BCBZ-REEL 2,.3 4 C to +85 C -Ball Wafer Level Chip Scale Package (WLCSP) CB- S4 AG787BCPZ-5RL7 2 4 C to +85 C -Lead Lead Frame Chip Scale Package (W_LFCSP) CP--9 S4 AG787BCPZ-REEL 2 4 C to +85 C -Lead Lead Frame Chip Scale Package (W_LFCSP) CP--9 S4 ue to space constraints, branding on this package is limited to three characters. 2 Z = Pb-free part. 3 Contact sales for availability. Rev. Page 5 of 6

0.5 Ω CMOS, Dual 2:1 MUX/SPDT Audio Switch ADG884

0.5 Ω CMOS, Dual 2:1 MUX/SPDT Audio Switch ADG884 ata Sheet FEATURES.8 V to 5.5 V operation Ultralow on resistance.28 Ω typical at 5 V supply.4 Ω maximum at 5 V supply Excellent audio performance, ultralow distortion. Ω typical.5 Ω maximum RON flatness