Logic Controlled, High-Side Power Switch with Reverse Current Blocking ADP195

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1 Data Sheet Logic Controlled, High-Side Power Switch with Reverse Current Blocking ADP95 FEATURES Ultralow on resistance (RDSON) 5 V 55 V 65 V V Input voltage range:. V to.6 V. A maximum continuous operating current Low enable control logic threshold can be operated from. V to. V Low μa (typical) ground V Low μa (maximum) reverse V Ultralow shutdown current:.7 μa V Reverse current blocking Tiny -ball wafer level chip scale package (WLCSP). mm. mm,.5 mm pitch Tiny 6-lead lead frame chip scale package (LFCSP). mm. mm.55 mm,.65 mm pitch APPLICATIONS Mobile phones Digital cameras and audio devices GPS devices Personal media players Portable and battery-powered equipment EN + TYPICAL APPLICATIONS CIRCUIT VIN GND ON OFF ADP95 REVERSE POLARITY PROTECTION LEVEL SHIFT AND SLEW RATE CONTROL Figure. VOUT LOAD GENERAL DESCRIPTION The ADP95 is a high-side load switch designed for operation between. V to.6 V and protected against reverse current flow from output to input. This load switch provides power domain isolation helping extended power domain isolation. The device contains a low on-resistance, P-channel MOSFET that supports over. A of continuous current and minimizes power loss. The low μa of quiescent current and ultralow shutdown current make the ADP95 ideal for battery-operated portable equipment. The built-in level shifter for enable logic makes the ADP95 compatible with many processors and GPIO controllers. In addition to operating performance, the ADP95 occupies minimal printed circuit board (PCB) space with an area of less than. mm and a height of.6 mm. It is available in an ultrasmall mm mm, -ball,.5 mm pitch WLCSP. A 6-lead mm mm.55 mm,.65 mm pitch LFCSP is also available Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 ADP95 TABLE OF CONTENTS Features... Applications... Typical Applications Circuit... General Description... Revision History... Specifications... Timing Diagram... Absolute Maximum Ratings... Thermal Data... Thermal Resistance... ESD Caution... Data Sheet Pin Configurations and Function Descriptions...5 Typical Performance Characteristics...6 Theory of Operation...9 Applications Information... Ground Current... Enable Feature... Timing... Outline Dimensions... Ordering Guide... REVISION HISTORY / Rev. B to Rev. C Changes to General Description Section... Changes to Table... Updated Outline Dimensions... / Rev. A to Rev. B Added 6-Lead LFCSP...Universal Changes to Features, Applications, and General Description Sections... Added VIN to VOUT Resistance, LFCSP Parameter, Table... Changes to Table and Table... Added Figure ; Renumbered Sequentially... 5 Added Table 5; Renumbered Sequentially... 5 Added Figure 6, Figure 8, and Figure... 6 Changes to Theory of Operation Section... 9 Updated Outline Dimensions... Changes to Ordering Guide... 7/ Rev. to Rev. A Changes to Features and Applications Sections... Changed μa Ground Current to μa Ground Current in General Description Section... Changes to Table and Thermal Resistance Section... Added Thermal Data Section... / Revision : Initial Version Rev. C Page of

3 Data Sheet ADP95 SPECIFICATIONS VIN =.8 V, VEN = VIN, IOUT = ma, TA = 5 C, unless otherwise noted. Table. Parameter Symbol Conditions Min Typ Max Unit INPUT VOLTAGE RANGE VIN TJ = C to +85 C..6 V EN INPUT EN Input Threshold VIH. V VIN <.8 V, TJ = C to +85 C.9. V.8 V VIN.6 V, TJ = C to +85 C.5. EN Input Pull-Down Current IEN VIN =.8 V 5 na VIN Shutdown Current VEN = V, VIN = V, VOUT =.6 V na REVERSE BLOCKING VOUT Current VEN = V, VIN = V, VOUT =.6 V μa Hysteresis VIN VOUT 75 mv CURRENT Ground Current IGND VOUT =, includes VEN pull-down and reverse blocking bias current, VIN =.6 V, TJ = C to +85 C μa VOUT =, includes VEN pull-down and reverse blocking μa bias current, VIN =.8 V Off State Current IOFF VEN = GND (includes reverse blocking bias current), VOUT = V.7 μa VEN = GND, TJ = C to +85 C, VOUT = V 5 μa VIN to VOUT RESISTANCE RDSON WLCSP VIN =.6 V, ILOAD = ma, VEN =.6 V.5 Ω VIN =.5 V, ILOAD = ma, VEN =.5 V.55 Ω VIN =.8 V, ILOAD = ma, VEN =.8 V.65 Ω VIN =.8 V, ILOAD = ma, VEN =.8 V, TJ = C to +85 C.95 Ω VIN =.5 V, ILOAD = ma, VEN =.5 V.75 Ω VIN =. V, ILOAD = ma, VEN =. V. Ω LFCSP VIN =.6 V, ILOAD = ma, VEN =.6 V.7 Ω VIN =.5 V, ILOAD = ma, VEN =.5 V.78 Ω VIN =.8 V, ILOAD = ma, VEN =.8 V.9 Ω VIN =.8 V, ILOAD = ma, VEN =.8 V, TJ = C to +85 C. Ω VIN =.5 V, ILOAD = ma, VEN =.5 V.97 Ω VIN =. V, ILOAD = ma, VEN =. V.5 Ω VOUT TURN-ON DELAY TIME Turn-On Delay Time ton_dly VIN =.8 V, ILOAD = ma, VEN =.8 V, CLOAD = μf 5 μs VIN =.6 V, ILOAD = ma, VEN =.6 V, CLOAD = μf.5 μs TIMING DIAGRAM TURN-ON DELAY TURN-OFF DELAY 9% % TURN-ON RISE Figure. Timing Diagram TURN-OFF FALL Rev. C Page of

4 ADP95 ABSOLUTE MAXIMUM RATINGS Table. Parameter VIN, VIN, VIN to GND VOUT, VOUT, VOUT to GND EN to GND Continuous Drain Current TA = 5 C TA = 85 C Continuous Diode Current Storage Temperature Range Operating Junction Temperature Range Operating Ambient Temperature Range Soldering Conditions Rating. V to +. V. V to +. V. V to +. V ± A ±. A 5 ma 65 C to +5 C C to +5 C C to +85 C JEDEC J-STD- Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL DATA Absolute maximum ratings apply individually only, not in combination. The ADP95 can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that TJ is within the specified temperature limits. In applications with high power dissipation and poor PCB thermal resistance, the maximum ambient temperature may need to be derated. In applications with moderate power dissipation and low PCB thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. The junction temperature (TJ) of the device is dependent on the ambient temperature (TA), the power dissipation of the device (PD), and the junction-to-ambient thermal resistance of the package (θja). Maximum junction temperature (TJ) is calculated from the ambient temperature (TA) and power dissipation (PD) using the formula TJ = TA + (PD θja) Data Sheet Junction-to-ambient thermal resistance (θja) of the package is based on modeling and calculation using a -layer board. The junction-to-ambient thermal resistance is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, close attention to thermal board design is required. The value of θja may vary, depending on PCB material, layout, and environmental conditions. The specified values of θja are based on a -layer, inch inch PCB. See JESD5-7 and JESD5-9 for detailed information regarding board construction. For additional information, see the AN-67 application note, MicroCSP TM Wafer Level Chip Scale Package. ΨJB is the junction-to-board thermal characterization parameter with units of C/W. ΨJB of the package is based on modeling and calculation using a -layer board. The JESD5- document, Guidelines for Reporting and Using Electronic Package Thermal Information, states that thermal characterization parameters are not the same as thermal resistances. ΨJB measures the component power flowing through multiple thermal paths rather than through a single path, as in thermal resistance (θjb). Therefore, ΨJB thermal paths include convection from the top of the package as well as radiation from the package, factors that make ΨJB more useful in real-world applications. Maximum junction temperature (TJ) is calculated from the board temperature (TB) and the power dissipation (PD) using the formula TJ = TB + (PD ΨJB) See JESD5-8, JESD5-9, and JESD5- for more detailed information about ΨJB. THERMAL RESISTANCE θja and ΨJB are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table. Thermal Resistance Package Type θja ΨJB Unit -Ball,.5 mm Pitch WLCSP C/W 6-Lead, mm mm LFCSP 7.. C/W ESD CAUTION Rev. C Page of

5 Data Sheet ADP95 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS A B VIN EN VOUT TOP VIEW (Not to Scale) GND Figure. -Ball WLCSP Pin Configuration VOUT VOUT GND ADP95 TOP VIEW (Not to Scale) 6 VIN 5 VIN EN NOTES. THE EXPOSED PAD MUST BE CONNECTED TO GND. Figure. 6-Lead LFCSP Pin Configuration Table. WLCSP Pin Function Descriptions Pin No. Mnemonic Description A VIN Input Voltage. A VOUT Output Voltage. B EN Enable Input. Drive EN high to turn on the switch and drive EN low to turn off the switch. B GND Ground. Table 5. LFCSP Pin Function Descriptions Pin No. Mnemonic Description VOUT Output Voltage. Connect VOUT and VOUT together. VOUT Output Voltage. Connect VOUT and VOUT together. GND Ground. EN Enable Input. Drive EN high to turn on the switch and drive EN low to turn off the switch. 5 VIN Input Voltage. Connect VIN and VIN together. 6 VIN Input Voltage. Connect VIN and VIN together. EP EP The exposed pad must be connected to ground. Rev. C Page 5 of

6 ADP95 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VIN =.8 V, VEN = VIN, CIN = COUT = μf, TA = 5 C, unless otherwise noted... I OUT = ma I OUT = ma I OUT = ma I OUT = 5mA I OUT = ma.6.. RDS ON (Ω) RDS ON (Ω) I OUT = ma I OUT = 5mA I OUT = ma I OUT = ma I OUT = 5mA I OUT = ma Figure 5. RDSON vs. Temperature, WLCSP V IN (V) Figure 8. RDSON vs. Input Voltage (VIN), LFCSP RDS ON (Ω) I OUT = ma I OUT = 5mA I OUT = ma I OUT = ma I OUT = 5mA I OUT = ma VOLTAGE DROP (V) V IN =. V IN =.6 V IN =.8 V IN =. V IN =. V IN =.6 V IN =. V IN =.6. C 5 C 5 C 85 C 5 C Figure 6. RDSON vs. Temperature, LFCSP LOAD (ma) Figure 9. Voltage Drop vs. Load Current, WLCSP RDS ON (Ω) I OUT = ma I OUT = ma I OUT = ma I OUT = 5mA I OUT = ma VOLTAGE DROP (V) V IN =. V IN =.6 V IN =.8 V IN =. V IN =. V IN =.8 V IN =. V IN =. V IN =. V IN = V IN (V) Figure 7. RDSON vs. Input Voltage (VIN), WLCSP LOAD (ma) Figure. Voltage Drop vs. Load Current, LFCSP Rev. C Page 6 of

7 Data Sheet ADP95 LOAD CURRENT LOAD CURRENT CH V B W CH V B W Mµs A CH.V CH A Ω B W T % Figure. Typical Rise Time and Inrush Current, VIN =.6 V, No Load CH V B W CH V B W Mµs A CH.V CH ma Ω B W T % Figure. Typical Rise Time and Inrush Current, VIN =. V, Load = ma I OUT = ma I OUT = ma I OUT = ma I OUT = ma I OUT = 5mA LOAD CURRENT GROUND CURRENT (µa) CH V B W CH V B W Mµs A CH.V CH A Ω B W T % Figure. Typical Rise Time and Inrush Current, VIN =.6 V, Load = ma Figure 5. Ground Current vs. Temperature 6 I OUT = ma I OUT = ma I OUT = ma I OUT = 5mA I OUT = ma GROUND CURRENT (µa) 8 LOAD CURRENT CH V B W CH V B W Mµs A CH.V CH ma Ω B W T % Figure. Typical Rise Time and Inrush Current, VIN =. V, No Load V IN (V) Figure 6. Ground Current vs. Input Voltage (VIN) Rev. C Page 7 of

8 ADP95 Data Sheet SHUTDOWN CURRENT (µa) 5 V IN =.V V IN =.V V IN =.V V IN =.V V IN =.8V V IN =.V V IN =.V V IN =.6V SHUTDOWN CURRENT (µa) V IN =.V V IN =.V V IN =.6V V IN =.8V V IN =.V V IN =.V V IN =.6V V IN =.V V IN =.V V IN =.6V Figure 7. Shutdown Current vs. Temperature Figure 9. Reverse Output Shutdown Current vs. Temperature SHUTDOWN CURRENT (µa) V IN =.V V IN =.V V IN =.V V IN =.V V IN =.8V V IN =.V V IN =.V V IN =.6V SHUTDOWN CURRENT (µa) V IN =.V V IN =.V V IN =.V V IN =.V V IN =.8V V IN =.V V IN =.V V IN =.6V Figure 8. Reverse Input Shutdown Current vs. Temperature Figure. Reverse Shutdown Current vs. Temperature Rev. C Page 8 of

9 Data Sheet THEORY OF OPERATION VIN GND EN ADP95 REVERSE POLARITY PROTECTION LEVEL SHIFT AND SLEW RATE CONTROL Figure. Functional Block Diagram VOUT The ADP95 is a high-side PMOS load switch. It is designed for supply operation between. V to.6 V. The PMOS load switch is designed for low on resistance, 65 mω at VIN =.8 V and supports greater than A of continuous current. It is a low ADP95 quiescent current device with a nominal MΩ pull-down resistor on its enable pin (EN). The reverse current protection circuitry prevents current flow backward through the ADP95 when the output voltage is greater than the input voltage. A comparator senses the difference between the input and output voltages. When the difference between the input voltage and output voltage exceeds 75 mv, the body of the pfet is switched to VOUT and is turned off or opened; that is, the gate is connected to VOUT. The packaging is a space-saving. mm. mm, -ball WLCSP. The ADP95 is also available in a mm mm.55 mm,.65 mm pitch LFCSP. Rev. C Page 9 of

10 ADP95 APPLICATIONS INFORMATION GROUND CURRENT The major source for ground current in the ADP95 is an internal MΩ pull-down on the enable pin. Figure shows the typical ground current when VEN = VIN and varies from. V to.6 V. GROUND CURRENT (µa) LOAD (ma) V IN =.V V IN =.6V V IN =.V V IN =.V Figure. Ground Current vs. Load Current V IN =.8V V IN =.V V IN =.V V IN =.6V As shown in Figure, an increase in quiescent current can occur when VEN VIN. This is caused by the CMOS logic nature of the level shift circuitry as it translates an VEN signal. V to a logic high. This increase is a function of the VIN VEN delta. I GND (µa) (V) V IN =.V V IN =.5V V IN =.8V V IN =.5V V IN =.6V Figure. Typical Ground Current when VEN VIN ENABLE FEATURE Data Sheet The ADP95 uses the EN pin to enable and disable the VOUT pin under normal operating conditions. As shown in Figure, when a rising voltage on VEN crosses the active threshold, VOUT turns on. When a falling voltage on VEN crosses the inactive threshold, VOUT turns off. (V) (V) Figure. Typical EN Operation As shown in Figure, the EN pin has hysteresis built in. This prevents on/off oscillations that can occur due to noise on the EN pin as it passes through the threshold points. The EN pin active/inactive thresholds derive from the VIN voltage; therefore, these thresholds vary with the changing input voltage. Figure 5 shows the typical EN active/inactive thresholds when the input voltage varies from. V to.6 V. TYPICAL EN THRESHOLDS (V) EN ACTIVE EN INACTIVE V IN (V) Figure 5. Typical EN Thresholds vs. Input Voltage (VIN) Rev. C Page of

11 Data Sheet ADP95 TIMING Turn-on delay is defined as the delta between the time that VEN reaches >. V until VOUT rises to ~% of its final value. The ADP95 includes circuitry to have typical 5 μs turn-on delay at.6 V VIN to limit the VIN inrush current. As shown in Figure 6, the turn-on delay is dependent on the input voltage V IN =.V V IN =.8V V IN =.5V V IN =.6V LOAD CURRENT VOLTAGE (V) TIME (µs) Figure 6. Typical Turn-On Delay Time with Varying Input Voltage The rise time is defined as the delta between the time from % to 9% of VOUT reaching its final value. It is dependent on the RC time constant where C = load capacitance (CLOAD) and R = RDSON RLOAD. Because RDSON is usually smaller than RLOAD, an adequate approximation for RC is RDSON CLOAD. An input or load capacitor is not needed for the ADP95; however, capacitors can be used to suppress noise on the board. If significant load capacitance is connected, inrush current is a concern CH V B W CH V Mµs A CH.V CH ma Ω B W T % Figure 8. Typical Rise Time and Inrush Current, CLOAD = μf, VIN =.8 V, Load = ma The turn-off time is defined as the delta between the time from 9% to % of VOUT reaching its final value. It is also dependent on the RC time constant. VOLTAGE (V) AT ma AT ma TIME (µs) Figure 9. Typical Turn-Off Time LOAD CURRENT CH V B W CH V B W Mµs A CH.V CH ma Ω B W T % Figure 7. Typical Rise Time and Inrush Current, CLOAD = μf, VIN =.8 V, No Load Rev. C Page of

12 ADP95 Data Sheet OUTLINE DIMENSIONS SEATING PLANE BALL A IDENTIFIER TOP VIEW (BALL SIDE DOWN) NOM COPLANARITY.5 REF BOTTOM VIEW (BALL SIDE UP) A B 9-A Figure. -Ball Wafer Level Chip Scale Package [WLCSP] (CB--) Dimensions shown in millimeters. BSC SQ BSC 6.75 REF PIN INDEX AREA TOP VIEW EXPOSED PAD BOTTOM VIEW...9 PIN INDICATOR (R.5) SEATING PLANE MAX. NOM. REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Figure. 6-Lead Lead Frame Chip Scale Package [LFCSP_UD]. x. mm Body, Ultra Thin, Dual Lead (CP-6-) Dimensions shown in millimeters 7---B ORDERING GUIDE Model Temperature Range Package Description Package Option Branding ADP95ACBZ-R7 C to +85 C -Ball Wafer Level Chip Scale Package [WLCSP] CB-- 5Y ADP95ACPZ-R7 C to +85 C 6-Lead Lead Frame Chip Scale Package [LFCSP_UD] CP-6- LJ6 ADP95-EVALZ Evaluation Board ADP95-CP-EVALZ Evaluation Board Z = RoHS Compliant Part. Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D8679--/(C) Rev. C Page of

Logic Controlled, High-Side Power Switches ADP190/ADP191

Logic Controlled, High-Side Power Switches FEAURES Low RDSON of 5 mω at.8 V Internal output discharge resistor (ADP9) urn-on slew rate limiting (ADP9) Low input voltage range:. V to 3.6 V 5 ma continuous