Integrated 500 ma Load Switch with Quad Signal Switch ADP1190

Size: px

Start display at page:

Download "Integrated 500 ma Load Switch with Quad Signal Switch ADP1190"

Giles O’Connor’
5 years ago
Views:

1 Data Sheet Integrated 5 ma Load Switch with Quad Signal Switch AD9 FEATURES FUCTIOAL BLOCK DIAGRAM Low input voltage range:.4 V to 3.6 V ower switch: low RDSO of 6 mω at 3.6 V, with active discharge 4 normally open SST signal switches: RDSO of 2 Ω at.8 V with active pull-down on one side 5 ma continuous operating current Built-in level shift for control logic that can be operated by.2 V logic Ultralow shutdown current: <.7 μa Ultrasmall.2 mm.6 mm.5 mm, 2-ball,.4 mm pitch WLCS S S2 S3 T T2 T3 ALICATIOS Mobile phones SIM card disconnect switches Digital cameras and audio devices ortable and battery-powered equipment O OFF S4 E 4MΩ 5ms DEBOUCE T4 GD I OUT LOAD SWITCH 259- Figure. GEERAL DESCRITIO The AD9 is an integrated high-side load switch with four signal switches, designed for operation from.4 V to 3.6 V. This load switch provides power domain isolation for extended power battery life. The load switch is a low on-resistance -channel MOSFET that supports up to 5 ma of continuous load current and minimizes power loss. Integrated with the load switch are four normally open 2 Ω SST signal switches. Aside from its excellent operating performance, the AD9 occupies minimal printed circuit board (CB) space with an area less than.92 mm 2 and a height of.5 mm. The AD9 is available in an ultrasmall.2 mm.6 mm, 2-ball,.4 mm pitch WLCS. Rev. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. o license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way,.O. Box 96, orwood, MA , U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support

2 AD9 TABLE OF COTETS Features... Applications... Functional Block Diagram... General Description... Revision History... 2 Specifications... 3 Timing Diagram... 3 Absolute Maximum Ratings... 4 Thermal Data... 4 Data Sheet Thermal Resistance...4 ESD Caution...4 in Configuration and Function Descriptions...5 Typical erformance Characteristics...6 Theory of Operation...9 Application Block Diagram... Outline Dimensions... Ordering Guide... REVISIO HISTORY 4/3 Revision : Initial Version Rev. age 2 of 2

3 Data Sheet AD9 SECIFICATIOS VI =.8 V, VE = VI, ILOAD = 2 ma, TA = 25 C, unless otherwise noted. Table. arameter Symbol Test Conditions/Comments Min Typ Max Unit IUT VOLTAGE RAGE VI TJ = 4 C to +85 C V E IUT E Input Threshold VE_TH.4 V < VI <.8 V, TJ = 4 C to +85 C (active low).35.2 V.8 V VI 3.6 V, TJ = 4 C to +85 C (active low).45.2 V Logic High Voltage VIH.4 V VI 3.6 V.2 V Logic Low Voltage VIL.4 V VI 3.6 V (chip enable).35 V E Input ull-up Resistance RE 4 MΩ CURRET Ground Current IGD OUT open, TJ = 4 C to +85 C 2 µa Shutdown Current IOFF E = VI or open.7 µa E = VI or open, TJ = 4 C to +85 C 2 µa Analog Switch Off Current IA_OFF Into S, E = VI or open.4 µa LOAD SWITCH VI TO VOUT RESISTACE RDSO SIGAL SWITCH RESISTACE RDSO Maximum value of analog input sweep VI = 3.6 V, ILOAD = 2 ma, E =.5 V 6 mω VI = 2.5 V, ILOAD = 2 ma, E =.5 V 8 mω VI =.8 V, ILOAD = 2 ma, E =.5 V, TJ = 4 C to +85 C 7 mω VI = 3.6 V, ILOAD = ma, E = GD.6 Ω VI = 2.5 V, ILOAD = ma, E = GD Ω VI =.8 V, ILOAD = ma, E = GD 2. Ω RDS Flatness VI = 3.6 V, ILOAD = ma, E = GD.5 Ω VI =.8 V, ILOAD = ma, E = GD Ω OUTUT DISCHARGE RESISTACE RDIS On load switch output and each analog switch output, 25 Ω T, T2, T3, and T4 3 db BADWIDTH BW3dB VI = 3.6 V, RLOAD = 5 Ω, CLOAD = 5 pf, see Figure 23 5 MHz VOUT TIME Turn-On Delay Time to_dly ILOAD = 2 ma, E = GD, CLOAD =. μf 5 ms Turn-Off Delay Time toff_dly VI = 3.6 V, ILOAD = 2 ma, E =.5 V, CLOAD =. μf 4 μs Ground current includes E pull-down current. TIMIG DIAGRAM TUR-O DELAY TUR-OFF DELAY 9% % TUR-O TIME TUR-OFF TIME Figure 2. Timing Diagram Rev. age 3 of 2

4 AD9 ABSOLUTE MAXIMUM RATIGS Table 2. arameter I to GD OUT to GD Sx to GD Tx to GD E to GD Continuous Load Switch Current TA = 25 C TA = 85 C Continuous Diode Current Storage Temperature Range Junction Temperature Operating Junction Temperature Range Operating Ambient Temperature Range Soldering Conditions Rating.3 V to +4. V.3 V to VI.3 V to +4. V.3 V to +4. V.3 V to +4. V ± A ±5 ma 5 ma 65 C to +5 C +5 C 4 C to +25 C 4 C to +85 C JEDEC J-STD-2 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL DATA Absolute maximum ratings apply individually only, not in combination. The AD9 can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that TJ is within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may need to be derated. In applications with moderate power dissipation and low CB thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. The junction temperature (TJ) of the device is dependent on the ambient temperature (TA), the power dissipation of the device (D), and the junction-to-ambient thermal resistance of the package (θja). Maximum junction temperature (TJ) is calculated from the ambient temperature (TA) and power dissipation (D) using the formula TJ = TA + (D θja) Data Sheet The junction-to-ambient thermal resistance (θja) of the package is based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, close attention to thermal board design is required. The value of θja may vary, depending on CB material, layout, and environmental conditions. The specified value of θja is based on a 4-layer, 4 in. 3 in. circuit board. See JESD5-7 and JESD5-9 for detailed information on the board construction. For additional information, see the A-67 Application ote, Wafer Level Chip Scale ackage, available at ΨJB is the junction-to-board thermal characterization parameter with units of C/W. ΨJB of the package is based on modeling and calculation using a 4-layer board. JESD5-2, Guidelines for Reporting and Using Electronic ackage Thermal Information, states that thermal characterization parameters are not the same as thermal resistances. ΨJB measures the component power flowing through multiple thermal paths rather than through a single path as in thermal resistance, θjb. Therefore, ΨJB thermal paths include convection from the top of the package as well as radiation from the package, factors that make ΨJB more useful in real-world applications. Maximum junction temperature (TJ) is calculated from the board temperature (TB) and power dissipation (D) using the formula TJ = TB + (D ΨJB) See JESD5-8 and JESD5-2 for more detailed information about ΨJB. THERMAL RESISTACE θja and ΨJB are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance ackage Type θja ΨJB Unit 2-Ball WLCS C/W ESD CAUTIO Rev. age 4 of 2

5 Data Sheet AD9 I COFIGURATIO AD FUCTIO DESCRITIOS AD9 2 3 A B C D GD T S E T2 S2 I T3 S3 OUT T4 S4 TO VIEW (BALL SIDE DOW) ot to Scale Figure 3. in Configuration Table 4. in Function Descriptions in o. Mnemonic Description A GD Ground. B E Enable Input, Active Low. C I Input Voltage. D OUT Load Switch Output Voltage. A2 T Channel Analog Switch. Connect to the SIM card socket (has active discharge). B2 T2 Channel 2 Analog Switch. Connect to the SIM card socket (has active discharge). C2 T3 Channel 3 Analog Switch. Connect to the SIM card socket (has active discharge). D2 T4 Channel 4 Analog Switch. Connect to the SIM card socket (has active discharge). A3 S Channel Analog Switch. Connect to the microcontroller. B3 S2 Channel 2 Analog Switch. Connect to the microcontroller. C3 S3 Channel 3 Analog Switch. Connect to the microcontroller. D3 S4 Channel 4 Analog Switch. Connect to the microcontroller. Rev. age 5 of 2

6 AD9 Data Sheet TYICAL ERFORMACE CHARACTERISTICS VI =.8 V, VE = VI, CI = COUT = µf, TA = 25 C, unless otherwise noted. RDS O (Ω) mA ma 5mA ma 25mA 5mA VOLTAGE DRO (V) V.5V.6V.8V 2.V 2.4V 2.8V 3.V 3.3V 3.6V V I (V) Figure 4. Load Switch RDSO vs. Input Voltage (VI), Different Load Currents I LOAD (ma) Figure 7. Load Switch Voltage Drop vs. Load Current, Different Input Voltages RDS O (Ω) TEMERATURE ( C) ma 5mA ma 25mA 5mA Figure 5. Load Switch RDSO vs. Temperature, Different Load Currents, VI =.8 V RDS O (Ω) TEMERATURE ( C) ma 5mA ma 25mA 5mA Figure 6. Load Switch RDSO vs. Temperature, Different Load Currents, VI = 3.6 V GROUD CURRET (µa) GROUD CURRET (µa) V I (V) Figure 8. Ground Current vs. Input Voltage, Different Load Currents mA ma 5mA ma 25mA 5mA TEMERATURE ( C) ma 5mA ma 25mA 5mA Figure 9. Ground Current vs. Temperature, Different Load Currents, VI =.8 V Rev. age 6 of 2

7 Data Sheet AD9 GROUD CURRET (µa) TEMERATURE ( C) ma 5mA ma 25mA 5mA 259- RDS O (Ω) AALOG SWITCH VOLTAGE (V) 3.6V 2.2V.8V.6V.4V Figure. Ground Current vs. Temperature, Different Load Currents, VI = 3.6 V Figure 3. Signal Switch RDSO vs. Analog Switch Voltage SHUTDOW CURRET (µa) v.6v.8v 2.4V 2.8V 3.3V 3.6V RDS O (Ω) C 5 C +25 C +55 C +85 C TEMERATURE ( C) Figure. Shutdown Current vs. Temperature, Different Input Voltages AALOG SWITCH VOLTAGE (V) Figure 4. Signal Switch RDSO vs. Analog Switch Voltage and Temperature, VI =.4 V C 5 C +25 C +55 C +85 C C 5 C +25 C +55 C +85 C GROUD CURRET (µa) RDS O (Ω) V I (V) Figure 2. o Load Ground Current vs. Input Voltage and Temperature AALOG SWITCH VOLTAGE (V) Figure 5. Signal Switch RDSO vs. Analog Switch Voltage and Temperature, VI =.8 V Rev. age 7 of 2

8 AD9 Data Sheet C 5 C +25 C +55 C +85 C T EABLE 2. RDS O (Ω) V OUT AALOG SWITCH VOLTAGE (V) Figure 6. Signal Switch RDSO vs. Analog Switch Voltage and Temperature, VI = 3.6 V CH.V B W CH3 2.V B W M2.ms A CH 4.mV T.4% Figure 9. Enable Debounce Behavior, VI =.8 V T T EABLE EABLE 2 T 3 V OUT 3 V OUT CH 2.V B W CH3.V B W CH2.V B W M.ms A CH 88mV T.8% Figure 7. Typical Turn-On Delay Time, VI =.8 V, 5 ma Load CH.V B W CH3 2.V B W M2.ms A CH.8V T.% Figure 2. Enable Debounce Behavior, VI = 3.6 V T EABLE 2 T 3 V OUT CH 2.V B W CH3 2.V B W CH2 2.V B W M.ms A CH2.8V T 65.4% Figure 8. Typical Turn-On Delay Time, VI = 3.6 V, ma Load Rev. age 8 of 2

9 Data Sheet THEORY OF OERATIO The AD9 is a high-side load switch integrated with four signal switches. The load switch and signal switches are turned on by a low signal on the E pin. A 4 MΩ pull-up resistor on this pin allows it to be driven by an open-collector or mechanical switch. When the part is disabled, the T to T4 pins are actively pulled down with a nominal resistance of 25 Ω. There is a 5 ms debounce counter on E for use with a mechanical E switch. That is, E must be held low for 5 ms before the part is enabled. If E transitions high before this timeout, the counter is reset and starts a new 5 ms count. AD9 The signal path is controlled by a MOS/MOS transmission gate with an on resistance of 2 Ω. Break-before-make logic control ensures that the active pull-down is off before the signal path is enabled. In addition to these features, the AD9 occupies minimal printed circuit board (CB) space with an area less than.92 mm 2 and a height of.5 mm. The AD9 is available in an ultrasmall.2 mm.6 mm, 2-ball,.4 mm pitch WLCS. S T S2 T2 S3 T3 S4 T4 O OFF E 4MΩ 5ms DEBOUCE GD I OUT Figure 2. Block Diagram with ESD rotection Devices Rev. age 9 of 2

10 AD9 Data Sheet ALICATIO BLOCK DIAGRAM MICRO- COTROLLER COECTOR SIM CARD S T I/O S2 T2 I/O S3 T3 RST S4 T4 CLK E GD GD 4MΩ I OUT V CC V I =.4V TO 3.6V Figure 22. Typical Application 5Ω V S V OUT 5Ω ETWORK AALYZER Figure 23. Bandwidth Measurement Setup Rev. age of 2

11 Data Sheet AD9 OUTLIE DIMESIOS BOTTOM VIEW (BALL SIDE U) 3 2 BALL A IDETIFIER REF A B C TO VIEW (BALL SIDE DOW) ED VIEW.4 BSC COLAARITY.4.8 REF D Figure Ball Wafer Level Chip Scale ackage [WLCS] (CB-2-) Dimensions shown in millimeters ORDERIG GUIDE Model Temperature Range ackage Description ackage Option Branding AD9ACBZ-R7 4 C to +85 C 2-Ball Wafer Level Chip Scale ackage [WLCS] CB-2- LE Z = RoHS Compliant art. SEATIG LAE A Rev. age of 2

Logic Controlled, High-Side Power Switch with Reverse Current Blocking ADP195

Data Sheet Logic Controlled, High-Side Power Switch with Reverse Current Blocking ADP95 FEATURES Ultralow on resistance (RDSON) 5 mω @.6 V 55 mω @.5 V 65 mω @.8 V mω @. V Input voltage range:. V to.6 V.