Low Power, Adjustable UV and OV Monitor with 400 mv, ±0.275% Reference ADCMP671
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1 Data Sheet Low Power, Adjustable UV and Monitor with mv, ±.7% Reference ADCMP67 FEATURES Window monitoring with minimum processor I/O Individually monitoring N rails with only N + processor I/O mv, ±.7% threshold at VDD =. V, C Supply range:.7 V to. V Low quiescent current: 7 μa maximum at C Input range includes ground Internal hysteresis: 9. mv typical Low input bias current:. na maximum Open-drain outputs Power good indication output Designated over voltage indication output Low profile ( mm), 6-lead TSOT package FUNCTIONAL BLOCK DIAGRAM V DD INH UV mv INL GND Figure. ADCMP67 6- APPLICATIONS Supply voltage monitoring Li-Ion monitoring Portable applications Handheld instruments GENERAL DESCRIPTION The ADCMP67 voltage monitor consists of two low power, high accuracy comparators and reference circuits. It operates on a supply voltage from.7 V to. V and draws 7 μa maximum, making it suitable for low power system monitoring and portable applications. The part is designed to monitor and report supply undervoltage and overvoltage fault. The low input bias current and voltage reference allows resistor adjustable UV and threshold down to mv. The ADCMP67 has two opendrain outputs: the output indicates that the supply is within the UV and window, and the output indicates that the supply is overvoltage. This output combination allows users to window monitor N supplies with an N + processor input/output (I/O). Each output is guaranteed to sink greater than ma over temperature. The ADCMP67 is available in 6-lead TSOT package. The device operates over the C to + C temperature range. THRESHOLD VOLTAGE (mv) INH INL INH INL RISING INPUT FALLING INPUT 9 88 TWO TYPICAL PARTS COMPARATOR A AND COMPARATOR B V DD = V TEMPERATURE ( C) Figure. Comparator Thresholds vs. Temperature 6- Rev. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.
2 ADCMP67 TABLE OF CONTENTS Features... Applications... Functional Block Diagram... General Description... Revision History... Specifications... Absolute Maximum Ratings... 7 Thermal Resistance... 7 ESD Caution... 7 Pin Configuration and Function Descriptions... 8 Data Sheet Typical Performance Characteristics...9 Applications Information... Comparators and Internal Reference... Power Supply... Inputs... Hysteresis... Voltage Monitoring Scheme... Outputs... Outline Dimensions... 6 Ordering Guide... 6 REVISION HISTORY / Revision : Initial Version Rev. Page of 6
3 Data Sheet ADCMP67 SPECIFICATIONS VDD =.7 V to. V, TA = C, unless otherwise noted. Table. Parameter Min Typ Max Unit Test Conditions/Comments THRESHOLDS Rising Input Threshold Voltage (VTH(R)) mv VDD =.7 V mv VDD =. V mv VDD =. V Falling Input Threshold Voltage(VTH(F)) mv VDD =.7 V mv VDD =. V mv VDD =. V Rising Input Threshold Voltage Accuracy ±.7 % VDD =. V Falling Input Threshold Voltage Accuracy ±.7 % VDD =. V Hysteresis = VTH(R) VTH(F) mv INPUT CHARACTERISTICS Input Bias Current. na VDD =.7 V, VIN = VDD. na VDD =.7 V, VIN =. V OPEN-DRAN OUTPUTS Output Low Voltage mv VDD =.7 V, IOUT = ma mv VDD =. V, IOUT = ma Output Leakage Current.. μa VDD =.7 V, VOUT = VDD.. μa VDD =.7 V, VOUT =. V DYNAMIC PERFORMANCE, High-to-Low Propagation Delay μs VDD =. V, VOL = mv Low-to-High Propagation Delay 8 μs VDD =. V, VOH =.9 VDD Output Rise Time. μs VDD =. V, VOUT = (. to.9) VDD Output Fall Time.7 μs VDD =. V, VOUT = (. to.9) VDD POWER SUPPLY Supply Current.7 μa VDD =.7 V 6. μa VDD =. V RL = kω, VOUT = V swing. VIN = mv input overdrive. VIN = mv overdrive. RL = kω. No load current. Rev. Page of 6
4 ADCMP67 Data Sheet VDD =.7 V to. V, C TA 7 C, unless otherwise noted. Table. Parameter Min Typ Max Unit Test Conditions/Comments THRESHOLDS Rising Input Threshold Voltage (VTH(R)) 9.. mv VDD =.7 V 97.. mv VDD =. V mv VDD =. V Falling Input Threshold Voltage (VTH(F)) mv VDD =.7 V mv VDD =. V mv VDD =. V Rising Input Threshold Voltage Accuracy ±.7 % VDD =. V Falling Input Threshold Voltage Accuracy ±. % VDD =. V Hysteresis = VTH(R) VTH(F) 6.8. mv INPUT CHARACTERISTICS Input Bias Current na VDD =.7 V, VIN = VDD na VDD =.7 V, VIN =. V OPEN-DRAIN OUTPUTS Output Low Voltage mv VDD =.7 V, IOUT = ma mv VDD =. V, IOUT = ma Output Leakage Current. μa VDD =.7 V, VOUT = VDD. μa VDD =.7 V, VOUT =. V POWER SUPPLY Supply Current μa VDD =.7 V μa VDD =. V RL = kω, VOUT = V swing. VIN = mv input overdrive. VIN = mv overdrive. No load. Rev. Page of 6
5 Data Sheet ADCMP67 VDD =.7 V to. V, C TA +8 C, unless otherwise noted. Table. Parameter Min Typ Max Unit Test Conditions/Comments THRESHOLDS Rising Input Threshold Voltage (VTH(R)) mv VDD =.7 V 9..9 mv VDD =. V 9.. mv VDD =. V Falling Input Threshold Voltage (VTH(F)) 8..9 mv VDD =.7 V mv VDD =. V mv VDD =. V Rising Input Threshold Voltage Accuracy ±.6 % VDD =. V Falling Input Threshold Voltage Accuracy ±.7 % VDD =. V Hysteresis = VTH(R) VTH(F)..6 mv INPUT CHARACTERISTICS Input Bias Current na VDD =.7 V, VIN = VDD na VDD =.7 V, VIN =. V OPEN-DRAIN OUTPUTS Output Low Voltage mv VDD =.7 V, IOUT = ma mv VDD =. V, IOUT = ma Output Leakage Current. μa VDD =.7 V, VOUT = VDD. μa VDD =.7 V, VOUT =. V POWER SUPPLY Supply Current μa VDD =.7 V μa VDD =. V RL = kω, VOUT = V swing. VIN = mv input overdrive. VIN = mv overdrive. No load. Rev. Page of 6
6 ADCMP67 Data Sheet VDD =.7 V to. V, C TA + C, unless otherwise noted. Table. Parameter Min Typ Max Unit Test Conditions/Comments THRESHOLDS Rising Input Threshold Voltage (VTH(R)) mv VDD =.7 V 9..9 mv VDD =. V 9..8 mv VDD =. V Falling Input Threshold Voltage (VTH(F)) 8..9 mv VDD =.7 V mv VDD =. V mv VDD =. V Rising Input Threshold Voltage Accuracy ±.6 % VDD =. V Falling Input Threshold Voltage Accuracy ±. % VDD =. V Hysteresis = VTH(R) VTH(F).. mv INPUT CHARACTERISTICS Input Bias Current. na VDD =.7 V, VIN = VDD. na VDD =.7 V, VIN =. V OPEN-DRAIN OUTPUTS Output Low Voltage mv VDD =.7 V, IOUT = ma mv VDD =. V, IOUT = ma Output Leakage Current. μa VDD =.7 V, VOUT = VDD. μa VDD =.7 V, VOUT =. V POWER SUPPLY Supply Current 6 μa VDD =.7 V 7 μa VDD =. V RL = kω, VOUT = V swing. VIN = mv input overdrive. VIN = mv overdrive. No load. Rev. Page 6 of 6
7 Data Sheet ABSOLUTE MAXIMUM RATINGS Table. Parameter VDD Rating. V to +6 V. V to +6 V. V to +6 V INH, INL, Output Short-Circuit Duration Input Current Operating Temperature Range Storage Temperature Range Lead Temperature Soldering ( sec) C Vapor Phase (6 sec) C Infrared ( sec) C Indefinite ma C to + C 6 C to + C When the output is shorted indefinitely, the use of a heat sink may be required to keep the junction temperature within the absolute maximum ratings. ADCMP67 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 6. Thermal Resistance Package Type θja Unit 6-Lead TSOT C/W ESD CAUTION Rev. Page 7 of 6
8 ADCMP67 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 6 ADCMP67 GND TOP VIEW V DD (Not to Scale) INH INL Figure. Pin Configuration 6- Table 7. Pin Function Descriptions Pin No. Mnemonic Description Open-Drain Active High Power Good Output. It asserts when the input falls within the UV and window, for example, INH high and INL low. GND Ground. INH Monitors for Supply Undervoltage Fault Through an External Resistor Divider Network. It is internally connected to the noninverting input of a comparator. The other input of the comparator is connected to a mv reference. INL Monitors for Supply Overvoltage Fault Through an External Resistor Divider Network. It is internally connected to the inverting input of a comparator. The other input of the comparator is connected to a mv reference. VDD Power Supply Pin. 6 Open-Drain Output Active Low Overvoltage Fault Indication Output. It asserts when there is an overvoltage fault, for example, INL high. Rev. Page 8 of 6
9 Data Sheet ADCMP67 TYPICAL PERFORMANCE CHARACTERISTICS 6 V DD = V T A = C V DD = V T A = C PERCENT OF UNITS (%) PERCENT OF UNITS (%) RISING INPUT THRESHOLD VOLTAGE (mv) FALLING INPUT THRESHOLD VOLTAGE (mv) 6-7 Figure. Distribution of Rising Input Threshold Voltage Figure 7. Distribution of Falling Input Threshold Voltage PERCENT OF UNITS (%) V DD = V T A = C RISING INPUT THRESHOLD VOLTAGE (mv) 99 V DD =.8V V DD =.V V DD =.V V DD =.V HYSTERESIS (mv) TEMPERATURE ( C) 6-8 Figure. Distribution of Hysteresis Figure 8. Rising Input Threshold Voltage vs. Temperature for Various VDD Voltages RISING INPUT THRESHOLD VOLTAGE (mv) 98 FOUR TYPICAL PARTS V DD = V RISING INPUT THRESHOLD VOLTAGE (mv) T A = C T A = + C T A = + C T A = +8 C TEMPERATURE ( C) SUPPLY VOLTAGE (V) 6-9 Figure 6. Rising Input Threshold Voltage vs. Temperature for Four Typical Parts Figure 9. Rising Input Threshold Voltage vs. Supply Voltage Rev. Page 9 of 6
10 ADCMP67 Data Sheet HYSTERESIS (mv) NH NL INH INL. 6 8 TEMPERATURE ( C) FOUR TYPICAL PARTS V DD = V 6- HYSTERESIS (mv) V DD =.8V V DD =.V V DD =.V V DD =.V. 6 8 TEMPERATURE ( C) 6- Figure. Hysteresis vs. Temperature for Four Typical Parts Figure. Hysteresis vs. Temperature for Various VDD Voltages T A = + C HYSTERESIS (mv) T A = + C T A = +8 C T A = C THRESHOLD SHIFT (mv) T A = C T A = + C T A = +8 C T A = + C SUPPLY VOLTAGE (V) Figure. Hysteresis vs. Supply Voltage SUPPLY VOLTAGE (V) Figure. Minimum Supply Voltage 6- NO LOAD CURRENT 9 SUPPLY CURRENT (µa) 8 T A = +8 C T A = + C 7 T A = + C 6 T A = C SUPPLY VOLTAGE (V). 6- SUPPLY CURRENT (µa) T A = +8 C T A = + C.. T A = + C SUPPLY VOLTAGE (V) T A = C. 6- Figure. Quiescent Supply Current vs. Supply Voltage Figure. Start-Up Supply Current Rev. Page of 6
11 Data Sheet ADCMP67 T A = C V DD =.V V DD =.V V DD =.V V DD =.7V T A = C V DD =.V V DD =.V V DD =.V V DD =.7V SUPPLY CURRENT (µa) SUPPLY CURRENT (µa)... OUTPUT SINK CURRENT (ma) OUTPUT SINK CURRENT (ma) 6-7 Figure 6. Supply Current vs. Output Sink Current for TA = C Figure 9. Supply Current vs. Output Sink Current for TA = C T A = 8 C V DD =.V V DD =.V V DD =.V V DD =.7V k k T A = + C CURRENT IS GOING OUT OF THE DEVICE. V DD = V.V < V IB < V SUPPLY CURRENT (µa) INPUT BIAS CURRENT (na) T A = + C T A = +8 C T A = C... OUTPUT SINK CURRENT (ma) INPUT VOLTAGE (V) 6-9 Figure 7. Supply Current vs. Output Sink Current for TA = 8 C Figure. Below Ground Input Bias Current vs. Input Voltage INPUT BIAS CURRENT (na) CURRENT IS POSITIVE GOING INTO THE DEVICE V DD = V V < V IB < V INPUT VOLTAGE (V) T A = + C T A = +8 C T A = + C T A = C. 6- INPUT BIAS CURRENT (na). T A = + C T A = + C T A = +8 C T A = C CURRENT IS GOING INTO THE DEVICE V DD = V V IB > V. INPUT VOLTAGE (V) 6- Figure 8. Low Level Input Bias Current vs. Input Voltage Figure. High Level Input Bias Current vs. Input Voltage Rev. Page of 6
12 ADCMP67 Data Sheet OUTPUT SATURATION VOLTAGE (mv) T A = C V DD =.V V DD =.V V DD =.V V DD =.8V OUTPUT SATURATION VOLTAGE (mv) T A = C V DD =.V V DD =.V V DD =.V V DD =.8V... OUTPUT SINK CURRENT (ma) OUTPUT SINK CURRENT (ma) 6- Figure. Output Saturation Voltage vs. Output Sink Current for TA = C Figure. Output Saturation Voltage vs. Output Sink Current for TA = C OUTPUT SATURATION VOLTAGE (mv) T A = 8 C V DD =.V V DD =.V V DD =.V V DD =.8V SHORT-CIRCUIT CURRENT (ma) V DD = V T A = + C T A = C T A = +8 C T A = + C... OUTPUT SINK CURRENT (ma) Figure. Output Saturation Voltage vs. Output Sink Current for TA = 8 C 6- OUTPUT VOLTAGE (V) Figure 6. Output Short-Circuit Current vs. Output Voltage 6-7 T A = C V DD =.V V DD = V SHORT-CIRCUIT CURRENT (ma) 6 V DD =.V V DD =.V V DD =.8V OUTPUT LEAKAGE CURRENT (na).. T A = + C T A = +8 C T A = + C T A = C OUTPUT VOLTAGE (V) 6-6. OUTPUT VOLTAGE (V) 6-7 Figure. Output Short-Circuit Current vs. Output Voltage Figure 7. Output Leakage Current vs. Output Voltage Rev. Page of 6
13 Data Sheet ADCMP67 PROPAGATION DELAY (µs) 7 6 T A = C 6 INH LH INL LH INH HL INL HL 8 INPUT ERDRIVE (mv) Figure 8. Propagation Delay vs. Input Overdrive 6-8 V OUT (V) OUTPUTS BEING PULLED UP TO VDD WITH kω INH = LOW INL = LOW V DD (V) Figure. Output Voltage vs. Supply Voltage with Both INH and INL Low 6- INL VTH(R) INH VTH(R) INL VTH(F) OUTPUTS BEING PULLED UP TO V DD WITH kω INH = HIGH INL = LOW INH VTH(F) V IN V OUT (V) R _PULLUP = kω V _PULLUP = V CH.V CH.V M.µs Figure 9. Propagation Delay 6-9 V DD (V) Figure. Output Voltage vs. Supply Voltage with INH High and INL Low 6- RISE AND FALL TIMES (µs). V DD = V C L = pf T A = C RISE FALL.. OUTPUT PULL-UP RESISTOR (kω) Figure. Rise and Fall Times vs. Output Pull-Up Resistor 6- V OUT (V) OUTPUTS BEING PULLED UP TO V DD WITH kω INH = HIGH INL = HIGH V DD (V) Figure. Output Voltage vs. Supply Voltage with Both INH and INL High 6- Rev. Page of 6
14 ADCMP67 APPLICATIONS INFORMATION The ADCMP67 is a UV and monitor with a built-in mv reference that operates from.7 V to. V. The comparator is.7% accurate with a built-in hysteresis of 9. mv. The outputs are open-drain, capable of sinking ma. COMPARATORS AND INTERNAL REFERENCE There are two comparators inside the ADCMP67. The comparator with its noninverting input connected to the INH pin (and its inverting input connected internally to the mv reference) is for undervoltage detection, and the comparator with its inverting input available through the INL pin (and its noninverting input connected internally to the mv reference) is for overvoltage detection. The rising input threshold voltage of the comparators is designed to be equal to that of the reference. POWER SUPPLY The ADCMP67 is designed to operate from.7 V to. V. A. μf decoupling capacitor is recommended between VDD and GND. INPUTS The comparator inputs are limited to the maximum VDD voltage range. The voltage on these inputs can be more than VDD but never more than the maximum allowed VDD voltage. When adding a resistor string to the input, choose resistor values carefully because the input bias current is in parallel with the bottom resistor of the string. Therefore, choose the bottom resistor first to control the error introduced by the bias current. To minimize the number of external components use three resistor dividers to program the UV and thresholds. HYSTERESIS To prevent oscillations at the output caused by noise or slowly moving signals passing the switching threshold, each comparator has a built-in hysteresis of approximately 8.9 mv. VOLTAGE MONITORING SCHEME When monitoring a supply rail, the desired nominal operating voltage for monitoring is denoted by VM, IM is the nominal current through the resistor divider, V is the overvoltage trip point, and VUV is the undervoltage trip point. Figure illustrates the voltage monitoring input connection. Three external resistors, RX, RY, and RZ, divide the positive voltage for monitoring (VM) into the high-side voltage (VH) and lowside voltage (VL). The high-side voltage is connected to the INH pin, and the low-side voltage is connected to the INL pin. R X R Y R Z V INH INL UV mv V V DD ADCMP67 GND Data Sheet Figure. Undervoltage/Overvoltage Monitoring Configuration To trigger an overvoltage condition, the low-side voltage (in this case, VL) must exceed the. V threshold on the INL pin. The low-side voltage, VL, is given by the following equation: Also, V = V L R X R + R V R X + RY + RZ = I Z Y M M + R Z =. V Therefore, RZ, which sets the desired trip point for the overvoltage monitor, is calculated using the following equation: R Z = (.)( VM ) ( V )( I ) M To trigger the undervoltage condition, the high-side voltage, VH, must fall below the. V threshold on the INH pin. The highside voltage, VH, is given by the following equation: V H = V UV R Y + RZ RX + RY + R Z =. V Because RZ is already known, RY can be expressed as follows: R Y = (.)( VM ) RZ ( V )( I ) UV M When RY and RZ are known, RX is calculated using the following equation: R X = ( VM ) RZ RY ( I ) M If VM, IM, V, or VUV changes each step must be recalculated. 6- Rev. Page of 6
15 Data Sheet ADCMP67 OUTPUTS The output is used to indicate supply power good for the rail being monitored. It asserts if the monitored voltage falls within the UV and threshold window. The output acts as a dedicated overvoltage indication output, allows the board manager to take decisive action to protect the system from overvoltage faults. Both outputs are open-drain and can be pulled up to voltages above VDD. These outputs are capable of sinking current up to ma. In the multisupply monitoring application, multiple ADCMP67 can be used with their pin tied together to generate a single overvoltage fault alert signal, as shown in Figure. During power up and power down, the power management processor of the board can manage supply sequencing based on signals. In the event of supply overvoltage fault, the processor can react quickly to the provide necessary circuit protection because of its dedicated alert. The processor is also able to identify the faulty supply from combining the information on the pins. This allows the processor to use the N + input pins to individually monitor N channels of supplies..v.8v.v.9v ADCMP67 ADCMP67 ADCMP67 ADCMP67.V GOOD.8V GOOD.V GOOD.9V GOOD FAULT BOARD MANAGER Figure. N Rails Monitoring with N + Processor I/O 6- Rev. Page of 6
16 ADCMP67 Data Sheet OUTLINE DIMENSIONS.9 BSC.6 BSC 6.8 BSC PIN INDICATOR.9 BSC.9 BSC * *. MAX..8. MAX.. SEATING PLANE *COMPLIANT TO JEDEC STANDARDS MO-9-AA WITH THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS. Figure 6. 6-Lead Thin Small Outline Transistor Package [TSOT] (UJ-6) Dimensions shown in millimeters 88-A ORDERING GUIDE Model Temperature Range Package Description Package Option Branding ADCMP67-YUJZ-RL7 C to + C 6-Lead Thin Small Outline Transistor Package [TSOT] UJ-6 LLS Z = RoHS Compliant Part. Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D6--/() Rev. Page 6 of 6
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