RT2517B. 1A, 6V, Ultra-Low Dropout Linear Regulator. Features. General Description. Applications. Ordering Information. Marking Information

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1 Sample & Buy 1A, 6V, Ultra-Low Dropout Linear Regulator General Description The is a high performance positive voltage regulator designed for use in applications requiring ultralow input voltage and ultra-low dropout voltage at up to 1A. The feature of ultra-low dropout voltage is ideal for the application where output voltage is very close to input voltage. The input voltage can be as low as 2.2V and the output voltage is adjustable by an external resistive divider. The provides an excellent output voltage regulation over variations in line, load and temperature. Current limit and thermal shutdown protection functions are provided. Additionally, an enable pin is designed to further reduce power consumption while shutdown and the shutdown current is as low as 1.5μA. The is available in the SOP-8 (Exposed Pad) package. Ordering Information Package Type SP : SOP-8 (Exposed Pad-Option 2) Lead Plating System G : Green (Halogen Free and Pb Free) Note : Richtek products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. Features AEC-Q100 Grade2 Certification Input Voltage Range : 2.2V to 6V Range from 1.2V to V DROP Reference Voltage : 1.2V ±2% over 40 C to 105 C Ultra-Low Dropout Voltage : 200mV at 1A over 40 C to 105 C Low Quiescent 1.5μA in Shutdown Mode Soft Discharge Functionality Thermal Shutdown and Current Limit RoHS Compliant and Halogen Free Applications Automotive Audio, Navigation, & Info systems Industrial Grade General Purpose Point of Load Digital Set top Boxes Vehicle Electronics Marking Information GSPYMDNN Pin Configuration IC EN VIN VIN GSP : Product Number YMDNN : Date Code (TOP VIEW) GND GND ADJ VOUT VOUT SOP-8 (Exposed Pad) Simplified Application Circuit C1 VIN VOUT R1 C2 Enable EN GND ADJ R2 1

2 Functional Pin Description Pin No. Pin Name Pin Function 1 IC Internal connection. Leave floating and do not make connection to this pin. 2 EN Chip enable (Active High). This pin will be pulled up by internal circuit if this pin is open. 3,4 VIN Supply voltage input. Connect a minimum 10 F ceramic capacitor at this pin. 5,6 VOUT Output voltage. A minimum 10 F capacitor should be placed directly at this pin. 7 ADJ Feedback voltage input. Connect an external resistor divider to this pin for output voltage setting. If this pin is connected to the VOUT pin, the output voltage will be set at 1.2V. 8, 9 (Exposed pad) GND Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum the power dissipation. Functional Block Diagram VIN R SENSE VOUT V PUMP ADJ EN Thermal Shutdown Reference Generator + GND - Reverse Voltage Shutdown 2

3 Operation The is a linear regulator designed specially for ultra-low dropout voltage. The input voltage range is from 2.2V to 6V. Output Transistor The builds in a MOSFET output transistor which provides a low switch-on resistance for low dropout voltage applications. Error Amplifier The Error Amplifier compares the internal reference voltage with the output feedback voltage from the internal divider, and controls the Gate voltage of MOSFET to support good line regulation and load regulation at output voltage. Reference Generator The provides a reference voltage by internal reference generator circuit. The reference voltage can be used to determine the output voltage. Thermal Shutdown The thermal shutdown function will turn off the MOSFET when the junction temperature exceeds 160 C (typ.). Once the junction temperature cools down by approximately 10 C, the regulator will automatically resume operation. Current Limit The provides current limit function to prevent the device from damages during over-load or short-circuit condition. This current is detected by an internal sensing device 3

4 Absolute Maximum Ratings (Note 1) Supply Voltage, VIN V to 7V Other Pins V to 6V Power Dissipation, P T A = 25 C SOP-8 (Exposed Pad) W Package Thermal Resistance (Note 2) SOP-8 (Exposed Pad), θ JA C/W SOP-8 (Exposed Pad), θ JC C/W Lead Temperature (Soldering, 10 sec.) C Junction Temperature C Storage Temperature Range C to 150 C ESD Susceptibility (Note 3) HBM (Human Body Model) kV Recommended Operating Conditions (Note 4) Supply Input Voltage, VIN V to 6V Junction Temperature Range C to 125 C Electrical Characteristics (VIN = 2.2V to 6V, IOUT = 10μA to 1A, VADJ = VOUT, 40 C TA 105 C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Shutdown Supply Current I SHDN = 3.3V, V EN = 0V A Quiescent Current I Q = 3.3V, I OUT = 0A ma Line Regulation V LINE I OUT = 10mA %/V Load Regulation V LOAD I OUT = 10mA to 1A % Current Limit I LIM = 3.3V A Current Foldback Threshold V Fold = 3.3V V Dropout Voltage V DROP I OUT = 1A, mv ADJ Reference Voltage V ADJ = 3.3V, V ADJ =, I OUT = 10mA V ADJ Pin Current I ADJ = 3.3V na EN Input Voltage Logic-High V IH = 3.3V Logic-Low V IL = 3.3V Enable Pin Current I EN = 6V, V EN = 0V A Thermal Shutdown Temperature T SD C Thermal Shutdown Hysteresis T SD C Note 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θ JA is measured at T A = 25 C on a high effective thermal conductivity four-layer test board per JEDEC θjc is measured at the exposed pad of the package. The PCB copper area with exposed pad is 70mm 2. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. V 4

5 Typical Application Circuit Enable 3, 4 VIN 5, 6 VOUT C1 R1 C2 10µF 10k 10µF ADJ 7 2 EN R2 20k GND 8, 9 (Exposed Pad) 1.8V/1A Figure V Output Voltage Operation Circuit 5

6 Typical Operating Characteristics Reference Voltage vs. Temperature Quiescent Current vs. Temperature Reference Voltage (V) VIN = 5V VIN = 3.3V Quiescent Current (ma) VIN = 5V VIN = 3.3V VOUT = 1.8V Temperature ( C) VOUT = 1.8V Temperature ( C) Shutdown Current vs. Temperature UVLO vs. Temperature Shutdown Current (µa) VIN = 5V VIN = 3.3V UVLO (V) Rising Falling VOUT = 1.8V Temperature ( C) VEN = 5V Temperature ( C) Dropout Voltage vs. I OUT EN Threshold Voltage vs. Temperature Dropout Voltage (mv) C 25 C 40 C EN Threshold Voltage (V) Rising Falling I OUT (A) IOUT = 1A VIN = 5V Temperature ( C) 6

7 Load Transient Response Line Transient Response (10mV/Div) (1V/Div) IOUT (1A/Div) VIN = 3.3V, VOUT = 1.8V, IOUT = 0 to 1A (10mV/Div) VIN = 3.3V to 4.3V, VOUT = 1.8V, IOUT = 1A Time (100μs/Div) Time (500μs/Div) Power On from EN Power Off from EN VEN (2V/Div) VEN (2V/Div) (1V/Div) (1V/Div) IIN (1A/Div) VIN = 2.5V, VOUT = 1.5V, IOUT = 1A IIN (1A/Div) VIN = 2.5V, VOUT = 1.5V, IOUT = 1A Time (100μs/Div) Time (100μs/Div) PSRR vs. Frequency IOUT = 300mA PSRR (db) IOUT = 1mA IOUT = 100mA VIN = 3.25V to 3.35V, VOUT = 1.8V Frequency (Hz) 7

8 Application Information The is a low voltage, low dropout linear regulator with an external bias supply input capable of supporting an input voltage range from 2.2V to 6V and adjustable output voltage from 1.2V to ( V DROP ). Output Voltage Setting The output voltage is adjustable from 2.2V to 6V via the external resistive voltage divider. The output voltage is set according to the following equation : R1 VOUT VADJ 1 R2 For ADJ pin noise immunity, the resistive divider total value of R1 and R2 are suggested not over 100kΩ, where V ADJ is the reference voltage with a typical value of 1.2V. Feed-Forward Capacitor (C FF ) The is designed to be stable without the external feed-forward capacitor (C FF ). However, an external feedforward capacitor between VOUT and ADJ pin is often adopted to optimizes the transient, noise, and PSRR performance. Regarding to the resistance value of the voltage divider, the recommended C FF values are as below : C FF = 1nF, for both R1 and R2 are larger than 1kΩ C FF = 10nF, for both R1 and R2 are smaller than 1kΩ VIN VOUT C IN *C FF COUT R1 EN ADJ GND R2 Figure 2. Application Circuit with C FF Chip Enable Operation The goes into sleep mode when the EN pin is in a logic low condition. In this condition, the pass transistor, error amplifier, and band gap are all turned off, reducing the supply current to only 10μA (max.). The EN pin can be directly tied to VIN to keep the part on. UVLO Protection The provides an input Under Voltage Lockout protection (UVLO). When the input voltage exceeds the UVLO rising threshold voltage (1.2V typ.), the device resets the internal circuit and prepares for operation. If the input voltage falls below the UVLO falling threshold voltage during normal operation, the device will be shut down. A hysteresis (140mV typ.) between the UVLO rising and falling threshold voltage is designed to avoid noise. Current Limit The contains an independent current limit circuitry, which controls the pass transistor's gate voltage, limiting the output current to 1A (typ.). C IN and C OUT Selection Like any low dropout regulator, the external capacitors of the must be carefully selected for regulator stability and performance. Using a capacitor of at least 10μF is suitable. The input capacitor must be located at a distance of not more than 0.5 inch from the input pin of the IC. Any good quality ceramic capacitor can be used. However, a capacitor with larger value and lower ESR (Equivalent Series Resistance) is recommended since it will provide better PSRR and line transient response. The is designed specifically to work with low ESR ceramic output capacitor for space saving and performance consideration. Using a ceramic capacitor with capacitance of at least 10μF on output ensures stability. Thermal Considerations For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The 8

9 maximum power dissipation can be calculated by the following formula : P D(MAX) = (T J(MAX) T A ) / θ JA where T J(MAX) is the maximum junction temperature, T A is the ambient temperature, and θ JA is the junction to ambient thermal resistance. For recommended operating condition specifications, the maximum junction temperature is 125 C. The junction to ambient thermal resistance, θ JA, is layout dependent. For SOP-8 (Exposed Pad) package, the thermal resistance, θ JA, is 49 C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at T A = 25 C can be calculated by the following formula : P D(MAX) = (125 C 25 C) / (49 C/W) = 2.041W for SOP-8 (Exposed Pad) package The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θ JA. The derating curve in Figure 3 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. Maximum Power Dissipation (W) Ambient Temperature ( C) Four-Layer PCB Figure 3. Derating Curve of Maximum Power Dissipation 9

10 Outline Dimension A H M EXPOSED THERMAL PAD (Bottom of Package) J Y X B F I C D Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A B C D F H I J M Option 1 Option 2 X Y X Y Lead SOP (Exposed Pad) Plastic Package Richtek Technology Corporation 14F, No. 8, Tai Yuen 1 st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863) Richtek products are sold by description only. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. 10