High Temperature, Low Drift, Micropower 2.5 V Reference ADR225

Transcription

1 Data Sheet FEATURES Extreme high temperature operation 4 C to + C, 8-lead FLATPACK 4 C to +75 C, 8-lead SOIC Temperature coefficient 4 ppm/ C, 8-lead FLATPACK ppm/ C, 8-lead SOIC High output current: ma Low supply current: 5 µa maximum Initial accuracy: ±.4% (± mv maximum), 8-lead SOIC Low dropout voltage Wide supply range: 3.3 V to 6 V APPLICATIONS Down-hole drilling and instrumentation Avionics Heavy industrial High temperature environments GENERAL DESCRIPTION The is a precision.5 V band gap voltage reference specified for a high temperature operation of 75 C and C. It uses a micropower core topology and laser trimming of highly stable, thin film resistors to achieve a temperature coefficient of 3 ppm/ C (maximum) up to 75 C and an initial accuracy of.4% (± mv maximum). A maximum operating current of 5 µa and a low dropout voltage allow the to function very well in battery-powered equipment. The voltage reference is offered in an 8-lead SOIC package with an operating temperature range of 4 C to +75 C. High Temperature, Low Drift, Micropower.5 V Reference PIN CONFIGURATION NC V S NC 3 GND 4 TOP VIEW (Not to Scale) 8 NC 7 NC 6 OUTPUT 5 NC NOTES. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. Figure. Pin Configuration for SOIC and FLATPACK Packages It is also available in an 8-lead ceramic flat pack (FLATPACK) with an operating temperature range of 4 C to + C. Both devices are designed for robustness at extreme temperatures and are qualified for hours of operation at the maximum temperature rating. The is a member of a growing series of high temperature qualified products offered by Analog Devices, Inc. For a complete selection table of the available high temperature products, see the high temperature product list and qualification data available at Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support

2 TABLE OF CONTENTS Features... Applications... Pin Configuration... General Description... Revision History... Specifications... 3 Electrical Characteristics... 3 Absolute Maximum Ratings... 4 Data Sheet Predicted Lifetime vs. Operating Temperature...4 Thermal Resistance...4 ESD Caution...4 Typical Performance Characteristics...5 Theory of Operation...9 Basic Voltage Reference Connections...9 Outline Dimensions... Ordering Guide... REVISION HISTORY /3 Rev. A to Rev. B Change to Features Section... Added Caption to Figure... Changes to Table... 3 Added Figure 6, Figure 7, Figure 8, Figure, Figure 3, Figure 4, Figure 8, and Figure 9; Renumbered Sequentially /3 Rev. to Rev. A Changes to Data Sheet Title and Added Wide Supply Range: 3.3 V to 6 V to Features Section... Changed Supply Voltage from.3 V to +5 V to.3 V to +8 V; Table /3 Revision : Initial Version Rev. B Page of

3 Data Sheet SPECIFICATIONS ELECTRICAL CHARACTERISTICS VS = 3.3 V, VOUT =.5 V, TMIN < TA < TMAX, unless otherwise noted. Table. 8-Lead SOIC 8-Lead FLATPACK 4 C TA +75 C 4 C TA + C Parameter Symbol Test Conditions/Comments Min Typ Max Min Typ Max Unit SUPPLY CURRENT ISY No load µa INITIAL ACCURACY VO IOUT = ma ± ± ±5 ±6 mv TEMPERATURE COEFFICIENT TCVOUT IOUT = ma ppm/ C REGULATION Line Regulation ΔVOUT/ΔVIN 3. V VS 5 V, IOUT = ma mv/v Load Regulation 3 ΔVOUT/ΔVLOAD VS = 5. V, ma IOUT ma mv/ma VOLTAGE Dropout Voltage VS VOUT ILOAD = ma.. V Noise Voltage en. Hz to Hz 5 5 µv p-p For proper operation, a µf capacitor is required between the OUTPUT pin and the GND pin of the device. TCVOUT is defined as the ratio of output change with temperature variation to the specified temperature range expressed in ppm/ C. TCVOUT = (VMAX VMIN)/VOUT(TMAX TMIN) 3 Load regulation specification includes the effect of self-heating. Rev. B Page 3 of

4 ABSOLUTE MAXIMUM RATINGS Table. Parameter Rating Supply Voltage.3 V to +8 V OUTPUT to GND.3 V to VS +.3 V Storage Temperature Range 65 C to +5 C Operating Temperature Range 8-Lead SOIC 4 C to +75 C 8-Lead FLATPACK 4 C to + C Junction Temperature Range 8-Lead SOIC 4 C to + C 8-Lead FLATPACK 4 C to +45 C Lead Temperature (Soldering 6 sec) 3 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PREDICTED LIFETIME vs. OPERATING TEMPERATURE Comprehensive reliability testing is performed on the. Product lifetimes at extended operating temperature are obtained using high temperature operating life (HTOL). Lifetimes are predicted from the Arrhenius equation, taking into account potential design and manufacturing failure mechanism assumptions. HTOL is performed to JEDEC JESD-A8. A minimum of three wafer fab and assembly lots are processed through HTOL at the maximum operating temperature. Comprehensive reliability testing is performed on all Analog Devices, Inc., high temperature (HT) products. PREDICTED LIFETIME (Hours) k k k Data Sheet OPERATING Figure. Predicted Lifetime vs. Operating Temperature THERMAL RESISTANCE θja is specified for worst-case conditions; that is, θja is specified for the device soldered in the circuit board. Table 3. Package Type θja θjc Unit 8-Lead SOIC 43 C/W 8-Lead FLATPACK 5 C/W ESD CAUTION 55- Rev. B Page 4 of

5 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VS = 3.3 V, VOUT =.5 V, TMIN TA TMAX for 8-lead SOIC package, unless otherwise noted OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Figure 3. Output Voltage (VOUT) vs. Temperature Figure 6. Output Voltage (VOUT) vs. Temperature, FLATPACK Package NUMBER OF UNITS TCV OUT (ppm/ C) Figure 4. TCVOUT Distribution, 4 C to +75 C 55-5 NUMBER OF UNITS TCV OUT (ppm/ C) Figure 7. TCVOUT Distribution, 4 C to + C, FLATPACK Package NUMBER OF PARTS NUMBER OF PARTS OUTPUT VOLTAGE ACCURACY (%) Figure 5. Output Voltage Accuracy at 75 C OUTPUT VOLTAGE ACCURACY (%) Figure 8. Output Voltage Accuracy at C, FLATPACK Package 55- Rev. B Page 5 of

6 Data Sheet SUPPLY CURRENT (µa) SUPPLY CURRENT (µa) Figure 9. Supply Current (ISY) vs. Temperature Figure. Supply Current (ISY) vs. Temperature, FLATPACK Package 5 LOAD REGULATION (ppm/ma) Figure. Load Regulation vs. Temperature (ILOAD = ma to ma) LOAD REGULATION (ppm/ma) Figure 3. Load Regulation vs. Temperature (ILOAD = ma to ma), FLATPACK Package LINE REGULATION (ppm/v) 4 3 LINE REGULATION (ppm/v) Figure. Line Regulation vs. Temperature Figure 4. Line Regulation vs. Temperature, FLATPACK Package 55-5 Rev. B Page 6 of

7 Data Sheet C +5 C +75 C C +5 C + C DROPOUT VOLTAGE (V) DROPOUT VOLTAGE (V) LOAD CURRENT (ma) Figure 5. Dropout Voltage vs. Load Current (ILOAD) LOAD CURRENT (ma) Figure 8. Dropout Voltage vs. Load Current (ILOAD), FLATPACK Package UNIT UNIT 3 UNIT OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Figure 6. Thermal Hysteresis, ILOAD = ma Figure 9. Thermal Hysteresis, ILOAD = ma, FLATPACK Package 55-7 V IN = V/DIV C OUT = µf NO LOAD V IN = 5V/DIV C IN = C OUT = µf R L = kω V 5V V V OUT = V/DIV V OUT = mv/div CH V B W CH V Mµs A CH 4.4V 55-3 CH 5V B W CH mv Mµs A CH 7.3V 55-4 Figure 7. Power-On Response (see Figure 5) Figure. Line Transient Response (see Figure 5) Rev. B Page 7 of

8 Data Sheet LOAD CURRENT ma.4 5. V OUT = mv/div C OUT = µf ma OUTPUT IMPEDANCE (Ω) CH V CH mv Mµs A CH.3V Figure. Load Transient Response 55-. k k k M FREQUENCY (Hz) Figure 3. Output Impedance (ZOUT) vs. Frequency, CIN = COUT = µf 55- POWER SUPPLY REJECTION RATIO (db) k k k M M FREQUENCY (Hz) Figure. Power Supply Rejection Ratio (PSRR) vs. Frequency, CLOAD = µf 55-5 Rev. B Page 8 of

9 Data Sheet THEORY OF OPERATION BASIC VOLTAGE REFERENCE CONNECTIONS The circuit shown in Figure 4 is the basic configuration for the. Note that a µf and. µf bypass network on the input and at least a µf bypass capacitor on the output are required for proper device operation. It is recommended that no connections be made to Pin, Pin 3, Pin 5, Pin 7, and Pin 8. NC V S 8 7 µf.µf NC NC = NO CONNECT. NC NC OUTPUT NC + µf + TANT µf Figure 4. Basic Voltage Reference Connections 55- VCC V+ +5V +5V + C µf C.µF U V S OUTPUT GND + C3 µf C4.µF R.5kΩ R3.5kΩ +IN A IN A V UA AD8634 5V RTD +IN IN +V S +5V U3 AD89 V OUT R.5kΩ 5V V S 55-7 Figure 5. Typical High Temperature Resistance Temperature Detector (RTD) Signal Conditioning Circuit Rev. B Page 9 of

10 Data Sheet OUTLINE DIMENSIONS 5. (.968) 4.8 (.89) 4. (.574) 3.8 (.497) (.44) 5.8 (.84).5 (.98). (.4) COPLANARITY. SEATING PLANE.7 (.5) BSC.75 (.688).35 (.53).5 (.).3 (.) 8.5 (.98).7 (.67).5 (.96).5 (.99).7 (.5).4 (.57) 45 COMPLIANT TO JEDEC STANDARDS MS--AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 47-A Figure 6. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) R TYP SQ SQ.85 TOP VIEW END VIEW IDEX MARK BOTTOM VIEW.4.7 MIN.35 TYP.5 TYP MIN SIDE VIEW A Figure 7. 8-Lead Ceramic Flat Package [FLATPACK] (F-8-) Dimensions shown in inches ORDERING GUIDE Model Temperature Range Package Description Package Option HRZN 4 C to +75 C 8-Lead Standard Small Outline Package [SOIC_N] R-8 HFZ 4 C to + C 8-Lead Ceramic Flat Package [FLATPACK] F-8- Z = RoHS Compliant Part. Rev. B Page of

11 Data Sheet NOTES Rev. B Page of

12 Data Sheet NOTES 3 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D55--/3(B) Rev. B Page of