RT9807. Micro-Power Voltage Detector with Manual Reset. General Description. Features. Applications. Pin Configurations. Ordering Information RT9807-

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1 Micro-Power Voltage Detector with Manual Reset General Description The is a micro-power voltage detector with deglitched manual reset input which supervises the power supply voltage level for microprocessors (µp) or digital systems. It provides internally fixed threshold levels ranging from.v to.v with 0.V per step, which covers most digital applications. It features low supply current of µa. The performs supervisory function by sending out a reset signal whenever the voltage falls below a preset threshold level. The timeout period of this reset signal can be adjusted via an external capacitor. Once recovers above the threshold level, the reset signal will be released after a certain delay time. To manually pull reset signal low, just pull the manual reset input (MR) below the specified logic-low level. The is available in an SOT-- package. Ordering Information - Note : Richtek products are : Marking Information For marking information, contact our sales representative directly or through a Richtek distributor located in your area. Package Type B : SOT-- Lead Plating System G : Green (Halogen Free and Pb Free) Output Voltage :.V :.V : :.V :.V } RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-00. } Suitable for use in SnPb or Pb-free soldering processes. Features Monitor System Voltages from 0.9V to.v Capacitor-Adjustable Reset Timeout Period Manual Reset Input Low Quiescent Current High Accuracy ±.% Low Functional Supply Voltage 0.9V N-Channel Open-Drain Output Small SOT-- Package RoHS Compliant and Halogen Free Applications Computers Controllers Intelligent Instruments Critical up and uc Power Monitoring Portable/Battery-Powered Equipment Pin Configurations (TOP VIEW) MR SOT-- Typical Application Circuit V DD C IN uf MR R 70k Reset C 0nF

2 Functional Pin Description Pin No. Pin Name Pin Function Reset Output Pin. (Open drain) Ground Pin. MR Manual Reset Pin. Connect an external capacitor for setting reset timeout period. Supply Voltage Input Pin. Function Block Diagram N-MOSFET - + Comparator Timeout Setting V REF Manual Reset MR Absolute Maximum Ratings (Note ) Supply Input Voltage, V DD V to 6V Reset Output Voltage, V to 6V Other Pins V to 6V Power Dissipation, P T A = C SOT W Package Thermal Resistance (Note ) SOT--, θ JA C/W Junction Temperature Range C Lead Temperature (Soldering, 0 sec.) C Storage Temperature Range C to 0 C ESD Susceptibility (Note ) HBM (Human Body Mode) kv MM (Machine Mode) V Recommended Operating Conditions (Note ) Junction Temperature Range C to C Ambient Temperature Range C to 8 C

3 Electrical Characteristics (T A = C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Operating Range V DD V Supply Current I DD V TH = V, V DD =.V -- µa Reset Threshold V TH. --. V Threshold Voltage Accuracy V TH. --. % Threshold Voltage Hysteresis V HYS -- 0 x V TH -- mv Reset Threshold Tempco ppm/ C Drop to Reset Delay t RP Drop = V TH 0mV µs Output Voltage Low (Note ) V OL V DD < V TH(min.), I SINK =.ma V MR Input Logic-High V IH 0.7V DD Threshold voltage Logic-Low VIL V DD MR Glitch Rejection ns MR to Reset Propagation Delay t MR µs MR Pull-up Resistance R MR kω Reset Timeout Period t RP C = 00pF..7.0 C = 0pF Source Current I RAMP na Source Threshold Voltage V TH-RAMP V Threshold Hysteresis mv Note. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note. θja is measured in natural convection at TA = C on a low effective thermal conductivity test board of JEDEC - thermal measurement standard. Note. Devices are ESD sensitive. Handling precaution is recommended. Note. The device is not guaranteed to function outside its operating conditions. Note. The voltage VOL can be calculated by VOL = - Ir x R. Where R is the pull-up resistor and Ir is the current flowing through the pull-up resistor. For typical application R = 00kΩ, VOL is less than 0.V. V ms

4 Typical Operating Characteristics 6 Supply Current vs. Input Voltage 0.67 Threshold Voltage vs. Temperature Supply Current (µa) TA = 8 C TA = C TA = C TA = 0 C Threshold Voltage (V) Rising Falling 0 Open Input Voltage (V) R = 70kΩ Reset Delay Time (ms) Reset Delay Time vs Capacitance = V, R = 70kΩ Cpacitance (nf) Drop Reset Delay Time (µs) Drop Reset Delay Time vs. Temperature 0 = V, Open, R = 70kΩ Detector Threshold vs. Temperature Power On Reset Delay Time vs. Temperature 0 Detector Threshold (V).6 Rising.6 Falling... = V, Open, R = 70kΩ Power On Reset Delay Time (µs) = V, Open, R = 70kΩ

5 Application Information The provides adjustable reset delay time to fit the need of a variety of µp applications. The reset delay time of the can be adjusted by connecting a capacitor between the pin and. The capacitor must fit the need of low-leakage (<0nA), and it is recommended to use a ceramic capacitor such as X7R or NPO type. V CC R R R C Reset Delay Time Setting When the voltage exceeds the threshold voltage, a current source will start to charge the capacitor and the voltage will rise. When the voltage exceeds 0.6V, the voltage will change from low to high. Therefore, there is a delay time between the point of reaching its threshold voltage and the active-high point. The delay time can be calculated according to the following equation. t DELAY (µs) =.7 x 06 x C (µf) + 7(µs) The rising and falling of the VCC and voltage can be explained in five steps as shown in the following diagram. VCC Figure. Voltage Divider A Hysteresis range B V CC_TH V CC_TH Hysteresis Voltage Minimum Operation Voltage Voltage Threshold Voltage V 0.6V Voltage Power-On Reset Delay Time Voltage Delay Time Operating with a Voltage Divider The voltage detector monitors the VCC voltage to generate a reset signal when VCC is higher than the detecting level. The detecting level is determined by an external resistive voltage divider. Figure. Delay Time R R R V CC_TH = V TH x +, V TH : Threshold Voltage. V CC_HYS = V HYS x + R Drop Reset Delay Time Figure. Operation Diagram. voltage is pulled up to VCC voltage.. When the VCC voltage is down to the detector threshold voltage (Point A), voltage becomes low level.. When the VCC voltage is lower than minimum operating voltage, the voltage is indefinite. In the case of open drain type, voltage is equal to pull-up voltage.. voltage becomes low level.. When the VCC voltage exceeds the threshold voltage (Point B), the internal source current will start to charge capacitor. The voltage will go high after a delay time when the capacitor voltage reaches 0.6V.

6 Interfacing to Other Voltages The is an open-drain voltage detector that can provide different voltage level of reset signals for processor application. As shown in Figure, the open-drain output can be connected to another voltage level less than.v. This allows for easy logic compatibility to various microprocessors. V V System Manual Reset Input Many processor based products require manual reset capability, allowing the user or external logic circuitry to initiate a reset. A logic low on MR asserts reset. Reset remains asserted while MR is low and for the reset timeout period after MR returns high. Connect a normally open momentary switch from MR to ground to create a manual reset function. Thermal Considerations For continuous operation, do not exceed absolute maximum operation junction temperature. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula : P D(MAX) = ( T J(MAX) T A ) / θ JA where T J(MAX) is the maximum operation junction temperature, T A is the ambient temperature and the θ JA is the junction to ambient thermal resistance. For recommended operating conditions specification of the, the maximum junction temperature is C. The junction to ambient thermal resistance θ JA is layout dependent. For SOT-- package, the thermal resistance θ JA is 0 C/W on the standard JEDEC - single layer 6 70k Figure.V µf thermal test board. The maximum power dissipation at T A = C can be calculated by the following formula : P D(MAX) = ( C C) / (0 C/W) = 0.W for SOT-- package The maximum power dissipation depends on operating ambient temperature for fixed T J(MAX) and thermal resistance θ JA. For package, the derating curve in Figure allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. Maximum Power Dissipation (W) Figure. Derating Curve for Package Layout Considerations is a precise current source. When developing the layout for the application, be careful to minimize board capacitance and leakage currents around this pin. Traces connected to should be kept as short as possible. Traces carrying high-speed digital signals and traces with large voltage potentials should be routed as far from as possible. Leakage current and stray capacitance (e.g., a scope probe) at this pin can cause errors in the reset delay time. SW MR Ambient R C IN C C should be placed as close as possible to the IC. Figure 6. PCB Layout Guide Single Layer PCB SOT--

7 Outline Dimension D H L C B b A A e Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A A B b C D e H L SOT-- Surface Mount Package Richtek Technology Corporation F, No. 8, Tai Yuen st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (886)6789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. 7