Low Voltage, 400 MHz, Quad 2:1 Mux with 3 ns Switching Time ADG774A

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1 Data Sheet FEATURES Bandwidth: >4 MHz Low insertion loss and on resistance: 2.2 Ω typical On resistance flatness:.3 Ω typical Single 3 V/5 V supply operation Very low distortion: <.3% Low quiescent supply current: 1 na typical Fast switching times ton = 6 ns toff = 3 ns TTL-/CMOS-compatible Pb-free packages 16-lead QSSOP 16-lead 3 mm 3 mm body LFCSP GERAL DESCRIPTION The is a monolithic CMOS device comprising four 2:1 multiplexer/demultiplexers with high impedance outputs. The CMOS process provides low power dissipation yet offers high switching speed and low on resistance. The on resistance variation is typically less than.5 Ω over the input signal range. The bandwidth of the is typically 4 MHz and this, coupled with low distortion (typically.3%), makes the part suitable for switching of high speed data signals. The on resistance profile is very flat over the full analog input range ensuring excellent linearity and low distortion. CMOS construction ensures ultralow power dissipation. The operates from a single 3.3 V/5 V supply and is TTL logic-compatible. The control logic for each switch is shown in the truth table (see Table 5). Low Voltage, 4 MHz, Quad 2:1 Mux with 3 ns Switching Time FUNCTIONAL BLOCK DIAGRAM S1A S1B S2A S2B S3A S3B S4A S4B 1 OF 2 DECODER Figure 1. These switches conduct equally well in both directions when on. In the off condition, signal levels up to the supplies are blocked. The switches exhibit break-before-make switching action. PRODUCT HIGHLIGHTS 1. Wide bandwidth data rates of >4 MHz. 2. Ultralow power dissipation. 3. Low leakage over temperature. 4. Break-before-make switching prevents channel shorting when the switches are configured as a multiplexer. 5. Crosstalk is typically 7 1 MHz. 6. Off isolation is typically 65 1 MHz. 7. Available in compact 3 mm 3 mm LFCSP. D1 D2 D3 D Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 916, Norwood, MA , U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support

2 TABLE OF CONTTS Features... 1 Functional Block Diagram... 1 General Description... 1 Product Highlights... 1 Revision History... 2 Specifications... 3 Single Supply... 3 Absolute Maximum Ratings... 5 Data Sheet ESD Caution...5 Pin Configurations and Function Descriptions...6 Typical Performance Characteristics...7 Test Circuits...9 Terminology Application Circuits Outline Dimensions Ordering Guide REVISION HISTORY 4/16 Rev. B to Rev. C Changed CP-16-3 to CP Throughout Changes to Figure 3 and Table Updated Outline Dimensions Changes to Ordering Guide /6 Rev. A to Rev. B Updated Format... Universal Added LFCSP Model... Universal Added Lead-Free Models... Universal Changes to Table Updated Outline Dimensions Changes to Ordering Guide /3 Rev. to Rev. A Changes to TPCs Updated Outline Dimensions /1 Revision : Initial Version Rev. C Page 2 of 14

3 Data Sheet SPECIFICATIONS SGLE SUPPLY VDD = 5 V ± 1%, GND = V, all specifications TM to TMAX, unless otherwise noted. 1 Table 1. B Version Parameter 25 C TM to TMAX Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range to 2.5 V On Resistance, RON 2.2 Ω typ VD = V to 1 V, IS = 1 ma Ω max On Resistance Match Between Channels, RON.15 Ω typ VD = V to 1 V, IS = 1 ma.5 Ω max On Resistance Flatness, RFLAT(ON).3 Ω typ VD = V to 1 V, IS = 1 ma.6 Ω max LEAKAGE CURRTS Source Off Leakage, IS (OFF) ±.1 na typ VD = 3 V/1 V, VS = 1 V/3 V, see Figure 17 ±.1 ±.25 na max Drain Off Leakage, ID (OFF) ±.1 na typ VD = 3 V/1 V, VS = 1 V/3 V, see Figure 17 ±.1 ±.25 na max Channel On Leakage, ID, IS (ON) ±.1 na typ VD = VS = 3 V/1 V, see Figure 18 ±.1 ±.25 na max DIGITAL PUTS Input High Voltage, VH 2.4 V min Input Low Voltage, VL.8 V max Input Current IL or IH.1 μa typ V = VL or VH ±.1 μa max Digital Input Capacitance, C 3 pf typ DYNAMIC CHARACTERISTICS 2 ton, ton () 6 ns typ CL = 35 pf, RL = 5 Ω, VS = 2 V, see Figure ns max toff, toff () 3 ns typ CL = 35 pf, RL = 5 Ω, VS = 2 V, see Figure 22 6 ns max Break-Before-Make Time Delay, td 3 ns typ CL = 35 pf, RL = 5 Ω, VS1 = VS2 = 2 V, see Figure 23 1 ns min Off Isolation 65 db typ f = 1 MHz, RL = 5 Ω, see Figure 2 Channel-to-Channel Crosstalk 7 db typ f = 1 MHz, RL = 5 Ω, see Figure 21 Bandwidth 3 db 4 MHz typ RL = 5 Ω, see Figure 19 Distortion.3 % typ RL = 1 Ω Charge Injection 6 pc typ CL = 1 nf, see Figure 24, VS = V CS (OFF) 5 pf typ CD (OFF) 7.5 pf typ CD, CS (ON) 12 pf typ POWER REQUIREMTS IDD 1 μa max.1 μa typ 1 Temperature range for B version is 4 C to +85 C. 2 Guaranteed by design, not subject to production test. VDD = 5.5 V Digital inputs = V or VDD Rev. C Page 3 of 14

4 Data Sheet VDD = 3 V ± 1%, GND = V, all specifications TM to TMAX, unless otherwise noted. 1 Table 2. B Version Parameter 25 C TM to TMAX Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range to 1.5 V On Resistance, RON 4 Ω typ VD = V to 1 V; IS = 1 ma 6 7 Ω max On Resistance Match Between Channels, RON.15 Ω typ VD = V to 1 V, IS = 1 ma.5 Ω max On Resistance Flatness, RFLAT(ON) 1.5 Ω typ VD = V to 1 V, IS = 1 ma 3 Ω max LEAKAGE CURRTS Source Off Leakage, IS (OFF) ±.1 na typ VD = 2 V/1 V, VS = 1 V/2 V, see Figure 17 ±.1 ±.25 na max Drain Off Leakage, ID (OFF) ±.1 na typ VD = 2 V/1 V, VS = 1 V/2 V, see Figure 17 ±.1 ±.25 na max Channel On Leakage, ID, IS(ON) ±.1 na typ VD = VS = 2 V/1 V, see Figure 18 ±.1 ±.25 na max DIGITAL PUTS Input High Voltage, VH 2. V min Input Low Voltage, VL.4 V max Input Current IL or IH.1 μa typ V = VL or VH ±.1 μa max Digital Input Capacitance, C 3 pf typ DYNAMIC CHARACTERISTICS 2 ton, ton () 7 ns typ CL = 35 pf, RL = 5 Ω, VS = 1.5 V, see Figure ns max toff, toff () 4 ns typ CL = 35 pf, RL = 5 Ω, VS = 1.5 V, see Figure 22 8 ns max Break-Before-Make Time Delay, td 3 ns typ CL = 35 pf, RL = 5 Ω, VS1 = VS2 = 1.5 V, see Figure 23 1 ns min Off Isolation 65 db typ f = 1 MHz, RL = 5 Ω Channel-to-Channel Crosstalk 7 db typ f = 1 MHz, RL = 5 Ω, see Figure 21 Bandwidth 3 db 4 MHz typ RL = 5 Ω, see Figure 19 Distortion 1.5 % typ RL = 1 Ω Charge Injection 4 pc typ CL = 1 nf, see Figure 24, VS = V CS (OFF) 5 pf typ CD (OFF) 7.5 pf typ CD, CS (ON) 12 pf typ POWER REQUIREMTS IDD 1 μa max.1 μa typ 1 Temperature range for B version is 4 C to +85 C. 2 Guaranteed by design, not subject to production test. VDD = 3.3 V Digital inputs = V or VDD Rev. C Page 4 of 14

5 Data Sheet ABSOLUTE MAXIMUM RATGS TA = 25 C, unless otherwise noted. Table 3. Parameters Rating VDD to GND.3 V to +6 V Analog, Digital Inputs 1.3 V to VDD +.3 V or 3 ma, whichever occurs first Continuous Current, S or D 1 ma Peak Current, S or D 3 ma (pulsed at 1 ms, 1% duty cycle max) Operating Temperature Range Industrial (B Version) 4 C to +85 C Storage Temperature Range 65 C to +15 C Junction Temperature 15 C Thermal Impedance, θja 16-Lead QSSOP C/W 2 16-Lead LFCSP (3 mm 3 mm) 48.7 C/W 2 Lead Temperature Soldering Vapor Phase (6 sec) 215 C Infrared (15 sec) 22 C Reflow Soldering (Pb-free) Peak Temperature 26 C (+ C/ 5 C) Time at Peak Temperature 1 sec to 4 sec Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION 1 Overvoltages at, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given. 2 Measured with the device soldered on a four-layer board. Rev. C Page 5 of 14

6 D2 GND D3 S3B Data Sheet P CONFIGURATIONS AND FUNCTION DESCRIPTIONS S1A V DD S1A 2 S1B 3 D1 4 S2A 5 S2B 6 D2 7 GND 8 TOP VIEW (Not to Scale) 16 V DD S4A 13 S4B 12 D4 11 S3A 1 S3B 9 D3 Figure 2. QSOP Pin Configuration S1B 1 12 S4A D S4B S2A 3 S2B 4 TOP VIEW (Not to Scale) 1 9 D4 S3A NOTES 1. THE EXPOSED PAD MUST BE TIED TO GND. Figure 3. LFCSP Pin Configuration Table 4. Pin Function Descriptions Pin No. QSOP LFCSP Mnemonic Function 1 15 Logic Control Input S1A Source Terminal 1A. May be an input or output. 3 1 S1B Source Terminal 1B May be an input or output. 4 2 D1 Drain Terminal D1. May be an input or output. 5 3 S2A Source Terminal 2A. May be an input or output. 6 4 S2B Source Terminal 2B. May be an input or output. 7 5 D2 Drain Terminal D2. May be an input or output. 8 6 GND Ground ( V) Reference. 9 7 D3 Drain Terminal D3. May be an input or output. 1 8 S3B Source Terminal 3B. May be an input or output S3A Source Terminal 3A. May be an input or output D4 Drain Terminal D4. May be an input or output S4B Source Terminal 4B. May be an input or output S4A Source Terminal 4A. May be an input or output Logic Control Input. When high, all switches are disabled VDD Most Positive Power Supply Potential. Not applicable 17 EPAD Exposed Pad. The exposed pad must be tied to GND. Table 5. Truth Table D1 D2 D3 D4 Function 1 X Hi-Z Hi-Z Hi-Z Hi-Z DISABLE S1A S2A S3A S4A = 1 S1B S2B S3B S4B = 1 Rev. C Page 6 of 14

7 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 2 T A = 25 C 2 V DD = 3V 16 V DD = 5.V R ON (Ω) 8 V DD = 4.5V R ON (Ω) C 4 V DD = 5.5V C 4 C /V D (V) Figure 4. On Resistance as a Function of Drain (VD) or Source (VS) Voltage for VDD = 5 V ± 1% /V D (V) Figure 7. On Resistance as a Function of Drain (VD) or Source (VS) Voltage for Different Temperatures with 3 ingle Supplies T A = 25 C V DD = 5.V S = V TEMP = 25 C V D = V DD R ON (Ω) 12 8 V DD = 2.7V V DD = 3.V CURRT (na) I S (OFF) I D (OFF) I S, I D (ON) /V D (V) V DD = 3.3V Figure 5. On Resistance as a Function of Drain (VD) or Source (VS) Voltage for VDD = 3 V ± 1% /V D (V) Figure 8. Leakage Current as a Function of Drain (VD) or Source (VS) Voltage for VDD = 5 V R ON (Ω) V DD = 5V +25 C +85 C CURRT (na) V DD = 3.V S = V TEMP = 25 C V D = V DD I D (OFF) I S (OFF) I S, I D (ON) /V D (V) 4 C Figure 6. On Resistance as a Function of Drain (VD) or Source (VS) Voltage for Different Temperatures with 5 ingle Supplies /V D (V) Figure 9. Leakage Current as a Function of Drain (VD) or Source (VS) Voltage for VDD = 3 V Rev. C Page 7 of 14

8 Data Sheet CURRT (na) V DD = 5.V S = V TEMP = 25 C V D = 3V/1V = 1V/3V I D (OFF) I S (OFF) I S, I D (ON) ATTUATION (db) TEMPERATURE ( C) Figure 1. Leakage Current as a Function of Temperature, VDD = 5 V FREQUCY (MHz) Figure 13. Crosstalk vs. Frequency CURRT (na) V DD = 3.V S = V TEMP = 25 C V D = 2V/1V = 1V/2V I D (OFF) I S, I D (ON) I S (OFF) ON RESPONSE (db) TEMPERATURE ( C) Figure 11. Leakage Current as a Function of Temperature, VDD = 3 V FREQUCY (MHz) Figure 14. Bandwidth ATTUATION (db) 4 6 Q J (pc) V DD = 3V V DD = 5V FREQUCY (MHz) Figure 12. Off Isolation vs. Frequency VOLTAGE (V) Figure 15. Charge Injection vs. Source Voltage Rev. C Page 8 of 14

9 Data Sheet TEST CIRCUITS.1µF V DD I DS NETWORK ANALYZER S V1 D S1A 5Ω R ON = V1/I DS V D1 5Ω V OUT GND Figure 16. On Resistance Figure 19. Bandwidth V DD.1µF I S (OFF) A S D I D (OFF) A V D S1A 5Ω NETWORK ANALYZER 5Ω V D1 5Ω V OUT GND Figure 17. Off Leakage Figure 2. Off Isolation.1µF V DD NETWORK ANALYZER NC S D I D (ON) A S1A S2A 5Ω V OUT NC = NO CONNECT V D R L 5Ω V D2 D1 GND 5Ω Figure 18. On Leakage Figure 21. Channel-to-Channel Crosstalk Rev. C Page 9 of 14

10 Data Sheet 5V.1µF V 3V V DD 5% 5% S D V OUT 9% 9% R L 1Ω C L 35pF V OUT GND t ON t OFF Figure 22. Switching Times.1µF 5V V DD 3V S1A V V D1 OUT 5% 5% S1B V V R L C L V 8% 8% S OUT 1Ω 35pF DECODER t D t D GND Figure 23. Break-Before-Make Time Delay V V DD R S S1A S1B S2A S2B S3A S3B S4A S4B 1 OF 2 DECODER C L 1nF C L 1nF C L 1nF C L 1nF D1 V OUT D2 V OUT D3 V OUT D4 V OUT V V OUT 3V Q J = C L V OUT V OUT Figure 24. Charge Injection Rev. C Page 1 of 14

11 Data Sheet TERMOLOGY VDD Most positive power supply potential. GND Ground ( V) reference. S Source terminal. May be an input or output. D Drain terminal. May be an input or output. Logic control input. Logic control input. RON Ohmic resistance between D and S. RON On resistance match between any two channels, that is, RON max RON min. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. IS (OFF) Source leakage current with the switch off. ID (OFF) Drain leakage current with the switch off. ID, IS (ON) Channel leakage current with the switch on. VD (VS) Analog voltage on the D and S terminals. CS (OFF) Off switch source capacitance. CD (OFF) Off switch drain capacitance. CD, CS (ON) On switch capacitance. ton Delay between applying the digital control input and the output switching on. See Figure 22. toff Delay between applying the digital control input and the output switching off. td Off time or on time measured between the 8% points of both switches when switching from one address state to another. See Figure 23. Crosstalk A measure of unwanted signal that is coupled through from one channel to another because of parasitic capacitance. Off Isolation A measure of unwanted signal coupling through an off switch. Bandwidth Frequency response of the switch in the on state measured at 3 db down. Distortion RFLAT(ON)/RL Rev. C Page 11 of 14

12 Data Sheet APPLICATION CIRCUITS 1 BASE Tx+ 1 BASE Tx Tx1 1 BASE Tx+ 1 BASE Tx Tx2 RJ45 1 BASE Tx+ 1 BASE Tx 1 BASE Tx+ 1 BASE Tx Rx1 Rx2 TRANSFORMER 1 BASE Tx 1 BASE Tx Figure 25. Full Duplex Transceiver Tx1 Rx1 12Ω 1Ω Figure 26. Loop Back Figure 27. Line Termination Figure 28. Line Clamp Rev. C Page 12 of 14

13 Data Sheet OUTLE DIMSIONS.197 (5.).193 (4.9).189 (4.8) (4.1).154 (3.91).15 (3.81).244 (6.2).236 (5.99).228 (5.79).65 (1.65).49 (1.25).69 (1.75).53 (1.35).1 (.25).6 (.15).2 (.51).1 (.25).1 (.25).4 (.1) COPLANARITY.4 (.1).25 (.64) BSC.12 (.3).8 (.2) SEATG PLANE 8.5 (1.27).16 (.41).41 (1.4) REF COMPLIANT TO JEDEC STANDARDS MO-137-AB CONTROLLG DIMSIONS ARE CHES; MILLIMETER DIMSIONS ( PARTHESES) ARE ROUNDED-OFF CH EQUIVALTS FOR REFERCE ONLY AND ARE NOT APPROPRIATE FOR USE DESIGN. Figure Lead Shrink Small Outline Package [QSOP] (RQ-16) Dimensions shown in inches and (millimeters) A P 1 DICATOR SQ BSC P 1 DICATOR EXPOSED PAD SQ SEATG PLANE TOP VIEW MAX.2 NOM COPLANARITY.8.2 REF BOTTOM VIEW COMPLIANT TO JEDEC STANDARDS MO-22-WEED-6. Figure Lead Lead Frame Chip Scale Package [LFCSP] 3 mm 3 mm Body and.75 mm Package Height (CP-16-27) Dimensions shown in millimeters.2 M FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE P CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET A ORDERG GUIDE Model 1 Temperature Range Package Description Package Option BRQ-REEL7 4 C to +85 C 16-Lead Shrink Small Outline Package [QSOP] RQ-16 BRQZ 4 C to +85 C 16-Lead Shrink Small Outline Package [QSOP] RQ-16 BRQZ-REEL 4 C to +85 C 16-Lead Shrink Small Outline Package [QSOP] RQ-16 BRQZ-REEL7 4 C to +85 C 16-Lead Shrink Small Outline Package [QSOP] RQ-16 BCPZ-REEL 4 C to +85 C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP BCPZ-R2 4 C to +85 C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP Z = RoHS Compliant Part. Rev. C Page 13 of 14

15 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc.: BCPZ-REEL BRQ-REEL7 BRQZ-REEL7 BRQZ BCPZ-R2 BRQZ-REEL

Low Voltage, 400 MHz, Quad 2:1 Mux with 3 ns Switching Time ADG774A

Low Voltage, 400 MHz, Quad 2:1 Mux with 3 ns Switching Time ADG774A Low Voltage, 4 MHz, Quad 2:1 Mux with 3 ns Switching Time FEATURES Bandwidth: >4 MHz Low insertion loss and on resistance: 2.2 Ω typical On resistance flatness:.3 Ω typical Single 3 V/5 V supply operation