ADG1606/ADG Ω RON, 16-Channel, Differential 8-Channel, ±5 V,+12 V,+5 V, and +3.3 V Multiplexers FEATURES FUNCTIONAL BLOCK DIAGRAMS

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1 4.5 Ω RON, 6-Channel, Differential 8-Channel, ±5 V,+2 V,+5 V, and +3.3 V Multiplexers ADG66/ADG67 FEATURES 4.5 Ω typical on resistance. Ω on resistance flatness ±3.3 V to ±8 V dual supply operation 3.3 V to 6 V single supply operation No VL supply required 3 V logic-compatible inputs Rail-to-rail operation Up to 378 ma of continuous current per channel 28-lead TSSOP and 32-lead, 5 mm 5 mm LFCSP_VQ APPLICATIONS Communication systems Medical systems Audio signal routing Video signal routing Automatic test equipment Data acquisition systems Battery-powered systems Sample-and-hold systems Relay replacements FUNCTIONAL BLOCK DIAGRAMS S S6 SA S8A SB S8B ADG66 -OF-6 DECODER A A A2 A3 EN Figure. ADG67 -OF-8 DECODER A A A2 EN Figure 2. D DA DB GENERAL DESCRIPTION The ADG66 and ADG67 are monolithic icmos analog multiplexers comprising of 6 single channels and eight differential channels, respectively. The ADG66 switches one of 6 inputs to a common output, as determined by the 4-bit binary address lines (A, A, A2, and A3). The ADG67 switches one of eight differential inputs to a common differential output, as determined by the 3-bit binary address lines (A, A, and A2). An EN input on both devices enables or disables the device. When disabled, all channels switch off. When enabled, each channel conducts equally well in both directions and has an input signal range that extends to the supplies. The ultralow on resistance and on-resistance flatness of these switches make them ideal solutions for data acquisition and gain switching applications where low distortion is critical. icmos construction ensures ultralow power dissipation, making the parts ideally suited for portable and batterypowered instruments. PRODUCT HIGHLIGHTS. 7.5 Ω maximum on resistance over temperature. 2. Minimum distortion: THD + N =.4% 3. 3 V logic-compatible digital inputs: VINH = 2. V, VINL =.8 V. 4. No VL logic power supply required. Rev. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA , U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 TABLE OF CONTENTS Features... Applications... Functional Block Diagrams... General Description... Product Highlights... Revision History... 2 Specifications... 3 ±5 V Dual Supply V Single Supply V Single Supply V Single Supply... 6 Continuous Current per Channel, S or D...7 Absolute Maximum Ratings...8 Thermal Resistance...8 ESD Caution...8 Pin Configurations and Function Descriptions...9 Typical Performance Characteristics... 3 Test Circuits... 7 Terminology... 2 Outline Dimensions... 2 Ordering Guide... 2 REVISION HISTORY /9 Revision : Initial Version Rev. Page 2 of 24

3 SPECIFICATIONS ±5 V DUAL SUPPLY VDD = +5 V ± %, VSS = 5 V ± %, GND = V, unless otherwise noted. Table. Parameter 25 C 4 C to +85 C 4 C to +25 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range VDD to VSS V On Resistance (RON) 4.5 Ω typ VS = ±4.5 V, IS = ma; see Figure Ω max VDD = ±4.5 V, VSS = ±4.5 V On Resistance Match Between Channels ( RON).2 Ω typ VS = ±4.5 V, IS = ma Ω max On Resistance Flatness (RFLAT(ON)). Ω typ VS = ±4.5 V, IS = ma Ω max LEAKAGE CURRENTS VDD = +5.5 V, VSS = 5.5 V Source Off Leakage, IS (Off) ±.2 na typ VS = ±4.5 V, VD = 4.5 V; see Figure 27 ±.5 ±.5 ±3 na max Drain Off Leakage, ID (Off) ±.5 na typ VS = ±4.5 V, VD = 4.5 V; see Figure 27 ADG66 ±.2 ±3 ±25 na max Channel On Leakage, ID, IS (On) ±. na typ VS = VD = ±4.5 V; see Figure 28 ±.3 ±3 ±25 na max DIGITAL INPUTS Input High Voltage, VINH 2. V min Input Low Voltage, VINL.8 V max Input Current, IINL or IINH ±.3 μa typ VIN = VGND or VDD ±. μa max Digital Input Capacitance, CIN 4 pf typ DYNAMIC CHARACTERISTICS Transition Time, ttransition 75 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 2.5 V; see Figure 29 ton (EN) 32 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 2.5 V; see Figure 3 toff (EN) 24 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 2.5 V; see Figure 3 Break-Before-Make Time Delay, tbbm 42 ns typ RL = 3 Ω, CL = 35 pf 5 ns min VS = VS2 = 2.5 V; see Figure 3 Charge Injection 27 pc typ VS = V, RS = Ω, CL = nf; see Figure 32 Off Isolation 62 db typ RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 33 Channel-to-Channel Crosstalk 62 db typ RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 35 Total Harmonic Distortion + Noise (THD + N).4 % typ RL = Ω, 5 V p-p, f = 2 Hz to 2 khz; see Figure 36 3 db Bandwidth RL = 5 Ω, CL = 5 pf; see Figure 34 ADG66 2 MHz typ ADG67 37 MHz typ CS (Off) 8 pf typ VS = V, f = MHz CD (Off) ADG pf typ VS = V, f = MHz ADG67 23 pf typ VS = V, f = MHz CD, CS (On) ADG66 27 pf typ VS = V, f = MHz ADG67 46 pf typ VS = V, f = MHz POWER REQUIREMENTS VDD = +5.5 V, VSS = 5.5 V IDD. μa typ Digital inputs = V or VDD. μa max VDD/VSS ±3.3/±8 V min/max Guaranteed by design, not subject to production test. Rev. Page 3 of 24

4 2 V SINGLE SUPPLY VDD = 2 V ± %, VSS = V, GND = V, unless otherwise noted. Table 2. Parameter 25 C 4 C to +85 C 4 C to +25 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V to VDD V On Resistance (RON) 4 Ω typ VS = V to V, IS = ma; see Figure Ω max VDD =.8 V, VSS = V On Resistance Match Between Channels ( RON).2 Ω typ VS = V, IS = ma Ω max On Resistance Flatness (RFLAT(ON)) Ω typ VS = V to V, IS = ma Ω max LEAKAGE CURRENTS VDD = 3.2 V, VSS = V Source Off Leakage, IS (Off) ±.2 na typ VS = V/ V, VD = V/ V; see Figure 27 ±.5 ±.5 ±3 na max Drain Off Leakage, ID (Off) ±.5 na typ VS = V/ V, VD = V/ V; see Figure 27 ADG66 ±.2 ±3 ±25 na max Channel On Leakage, ID, IS (On) ±. na typ VS = VD = V or V; see Figure 28 ±.3 ±3 ±25 na max DIGITAL INPUTS Input High Voltage, VINH 2. V min Input Low Voltage, VINL.8 V max Input Current, IINL or IINH ±.3 μa typ VIN = VGND or VDD ±. μa max Digital Input Capacitance, CIN 4 pf typ DYNAMIC CHARACTERISTICS Transition Time, ttransition 43 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 8 V; see Figure 29 ton (EN) 8 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 8 V; see Figure 3 toff (EN) 9 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 8 V; see Figure 3 Break-Before-Make Time Delay, tbbm 4 ns typ RL = 3 Ω, CL = 35 pf 5 ns min VS = VS2 = 8 V; see Figure 3 Charge Injection 33 pc typ VS = 6 V, RS = Ω, CL = nf; see Figure 32 Off Isolation 62 db typ RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 33 Channel-to-Channel Crosstalk 62 db typ RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 35 Total Harmonic Distortion + Noise (THD + N).4 % typ RL = Ω, 5 V p-p, f = 2 Hz to 2 khz; see Figure 36 3 db Bandwidth RL = 5 Ω, CL = 5 pf; see Figure 34 ADG66 22 MHz typ ADG67 38 MHz typ CS (Off) 8 pf typ VS = 6 V, f = MHz CD (Off) ADG66 24 pf typ VS = 6 V, f = MHz ADG67 2 pf typ VS = 6 V, f = MHz CD, CS (On) ADG pf typ VS = 6 V, f = MHz ADG67 43 pf typ VS = 6 V, f = MHz POWER REQUIREMENTS VDD = 2 V IDD. μa typ Digital inputs = V or VDD. μa max ADG66 3 μa typ Digital inputs = 5 V 48 μa max ADG67 37 μa typ Digital inputs = 5 V 6 μa max VDD 3.3/6 V min/max Guaranteed by design, not subject to production test. Rev. Page 4 of 24

5 5 V SINGLE SUPPLY VDD = 5 V ± %, VSS = V, GND = V, unless otherwise noted. Table 3. Parameter 25 C 4 C to +85 C 4 C to +25 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V to VDD V On Resistance (RON) 8.5 Ω typ VS = V to 4.5 V, IS = ma; see Figure Ω max VDD = 4.5 V, VSS = V On Resistance Match Between Channels ( RON).3 Ω typ VS = V to 4.5 V, IS = ma.8..2 Ω max On Resistance Flatness (RFLAT(ON)).8 Ω typ VS = V to 4.5 V, IS = ma Ω max LEAKAGE CURRENTS VDD = 5.5 V, VSS = V Source Off Leakage, IS (Off) ±. na typ VS = V/4.5 V, VD = 4.5 V/ V; see Figure 27 ±.5 ±.5 ±3 na max Drain Off Leakage, ID (Off) ±.2 na typ VS = V/4.5 V, VD = 4.5 V/ V; see Figure 27 ADG66 ±.2 ±3 ±25 na max Channel On Leakage, ID, IS (On) ±.5 na typ VS = VD = V or 4.5 V; see Figure 28 ±.3 ±3 ±25 na max DIGITAL INPUTS Input High Voltage, VINH 2. V min Input Low Voltage, VINL.8 V max Input Current, IINL or IINH ±.3 μa typ VIN = VGND or VDD ±. μa max Digital Input Capacitance, CIN 4 pf typ DYNAMIC CHARACTERISTICS Transition Time, ttransition 22 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 2.5 V; see Figure 29 ton (EN) 6 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 2.5 V; see Figure 3 toff (EN) 54 ns typ RL = 3 Ω, CL = 35 pf ns max VS = 2.5 V; see Figure 3 Break-Before-Make Time Delay, tbbm 45 ns typ RL = 3 Ω, CL = 35 pf 5 ns min VS = VS2 = 2.5 V; see Figure 3 Charge Injection 2 pc typ VS = 2.5 V, RS = Ω, CL = nf; see Figure 32 Off Isolation 62 db typ RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 33 Channel-to-Channel Crosstalk 62 db typ RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 35 Total Harmonic Distortion + Noise (THD + N).35 % typ RL = Ω, f = 2 Hz to 2 khz, VS = 3.5 V p-p; see Figure 36 3 db Bandwidth RL = 5 Ω, CL = 5 pf; see Figure 34 ADG66 9 MHz typ ADG67 34 MHz typ CS (Off) 2 pf typ VS = 2.5 V, f = MHz CD (Off) ADG66 27 pf typ VS = 2.5 V, f = MHz ADG67 37 pf typ VS = 2.5 V, f = MHz CD, CS (On) ADG66 3 pf typ VS = 2.5 V, f = MHz ADG67 6 pf typ VS = 2.5 V, f = MHz POWER REQUIREMENTS VDD = 5.5 V IDD. μa typ Digital inputs = V or VDD. μa max VDD 3.3/6 V min/max Guaranteed by design, not subject to production test. Rev. Page 5 of 24

6 3.3 V SINGLE SUPPLY VDD = 3.3 V, VSS = V, GND = V, unless otherwise noted. Table 4. Parameter 25 C 4 C to +85 C 4 C to +25 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V to VDD V On Resistance (RON) Ω typ VS = V to VDD, IS = ma; see Figure 26 VDD = 3.3 V, VSS = V On Resistance Match Between Channels ( RON) Ω typ VS = V to VDD, IS = ma On Resistance Flatness (RFLAT(ON)) Ω typ VS = V to VDD, IS = ma LEAKAGE CURRENTS VDD = 3.6 V, VSS = V Source Off Leakage, IS (Off) ±. na typ VS =.6 V/3 V, VD = 3 V/.6 V; see Figure 27 ±.5 ±.5 ±3 na max Drain Off Leakage, ID (Off) ±.2 na typ VS =.6 V/3 V, VD = 3 V/.6 V; see Figure 27 ADG66 ±.2 ±3 ±25 na max Channel On Leakage, ID, IS (On) ±.5 na typ VS = VD =.6 V or 3 V; see Figure 28 ±.3 ±3 ±25 na max DIGITAL INPUTS Input High Voltage, VINH 2. V min Input Low Voltage, VINL.8 V max Input Current, IINL or IINH ±.3 μa typ VIN = VGND or VDD ±. μa max Digital Input Capacitance, CIN 4 pf typ DYNAMIC CHARACTERISTICS Transition Time, ttransition 353 ns typ RL = 3 Ω, CL = 35 pf ns max VS =.5 V; see Figure 29 ton (EN) 263 ns typ RL = 3 Ω, CL = 35 pf ns max VS =.5 V; see Figure 3 toff (EN) 262 ns typ RL = 3 Ω, CL = 35 pf ns max VS =.5 V; see Figure 3 Break-Before-Make Time Delay, tbbm 74 ns typ RL = 3 Ω, CL = 35 pf 5 ns min VS = VS2 =.5 V; see Figure 3 Charge Injection 6 pc typ VS =.5 V, RS = Ω, CL = nf; see Figure 32 Off Isolation 62 db typ RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 33 Channel-to-Channel Crosstalk 62 db typ RL = 5 Ω, CL = 5 pf, f = MHz; see Figure 35 Total Harmonic Distortion + Noise (THD + N).6 % typ RL = Ω, f = 2 Hz to 2 khz, VS = 2 V p-p; see Figure 36 3 db Bandwidth RL = 5 Ω, CL = 5 pf; see Figure 34 ADG66 7 MHz typ ADG67 3 MHz typ CS (Off) 22 pf typ VS =.5 V, f = MHz CD (Off) ADG66 29 pf typ VS =.5 V, f = MHz ADG67 45 pf typ VS =.5 V, f = MHz CD, CS (On) ADG66 35 pf typ VS =.5 V, f = MHz ADG67 68 pf typ VS =.5 V, f = MHz POWER REQUIREMENTS VDD = 3.6 V IDD. μa typ Digital inputs = V or VDD. μa max VDD 3.3/6 V min/max Guaranteed by design, not subject to production test. Rev. Page 6 of 24

7 CONTINUOUS CURRENT PER CHANNEL, S OR D Table 5. ADG66 Parameter 25 C 85 C 25 C Unit CONTINUOUS CURRENT, S OR D VDD = +5 V, VSS = 5 V TSSOP (θja = 97.9 C/W) ma maximum LFCSP (θja = 46 C/W) ma maximum VDD = 2 V, VSS = V TSSOP (θja = 97.9 C/W) ma maximum LFCSP (θja = 46 C/W) ma maximum VDD = 5 V, VSS = V TSSOP (θja = 97.9 C/W) ma maximum LFCSP (θja = 46 C/W) ma maximum VDD = 3.3 V, VSS = V TSSOP (θja = 97.9 C/W) ma maximum LFCSP (θja = 46 C/W) ma maximum Table 6. ADG67 Parameter 25 C 85 C 25 C Unit CONTINUOUS CURRENT, S OR D VDD = +5 V, VSS = 5 V TSSOP (θja = 97.9 C/W) ma maximum LFCSP (θja = 46 C/W) ma maximum VDD = 2 V, VSS = V TSSOP (θja = 97.9 C/W) ma maximum LFCSP (θja = 46 C/W) ma maximum VDD = 5 V, VSS = V TSSOP (θja = 97.9 C/W) ma maximum LFCSP (θja = 46 C/W) ma maximum VDD = 3.3 V, VSS = V TSSOP (θja = 97.9 C/W) ma maximum LFCSP (θja = 46 C/W) ma maximum Rev. Page 7 of 24

8 ABSOLUTE MAXIMUM RATINGS TA = 25 C, unless otherwise noted. Table 7. Parameter Rating VDD to VSS 8 V VDD to GND.3 V to +8 V VSS to GND +.3 V to 8 V Analog Inputs VSS.3 V to VDD +.3 V or 3 ma, whichever occurs first Digital Inputs 2 GND.3 V to VDD +.3 V or 3 ma, whichever occurs first Peak Current, S or D. A (pulsed at ms, % duty cycle maximum) Continuous Current, S or D 3 Data + 5% Operating Temperature Range Industrial (B Version) 4 C to +25 C Storage Temperature Range 65 C to +5 C Junction Temperature 5 C Reflow Soldering Peak 26 C Temperature, Pb Free THERMAL RESISTANCE θja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 8. Thermal Resistance Package Type θja θjc Unit 28-Lead TSSOP C/W 32-Lead LFCSP_VQ 46 C/W ESD CAUTION Overvoltages at IN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given. 2 Overvoltages at the Ax, EN, Sx, or Dx pins are clamped by internal diodes. Current should be limited to the maximum ratings given. 3 See Table 5. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. Rev. Page 8 of 24

9 GND A3 A2 NC NC A A EN ADG66/ADG67 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS NC NC S S5 5 S4 6 S3 7 S2 8 S 9 S S9 GND 2 NC 3 A3 4 ADG66 TOP VIEW (Not to Scale) NC = NO CONNECT 28 D 27 V SS 26 S8 25 S7 24 S6 23 S5 22 S4 2 S3 2 S2 9 S 8 EN 7 A 6 A 5 A2 Figure 3. ADG66 TSSOP Pin Configuration S6 S5 2 S4 3 S3 4 S2 5 S 6 S 7 S NC 3 3 NC 29 D 28 NC 27 NC 26 NC 25 V SS PIN INDICATOR ADG66 TOP VIEW (Not to Scale) 24 S8 23 S7 22 S6 2 S5 2 S4 9 S3 8 S2 7 S NOTES. NC = NO CONNECT. 2. EXPOSED PAD TIED TO SUBSTRATE, V SS. Figure 4. ADG66 LFCSP_VQ Pin Configuration Table 9. ADG66 Pin Function Descriptions Pin No. TSSOP LFCSP_VQ Mnemonic Description 3 VDD Most Positive Power Supply Potential. 2, 3, 3 2, 3, 26, NC No Connect. 27, 28, 3, 32 4 S6 Source Terminal 6. This pin can be an input or an output. 5 2 S5 Source Terminal 5. This pin can be an input or an output. 6 3 S4 Source Terminal 4. This pin can be an input or an output. 7 4 S3 Source Terminal 3. This pin can be an input or an output. 8 5 S2 Source Terminal 2. This pin can be an input or an output. 9 6 S Source Terminal. This pin can be an input or an output. 7 S Source Terminal. This pin can be an input or an output. 8 S9 Source Terminal 9. This pin can be an input or an output. 2 9 GND Ground ( V) Reference. 4 A3 Logic Control Input. 5 A2 Logic Control Input. 6 4 A Logic Control Input. 7 5 A Logic Control Input. 8 6 EN Active High Digital Input. When this pin is low, the device is disabled and all switches are turned off. When this pin is high, the Ax logic inputs determine which switch is turned on. 9 7 S Source Terminal. This pin can be an input or an output. 2 8 S2 Source Terminal 2. This pin can be an input or an output. 2 9 S3 Source Terminal 3. This pin can be an input or an output S4 Source Terminal 4. This pin can be an input or an output S5 Source Terminal 5. This pin can be an input or an output S6 Source Terminal 6. This pin can be an input or an output S7 Source Terminal 7. This pin can be an input or an output S8 Source Terminal 8. This pin can be an input or an output VSS Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground D Drain Terminal. This pin can be an input or an output. EPAD Exposed Pad The exposed pad is connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS. Rev. Page 9 of 24

10 Table. ADG66 Truth Table A3 A2 A A EN On Switch X X X X None X = don t care. Rev. Page of 24

11 GND A2 NC NC NC A A EN ADG66/ADG67 DB NC S8B S7B 5 S6B 6 S5B 7 S4B 8 S3B 9 S2B SB GND 2 NC 3 NC 4 ADG67 TOP VIEW (Not to Scale) NC = NO CONNECT 28 DA 27 V SS 26 S8A 25 S7A 24 S6A 23 S5A 22 S4A 2 S3A 2 S2A 9 SA 8 EN 7 A 6 A 5 A2 Figure 5. ADG67 TSSOP Pin Configuration S8B S7B 2 S6B 3 S5B 4 S4B 5 S3B 6 S2B 7 SB 8 32 NC 3 DB 3 NC NC 27 DA 26 NC 25 V SS PIN INDICATOR ADG67 TOP VIEW (Not to Scale) 24 S8A 23 S7A 22 S6A 2 S5A 2 S4A 9 S3A 8 S2A 7 SA NOTES. NC = NO CONNECT. 2. EXPOSED PAD TIED TO SUBSTRATE, V SS. Figure 6. ADG67 LFCSP_VQ Pin Configuration Table. ADG67 Pin Function Descriptions Pin No. TSSOP LFCSP_VQ Mnemonic Description 29 VDD Most Positive Power Supply Potential. 2 3 DB Drain Terminal B. This pin can be an input or an output. 3, 3, 4, 2, 3, 26, NC No Connect. 28, 3, 32 4 S8B Source Terminal 8B. This pin can be an input or an output. 5 2 S7B Source Terminal 7B. This pin can be an input or an output. 6 3 S6B Source Terminal 6B. This pin can be an input or an output. 7 4 S5B Source Terminal 5B. This pin can be an input or an output. 8 5 S4B Source Terminal 4B. This pin can be an input or an output. 9 6 S3B Source Terminal 3B. This pin can be an input or an output. 7 S2B Source Terminal 2B. This pin can be an input or an output. 8 SB Source Terminal B. This pin can be an input or an output. 2 9 GND Ground ( V) Reference. 5 A2 Logic Control Input. 6 4 A Logic Control Input. 7 5 A Logic Control Input. 8 6 EN Active High Digital Input. When this pin is low, the device is disabled and all switches are turned off. When this pin is high, the Ax logic inputs determine which switch is turned on. 9 7 SA Source Terminal A. This pin can be an input or an output. 2 8 S2A Source Terminal 2A. This pin can be an input or an output. 2 9 S3A Source Terminal 3A. This pin can be an input or an output S4A Source Terminal 4A. This pin can be an input or an output S5A Source Terminal 5A. This pin can be an input or an output S6A Source Terminal 6A. This pin can be an input or an output S7A Source Terminal 7A. This pin can be an input or an output S8A Source Terminal 8A. This pin can be an input or an output VSS Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground DA Drain Terminal A. This pin can be an input or an output. EPAD Exposed Pad The exposed pad is connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS. Rev. Page of 24

12 Table 2. ADG67 Truth Table A2 A A EN On Switch Pair X X XX None X = don t care. Rev. Page 2 of 24

13 TYPICAL PERFORMANCE CHARACTERISTICS 7 T A = 25 C = 2V V SS = V ON RESISTANCE (Ω) = +3.3V V SS = 3.3V = +5V V SS = 5V = +8V V SS = 8V ON RESISTANCE (Ω) T A = +25 C T A = +85 C T A = +25 C T A = 4 C SOURCE OR DRAIN VOLTAGE (V) Figure 7. On Resistance as a Function of VD (VS) for Dual Supply SOURCE OR DRAIN VOLTAGE (V) Figure. On Resistance as a Function of VD (VS) for Different Temperatures, 2 V Single Supply ON RESISTANCE (Ω) = 5V V SS = V = 3.3V V SS = V = 2V V SS = V T A = 25 C = 6V V SS = V ON RESISTANCE (Ω) T A = +25 C T A = +85 C T A = +25 C T A = 4 C SOURCE OR DRAIN VOLTAGE (V) Figure 8. On Resistance as a Function of VD (VS) for Single Supply = 5V V SS = V SOURCE OR DRAIN VOLTAGE (V) Figure. On Resistance as a Function of VD (VS) for Different Temperatures, 5 V Single Supply = +5V V SS = 5V 8 6 = 3.3V V SS = V ON RESISTANCE (Ω) T A = +25 C T A = +85 C T A = +25 C T A = 4 C ON RESISTANCE (Ω) T A = +25 C T A = +85 C T A = +25 C T A = 4 C SOURCE OR DRAIN VOLTAGE (V) Figure 9. On Resistance as a Function of VD (VS) for Different Temperatures, ±5 V Dual Supply SOURCE OR DRAIN VOLTAGE (V) Figure 2. On Resistance as a Function of VD (VS) for Different Temperatures, 3.3 V Single Supply Rev. Page 3 of 24

14 LEAKAGE CURRENT (na) = +5V V SS = 5V V BIAS = +4.5V/ 4.5V I D (OFF) + I D (ON) + + I S (OFF) + I S (OFF) + I D (ON) I D (OFF) + LEAKAGE CURRENT (na) = 3.3V V SS = V V BIAS =.6V/3V I D, I S (ON) + + I D (OFF) + I D, I S (ON) I S (OFF) + I D (OFF) + I S (OFF) TEMPERATURE ( C) Figure 3. Leakage Currents as a Function of Temperature, ±5 V Dual Supply TEMPERATURE ( C) Figure 6. Leakage Currents as a Function of Temperature, 3.3 V Single Supply LEAKAGE CURRENT (na) = 2V V SS = V V BIAS = V/V I D (ON) + + I D (OFF) + I S (OFF) + I S (OFF) + I D (ON) I D (OFF) TEMPERATURE ( C) Figure 4. Leakage Currents as a Function of Temperature, 2 V Single Supply I DD (µa) = +2V V SS = V = +5V V SS = 5V 2 = +5V V SS = V = +3.3V V SS = V LOGIC LEVEL (V) Figure 7. IDD vs. Logic Level I DD = ALL LOGIC HIGH T A = 25 C LEAKAGE CURRENT (na) = 5V V SS = V V BIAS = V/4.5V I D, I S (ON) + + I D (OFF) + I D, I S (ON) I S (OFF) + I S (OFF) + I S (OFF) + CHARGE INJECTION (pc) T A = 25 C = +5V V SS = 5V = +2V V SS = V = +5V V SS = V TEMPERATURE ( C) = +3.3V V SS = V V S (V) Figure 5. Leakage Currents as a Function of Temperature, 5 V Single Supply Figure 8. Charge Injection vs. Source Voltage Rev. Page 4 of 24

15 T A = 25 C = +3.3V, V SS = V 2 T A = 25 C = +5V V SS = 5V TIME (ns) = +5V, V SS = V = +2V, V SS = V = +5V, V SS = 5V ISOLATOIN (db) TEMPERATURE ( C) Figure 9. Transition Time vs. Temperature k k M M M 5M FREQUENCY (Hz) Figure 2. ADG66 Crosstalk vs. Frequency T A = 25 C = +5V V SS = 5V 2 T A = 25 C = +5V V SS = 5V OFF ISOLATOIN (db) CROSSTALK (db) ADJACENT CHANNEL NONADJACENT CHANNEL 2 3k k M M M 5M FREQUENCY (Hz) Figure 2. Off Isolation vs. Frequency k k M M M 5M FREQUENCY (Hz) Figure 22. ADG67 Crosstalk vs. Frequency Rev. Page 5 of 24

16 INSERTION LOSS (db) ACPSRR (db) T A = 25 C = +5V V SS = 5V NO DECOUPLING CAPACITORS 5 T A = 25 C = +5V V SS = 5V 6 3k k M M 4M FREQUENCY (Hz) Figure 23. ADG66 On Response vs. Frequency DECOUPLING CAPACITORS ON SUPPLIES k k k M M M FREQUENCY (Hz) Figure 25. ACPSRR vs. Frequency R L = Ω T A = 25 C.5 = 3.3V, V S = 2V p-p THD + N (%).4.3 = 5V, V S = 3.5V p-p.2. = 2V, V S = 5V p-p = 5V, V SS = 5V, V S =5V p-p 5k k 5k 2k FREQUENCY (Hz) Figure 24. THD + N vs. Frequency Rev. Page 6 of 24

17 TEST CIRCUITS V I D (ON) S D NC S D A I DS V S NC = NO CONNECT V D Figure 26. On Resistance Figure 28. On Leakage I S (OFF) A S D I D (OFF) A V S V D Figure 27. Off Leakage V SS 3V ADDRESS DRIVE (V IN ) V 5% 5% t r < 2ns t f < 2ns V IN 5Ω A A A2 V SS S S2 TO S5 V S t TRANSITION t TRANSITION A3 S6 V S6 OUTPUT 9% ADG66 2.4V EN D OUTPUT 9% GND 3Ω 35pF SIMILAR CONNECTION FOR ADG Figure 29. Address to Output Switching Times, ttransition V SS 3V ADDRESS DRIVE (V IN ) V V IN 5Ω A A A2 V SS S S2 TO S5 V S A3 S6 OUTPUT 8% 8% ADG66 2.4V EN D OUTPUT GND 3Ω 35pF t BBM SIMILAR CONNECTION FOR ADG Figure 3. Break-Before-Make Delay, tbbm Rev. Page 7 of 24

18 V SS 3V V SS ENABLE DRIVE (V IN ) V 5% 5% A A A2 A3 S S2 TO S6 V S OUTPUT t ON (EN) t OFF (EN).9V OUT.9V OUT V IN 5Ω ADG66 EN D GND OUTPUT 3Ω 35pF Figure 3. Enable Delay, ton (EN), toff (EN) SIMILAR CONNECTION FOR ADG V SS 3V A A V SS V IN A2 A3 ADG66 V OUT Q INJ = C L ΔV OUT ΔV OUT R S V S V IN S EN GND D V OUT C L nf SIMILAR CONNECTION FOR ADG67. Figure 32. Charge Injection Rev. Page 8 of 24

19 DD V SS.µFV.µF DD V SS.µFV.µF S D V SS 5Ω NETWORK ANALYZER 5Ω V S NETWORK ANALYZER V OUT R L 5Ω S S2 V SS D R 5Ω GND V OUT R L 5Ω V S GND OFF ISOLATION = 2 log V OUT V S CHANNEL-TO-CHANNEL CROSSTALK = 2 log V OUT V S Figure 33. Off Isolation Figure 35. Channel-to-Channel Crosstalk DD V SS.µFV.µF V SS NETWORK ANALYZER DD V SS.µFV.µF AUDIO PRECISION S 5Ω V SS R S GND D V S V OUT R L 5Ω V OUT WITH SWITCH INSERTION LOSS = 2 log V OUT WITHOUT SWITCH V IN IN S GND D R L kω V OUT V S V p-p Figure 34. Bandwidth Figure 36. THD + N Rev. Page 9 of 24

20 TERMINOLOGY RON Ohmic resistance between the D and S terminals. ΔRON Difference between the RON of any two channels. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured. IS (Off) Source leakage current when the switch is off. ID (Off) Drain leakage current when the switch is off. ID, IS (On) Channel leakage current when the switch is on. VD, VS Analog voltage on Terminal D and Terminal S. CS (Off) Channel input capacitance for the off condition. CD (Off) Channel output capacitance for the off condition. CD, CS (On) On switch capacitance. CIN Digital input capacitance. ton (EN) Delay time between the 5% and 9% points of the digital input and the switch on condition. toff (EN) Delay time between the 5% and 9% points of the digital input and the switch off condition. ttransition Delay time between the 5% and 9% points of the digital inputs and the switch on condition when switching from one address state to another. tbbm Off time measured between the 8% points of the switches when switching from one address state to another. VINL Maximum input voltage for Logic. VINH Minimum input voltage for Logic. IINL, IINH Input current of the digital input. IDD Positive supply current. ISS Negative supply current. Off Isolation A measure of unwanted signal coupling through an off channel. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Bandwidth The frequency at which the output is attenuated by 3 db. On Response The frequency response of the on switch. THD + N The ratio of the harmonic amplitude plus noise of the signal to the fundamental. AC Power Supply Rejection Ratio (ACPSRR) Measures the ability of a part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of.62 V p-p. The ratio of the amplitude of signal on the output to the amplitude of the modulation is the ACPSRR. Rev. Page 2 of 24

21 OUTLINE DIMENSIONS BSC PIN.5.5 COPLANARITY..65 BSC MAX SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-53-AE Figure Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters PIN INDICATOR MAX SEATING PLANE 5. BSC SQ TOP VIEW.8 MAX.65 TYP BSC SQ.2 REF.5 MAX.2 NOM.6 MAX.5 BSC COPLANARITY.8 COMPLIANT TO JEDEC STANDARDS MO-22-VHHD-2 Figure Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters MAX EXPOSED PAD (BOTTOM VIEW) 3.5 REF PIN INDICATOR SQ MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. ORDERING GUIDE Model Temperature Range Package Description Package Option ADG66BRUZ 4 C to +25 C 28-Lead Thin Shrink Small Outline Package [TSSOP] RU-28 ADG66BRUZ-REEL7 4 C to +25 C 28-Lead Thin Shrink Small Outline Package [TSSOP] RU-28 ADG66BCPZ-REEL7 4 C to +25 C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-2 ADG67BRUZ 4 C to +25 C 28-Lead Thin Shrink Small Outline Package [TSSOP] RU-28 ADG67BRUZ-REEL7 4 C to +25 C 28-Lead Thin Shrink Small Outline Package [TSSOP] RU-28 ADG67BCPZ-REEL7 4 C to +25 C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-2 Z = RoHS Compliant Part. 78-A Rev. Page 2 of 24

22 NOTES Rev. Page 22 of 24

23 NOTES Rev. Page 23 of 24

24 NOTES 29 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D8489--/9() Rev. Page 24 of 24