RT9198/A. 300mA, Low Noise, Ultra-Fast CMOS LDO Regulator. General Description. Ordering Information RT9198/A- Features. Marking Information

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1 RT9198/A 3mA, Low Noise, Ultra-Fast CMOS LDO Regulator General Description The RT9198/A is designed for portable RF and wireless applications with demanding performance and space requirements. The RT9198/A performance is optimized for battery-powered systems to deliver ultra low noise and low quiescent current. Regulator ground current increases only slightly in dropout, further prolonging the battery life. The RT9198/A also works with low-esr ceramic capacitors, reducing the amount of board space necessary for power applications, critical in hand-held wireless devices. The RT9198/A consumes less than.1μa in shutdown mode and has fast turn-on time less than μs. The other features include ultra low dropout voltage, high output accuracy, current limiting protection, and high ripple rejection ratio. Available in the SOT-23-3, SOT-23-, TSOT-23-3, TSOT-23-, SC-7-, SC-82, MSOP-8 and WDFN-6L 2x2 packages, the RT9198/A also offers a range from 1.V to.v with.1v per step. Features Low-Noise for RF Application Fast Response in Line/Load Transient Quick Start-Up (Typically μs) <.1μA Standby Current When Shutdown Low Dropout : 3mA Wide Operating Voltage Ranges : 2.V to.v TTL-Logic-Controlled Shutdown Input Low Temperature Coefficient Current Limiting Protection Thermal Shutdown Protection Only 1μF Output Capacitor Required for Stability High Power Supply Rejection Ratio Custom Voltage Available RoHS Compliant and 1% Lead (Pb)-Free Applications CDMA/GSM Cellular Handsets Battery-Powered Equipment Laptop, Palmtops, Notebook Computers Hand-Held Instruments PCMCIA Cards Portable Information Appliances Ordering Information RT9198/A- Note : Richtek products are : Marking Information Package Type U : SC-7- UR : SC-7- (R-Type) Y : SC-82 V : SOT-23-3 B : SOT- 23- BR : SOT- 23- (R-Type) BG : SOT- 23- (G-Type) J3 : TSOT J : TSOT- 23- JR : TSOT- 23- (R-Type) JG : TSOT- 23- (G-Type) F : MSOP-8 QW : WDFN-6L 2x2 (W-Type) Lead Plating System P : Pb Free G : Green (Halogen Free and Pb Free) Output Voltage 1 : 1.V 16 : 1.6V : 49 : 4.9V :.V 1H : 1.8V 2H : 2.8V 4G : 4.7V Chip Enable Function (Active Low) Chip Enable Function (Active High) RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-2. Suitable for use in SnPb or Pb-free soldering processes. For marking information, contact our sales representative directly or through a Richtek distributor located in your area. 1

2 Pin Configurations (TOP VIEW) NC NC EN/EN EN/EN NC EN/EN TSOT-23-/SOT-23-/ TSOT-23-/SOT-23-/ TSOT-23-/ TSOT-23-3/ SC-7- (R-Type) SC-7- SOT-23-(G-Type) SOT-23-3 EN/EN NC NC NC NC EN/EN NC NC 4 EN/EN 3 2 WDFN-6L 2x2 MSOP-8 SC-82 Typical Application Circuit RT9198 V IN C IN 1uF C OUT 1uF V OUT Chip Enable On Off EN RT9198A V IN C IN 1uF C OUT 1uF V OUT Chip Enable Off On EN 2

3 Functional Pin Description Pin Name EN EN NC, Exposed Pad Pin Function Chip Enable (Active High). Note that this pin is high impedance. There should be a pull low 1k resistor connected to when the control signal is floating. Chip Enable (Active Low). Note that this pin is high impedance. There should be a pull high 1k resistor connected to when the control signal is floating. No Internal Connection. Ground. The exposed pad must be soldered to a large PCB and connected to for maximum power dissipation. Output Voltage. Input Voltage. Function Block Diagram EN/EN V REF Shutdown and Logic Control - + Error Amplifier MOS Driver Current-Limit and Thermal Protection 3

4 Absolute Maximum Ratings (Note 1) Supply Input Voltage V Power Dissipation, P T A = 2 C TSOT-23-3/TSOT-23-/SOT-23-3/SOT mW SC-7-, SC mW MSOP mW WDFN-6L 2x mW Package Thermal Resistance (Note 2) TSOT-23-3/TSOT-23-/SOT-23-3/SOT-23-, θ JA C/W TSOT-23-3/TSOT-23-/SOT-23-3/SOT-23-, θ JC C/W SC-7-, SC-82, θ JA C/W MSOP-8, θ JA C/W WDFN-6L 2x2, θ JA C/W WDFN-6L 2x2, θ JC C/W Junction Temperature C Lead Temperature (Soldering, 1 sec.) C Storage Temperature Range C to 1 C ESD Susceptibility (Note 3) HBM (Human Body Model) kV MM (Machine Model) V Recommended Operating Conditions (Note 4) Supply Input Voltage V to.v EN Input Voltage V to.v Junction Temperature Range C to 12 C Ambient Temperature Range C to 8 C Electrical Characteristics (V IN = + 1V, CIN = COUT = 1μF, T A = 2 C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Output Voltage Accuracy V OUT I OUT = 1mA % Current Limit I LIM R LOAD = ma Quiescent Current I Q Dropout Voltage (Note ) V DROP RT9198, V EN 1.2V, I OUT = ma RT9198A, V EN.4V, I OUT = ma A I OUT = 2mA I OUT = 3mA mv Line Regulation V LINE V IN = (V OUT + 1V) to.v, I OUT = 1mA % Load Regulation V LOAD 1mA < I OUT < 3mA % Shutdown Current I SHDN RT9198, V EN =, Shutdown RT9198A, V EN = V IN, Shutdown A EN Input Bias Current I IBEN V EN = or V IN -- 1 na 4

5 EN Threshold Parameter Symbol Test Conditions Min Typ Max Unit Logic-Low Voltage Logic-High Voltage V IL V IH RT9198, V IN = 3V to.v, Shutdown RT9198A, V IN = 3V to.v, Enable RT9198, V IN = 3V to.v, Enable RT9198A, V IN = 3V to.v, Shutdown Power Supply f = 1Hz PSRR C Rejection Rate OUT = 1 F, I OUT = 1mA f = 1kHz Thermal Shutdown Temperature Thermal Shutdown Temperature Hysteresis T SD C T SD C Note 1. Stresses beyond those listed Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θ JA is measured at T A = 2 C on a low effective thermal conductivity single-layer test board per JEDEC 1-3. θjc is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note. The dropout voltage is defined as V IN -V OUT, which is measured when V OUT is V OUT(NORMAL) 1mV. V db

6 Typical Operating Characteristics 2 Output Voltage vs. Temperature = V 1 9 Quiesent Current vs. Temperature RT9198/A-1 = 3.3V Output Voltage (V) No Load Quiescent Current (ua) Temperature ( C) Temperature ( C) EN Pin Threshold Voltage (V) EN Pin Shutdown Threshold vs. Temperature RT9198/A-1 = 3.3V Temperature ( C) Current Limit (ma) Current Limit vs. Input Voltage RT9198/A Input Voltage (V) Dropout Voltage (mv) Dropout Voltage vs. Load Current RT9198/A-33 TJ = 12 C TJ = 2 C Load Current (A) TJ = -4 C PSRR (db) PSRR 2 = 2.V, X7R -2-4 ILOAD = 1mA -6 ILOAD = 1mA K 1 1K 1K 1 1M Frequency (khz) (Hz) 6

7 Line Transient Response Line Transient Response Input Voltage Deviation (V) 4 3 ILOAD = ma Input Voltage Deviation (V) 4 3 ILOAD = 2mA Output Voltage Deviation (mv) 2-2 Output Voltage Deviation (mv) - Time (1μs/Div) Time (1μs/Div) Load Transient Response Load Transient Response Load Current (ma) 1 = 3.3V = 1.V ILOAD= 1mA to ma Load Current (ma) 4 2 = 3.3V = 1.V ILOAD = 1mA to 2mA Output Voltage Deviation (mv) - Output Voltage Deviation (mv) - Time (1μs/Div) Time (1μs/Div) Start Up EN Pin Shutdown Response EN Pin Voltage (V) 1 RT , = V = 1.8V ILOAD = 1mA EN Pin Voltage (V) 1 RT , = V = 1.8V ILOAD = 1mA Output Voltage (V) 2 1 Output Voltage (V) 2 1 Time (1μs/Div) Time (1ms/Div) 7

8 Noise Noise = 4.V = 1.8V ILOAD = 1mA = 4.V = 1.8V No Load Noise (μv) -2 Noise (μv) Time (ms/div) f = 1Hz to 1kHz Time (ms/div) f = 1Hz to 1kHz 8

9 Applications Information Like any low-dropout regulator, the external capacitors used for the RT9198/A must be carefully selected for regulator stability and performance. Using a capacitor whose value is > 1μF on the RT9198/A input and the amount of capacitance can be increased without limit. The input capacitor must be located a distance of not more than. inch from the input pin of the IC and returned to a clean analog ground. Any good quality ceramic or tantalum can be used for this capacitor. The capacitor with larger value and lower ESR (equivalent series resistance) provides better PSRR and line-transient response. The output capacitor must meet both requirements for minimum amount of capacitance and ESR in all LDOs application. The RT9198/A is designed specifically to work with low ESR ceramic output capacitor in space-saving and performance consideration. Using a ceramic capacitor whose value is at least 1μF with ESR is more than 2mΩ on the RT9198/A output ensures stability. The RT9198/A still works well with output capacitor of other types due to the wide stable ESR range. Figure 1. shows the curves of allowable ESR range as a function of load current for various output capacitor values. Output capacitor of larger capacitance can reduce noise and improve load transient response, stability, and PSRR. The output capacitor should be located with in. inch from the V OUT pin of the RT9198/A and returned to a clean analog ground. Region of Stable C OUT ESR vs. Load Current 1. Instable 1. Enable Function The RT9198/A features an LDO regulator enable/disable function. To assure the RT9198 LDO regulator will switch on, the EN turn on control level must be greater than 1.2V. The RT9198 LDO regulator will go into shutdown mode when the voltage on the EN pin falls below.4v. For RT9198A, the EN turn on control level must be lower than.4v to assure the RT9198A LDO regulator switch on. The RT9198A LDO regulator will go into shutdown mode when the voltage on the EN pin is higher than 1.2 V. The RT9198A equips a quick-discharge function to protect the system. When the regulator is turned off by EN pin, the internal MOSFET between V OUT and will be turned on to discharge output voltage quickly. If the enable function is not needed in a specific application, it may be tied to / to keep the LDO regulator in a continuously on state. Thermal Considerations Thermal protection limits power dissipation in RT9198/A. When the operating junction temperature exceeds 16 C, the OTP circuit starts the thermal shutdown function and turns the pass element off. The pass element turns on again after the junction temperature cools by 3 C. For continuous operation, do not exceed absolute maximum operatiog junction temperature 12 C. The power dissipation definition in device is shown as following formula : P D = (V IN V OUT) x I OUT + V IN x I Q COUT ESR (Ω) Stable COUT = 1uF The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula :. RT9198/A-1xU COUT = 1μF, X7R Load Current (ma) Figure 1 Simulation Verify P D(MAX) = ( T J(MAX) - T A ) / θ JA Where T J(MAX) is the maximum operating junction temperature 12 C, T A is the ambient temperature and the θ JA is the junction to ambient thermal resistance. Instable 9

10 For recommended operating conditions specification, where T J(MAX) is the maximum junction temperature of the die (12 C) and T A is the maximum ambient temperature. The junction to ambient thermal resistance (θ JA is layout dependent) for TSOT-23-3/TSOT-23-/SOT-23-3/SOT-23- package is 2 C/W, SC-7- and SC-82 package is 333 C/W and WDFN-6L 2x2 package is 16 C/W on standard JEDEC 1-3 thermal test board. The maximum power dissipation at T A = 2 C can be calculated by following formula : P D(MAX) = (12 C 2 C)/2 = 4mW (TSOT-23-3/ TSOT-23-/SOT-23-3/SOT-23-) P D(MAX) = (12 C 2 C)/333 = 3mW (SC-7-/SC-82) P D(MAX) = (12 C 2 C) / 16 = 66mW (WDFN-6L 2x2) The maximum power dissipation depends on operating ambient temperature for fixed T J(MAX) and thermal resistance θ JA. The Figure 2. of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. Maximum Power Dissipation (mw) WDFN-6L 2x2 SC 7- SC-82 SOT-23-3/SOT-23- TSOT-23-3/TSOT Ambient Temperature ( C) Figure 2. Derating Curve for Packages 1

11 Outline Dimension D H L C B e A b A1 Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A A B b C D e H L SOT-23-3 Surface Mount Package 11

12 D H L C B b A A1 e Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A A B b C D e H L SOT-23- Surface Mount Package 12

13 D H L C B e A b A1 Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A A B b C D e H L TSOT-23-3 Surface Mount Package 13

14 D H L C B b A A1 e Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A A B b C D e H L TSOT-23- Surface Mount Package 14

15 D H L C B b A A1 e Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A A B b C D e.6.26 H L SC-7- Surface Mount Package 1

16 D e H L C B b b1 A e A1 Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A A B b b C D e H L SC-82 Surface Mount Package 16

17 D L E E1 e A b A1 A2 Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A A A b D e.6.26 E E L Lead MSOP Plastic Package 17

18 D D2 L E E2 1 SEE DETAIL A A A1 A3 e b DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A A A b D D E E e.6.26 L W-Type 6L DFN 2x2 Package Richtek Technology Corporation 14F, No. 8, Tai Yuen 1 st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)26789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. 18