CMOS Static RAM 1 Meg (128K x 8-Bit) IDT71024S
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1 CMOS Static RAM 1 Meg (128K x 8-Bit) IDT71024S Features 128K x 8 advanced high-speed CMOS static RAM Commercial (0 C to +70 C), Industrial ( 40 C to +85 C) Equal access and cycle times Commercial and Industrial: 12/15/20ns Two Chip Selects plus one Output Enable pin Bidirectional inputs and outputs directly TTL-compatible Low power consumption via chip deselect Available in 300 and 400 mil Plastic SOJ. Description The IDT71024 is a 1,048,576-bit high-speed static RAM organized as 128K x 8. It is fabricated using high-performance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for high-speed memory needs. The IDT71024 has an output enable pin which operates as fast as 6ns, with address access times as fast as 12ns available. All bidirectional inputs and outputs of the IDT71024 are TTL-compatible, and operation is from a single 5V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation. The IDT71024 is packaged in 32-pin 300 mil Plastic SOJ and 32- pin 400 mil Plastic SOJ. Functional Block Diagram 2012 Integrated Device Technology, Inc. 1 FEBRUARY 2013 DSC-2964/19
2 Pin Configuration Absolute Maximum Ratings (1) Symbol Rating Value Unit VTERM (2) Terminal Voltage with Respect to GND 0.5 to +7.0 V TBIAS Temperature Under Bias 55 to +125 o C TSTG Storage Temperature 55 to +125 o C PT Power Dissipation 1.25 W IOUT DC Output Current 50 ma 2964 tbl Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VCC + 0.5V. Truth Table (1,3) Inputs WE CS1 CS2 OE 1. H = VIH, L = VIL, X = Don't care. 2. VLC = 0.2V, VHC = VCC 0.2V. 3. Other inputs VHC or VLC. SOJ Top View I/O Function X H X X High-Z Deselected Standby (ISB) X VHC (2) X X High-Z Deselected Standby (ISB1) X X L X High-Z Deselected Standby (ISB) X X VLC (2) X High-Z Deselected Standby (ISB1) H L H H High-Z Outputs Disabled H L H L DATAOUT Read Data L L H X DATAIN Write Data 2964 tbl 01 Capacitance (TA = +25 C, f = 1.0MHz, SOJ package) Symbol Parameter (1) Conditions Max. Unit CIN Input Capacitance VIN = 3dV 7 pf CI/O I/O Capacitance VOUT = 3dV 8 pf 2964 tbl 03 NOTE: 1. This parameter is guaranteed by device characterization, but is not production tested. Recommended DC Operating Conditions Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage V GND Ground V VIH Input High Voltage 2.2 VCC+0.5 V VIL Input Low Voltage 0.5 (1) 0.8 V Recommended Operating Temperature and Supply Voltage Grade Temperature GND VCC Commercial 0 C to +70 C 0V 5.0V ± 0.5V Industrial 40 C to +85 C 0V 5.0V ± 0.5V 2964 tbl 05 NOTE: 1. VIL (min.) = 1.5V for pulse width less than 10ns, once per cycle tbl
3 DC Electrical Characteristics (VCC = 5.0V ± 10%, Commercial and Industrial Temperature Ranges) IDT71024 Symbol Parameter Test Condition Min. Max. Unit ILI Input Leakage Current VCC = Max., VIN = GND to VCC ILO Output Leakage Current VCC = Max., CS1 = VIH, VOUT = GND to VCC 5 µa 5 µa VOL Output Low Voltage IOL = 8mA, VCC = Min. 0.4 V VOH Output High Voltage IOH = 4mA, VCC = Min. 2.4 V 2964 tbl 06 DC Electrical Characteristics (1) (VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC 0.2V) 71024S S S20 Symbol Parameters Com'l. Ind. Com'l. Ind. Com'l. Ind. Unit ICC ISB ISB1 Dynamic Operating Current, CS2 VIH and CS1 VIL, Outputs Open, VCC = Max., f = fmax (2) Standby Power Supply Current (TTL Level) CS1 VIH or CS2 VIL, Outputs Open, VCC = Max., f=fmax (2) Full Standby Power Supply Current (CMOS Level), CS1 VHC or CS2 VLC, Outputs Open, VCC = Max., f = 0 (2), VIN VLC or VIN VHC ma ma ma 1. All values are maximum guaranteed values. 2. fmax = 1/tRC (all address inputs are cycling at fmax); f = 0 means no address input lines are changing tbl 07 AC Test Conditions Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V AC Test Load See Figures 1 and 2 5V 5V 2964 tbl 08 DATA OUT 480Ω 480Ω 5pF* 255Ω DATA OUT 30pF 255Ω 2964 drw 04 Figure 1. AC Test Load 2964 drw 03 *Including jig and scope capacitance. Figure 2. AC Test Load (for tclz, tolz, tchz, tohz, tow, and twhz)
4 AC Electrical Characteristics (VCC = 5.0V ± 10%, Commercial and Industrial Temperature Ranges) 71024S S S20 Symbol Parameter Min. Max. Min. Max. Min. Max. Unit Read Cycle trc Read Cycle Time ns taa Address Access Time ns tacs Chip Select Access Time ns tclz (1) Chip Sele ct to Output in Low-Z ns tchz (1) Chip Deselect to Output in High-Z ns toe Output Enable to Output Valid ns tolz (1) Output Enab le to Output in Low-Z ns tohz (1) Output Disable to Output in High-Z ns toh Output Hold from Address Change ns tpu (1) Chip Select to Power-Up Time ns tpd (1) Chip Deselect to Power-Down Time ns Write Cycle twc Write Cycle Time ns taw Address Valid to End-of-Write ns tcw Chip Select to End-of-Write ns tas Address Set-Up Time ns twp Write Pulse Width ns twr Write Recovery Time ns tdw Data Valid to End-of-Write ns tdh Data Hold Time ns tow (1) Output Active from End-of-Write ns twhz (1) Write Enable to Output in High-Z ns NOTE: 1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested tbl
5 Timing Waveform of Read Cycle No. 1 (1) Timing Waveform of Read Cycle No. 2 (1,2,4) 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS1 is LOW, CS2 is HIGH. 3. Address must be valid prior to or coincident with the later of CS1 transition LOW and CS2 transition HIGH; otherwise taa is the limiting parameter. 4. OE is LOW. 5. Transition is measured ±200mV from steady state
6 Timing Waveform of Write Cycle No. 1 (WE Controlled Timing) (1,4,6) Timing Waveform of Write Cycle No. 2 (CS1 AND CS2 Controlled Timing) (1,4) 1. A write occurs during the overlap of a LOW CS1, HIGH CS2, and a LOW WE. 2. twr is measured from the earlier of either CS1 or WE going HIGH or CS2 going LOW to the end of the write cycle. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS1 LOW transition or the CS2 HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS1 and CS2 must both be active during the tcw write period. 5. Transition is measured ±200mV from steady state. 6. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, twp must be greater than or equal to twhz + tdw to allow the I/O drivers to turn off and data to be placed on the bus for the required tdw. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified twp
7 Ordering Information S XX X X X X Device Type Power Speed Package Process/ Temperature Range Blank 8 Tube or Tray Tape and Reel Blank I Commercial (0 C to +70 C) Industrial ( 40 C to +85 C) G Green TY Y 300-mil SOJ (SO32-2) 400-mil SOJ (SO32-3) Speed in nanoseconds 2964 drw
8 Datasheet Document History 9/30/99 Updated to new format Pg. 1, 3, 4, 7 Added 12ns industrial speed grade offering Pg. 1 4, 7 Removed military temperature offerings Removed 17ns and 25ns speed grades Pg. 3 Revised ICC and ISB1 for 15ns and 20ns industrial speed grades Pg. 6 Removed Note 1, reordered notes and footnotes Pg. 8 Added Datasheet Document History 1/6/2000 Pg. 4 Changed twp(min) for 12ns speed grade from 10ns to 8ns. 2/18/00 Pg. 3 Revised Icc and ISB for Industrial Temperature offerings to meet commercial specifications 3/14/00 Pg. 3 Revised ISB to accommodate speed functionality 08/09/00 Not recommended for new designs 02/01/01 Removed "Not recommended for new designs" 01/30/04 Pg. 7 Added "Restricted hazardous substance device" to the ordering information. 05/22/06 Pg.3 Added drawing Output Capacitive Derating drawing. 02/13/07 Pg.7 Added M generation die step to data sheet ordering information. 08/13/09 Pg.2 Corrected note reference. 02/05/13 Pg.1 Removed /MS from datasheet header. Removed IDT's reference to fabrication. Pg.7 Updated ordering information by adding Tape and Reel, updated Restricted Hazardous Substance Device wording to Green and removed the Die Stepping Revision, the"m" designator. CORPORATE HEADQUARTERS for SALES: 6024 Silver Creek Valley Road or San Jose, CA fax: The IDT logo is a registered trademark of Integrated Device Technology, Inc. for Tech Support: sramhelp@idt.com
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2Mx8 HIGH-SPEED ASYHRONOUS CMOS STATIC RAM WITH 3.3V/1.8V SUPPLY PRELIMINARY INFORMATION DECEMBER 2016 FEATURES High-speed access time: 8ns, 10ns, 20ns High- performance, low power CMOS process Multiple
IS61WV51216ALL IS61WV51216BLL IS64WV51216BLL
512K x 16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY OCTOBER 2009 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center power and ground
128K x 36, 256K x V Synchronous SRAMs 3.3V I/O, Pipelined Outputs Burst Counter, Single Cycle Deselect
128K x 36 256K x 18 3.3V Synchronous SRAMs 3.3V I/O Pipelined Outputs Burst Counter Single Cycle Deselect IDT71V3576S IDT71V3578S Features 128K x 36 256K x 18 memory configuratio Supports high system speed:
256K X 36, 512K X V Synchronous SRAMs 3.3V I/O, Burst Counter Pipelined Outputs, Single Cycle Deselect
256K X 36 512K X 18 3.3V Synchronous SRAMs 3.3V I/O Burst Counter Pipelined Outputs Single Cycle Deselect IDT71V67603/Z IDT71V67803/Z Features 256K x 36 512K x 18 memory configuratio Supports high system
CMOS SRAM. KM684000B Family. Document Title. Revision History. 512Kx8 bit Low Power CMOS Static RAM. Revision No. History. Remark. Draft Date 0.
Document Title 512Kx8 bit Low Power CMOS Static RAM Revision History Revision No. History Draft Date Remark 0.0 Initial Draft December 7, 1996 Advance 0.1 Revise - Changed Operating current by reticle
HIGH-SPEED 8/4K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM. LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
Features True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access Commercial: 6.5/7.5/9 (max.) Industrial: 7.5 (max.) Low-power operation
IDT74FCT257AT/CT/DT FAST CMOS QUAD 2-INPUT MULTIPLEXER
FAST CMOS QUAD 2-INPUT MULTIPLEXER IDT74FCT257AT/CT/DT FEATURES: A, C, and D grades Low input and output leakage 1µA (max.) CMOS power levels True TTL input and output compatibility: VOH = 3. (typ.) VOL
IS61WV25616ALL/ALS IS61WV25616BLL/BLS IS64WV25616BLL/BLS
ISWVALL/ALS ISWVBLL/BLS K x HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM FEATURES HIGH SPEED: (IS/WVALL/BLL) High-speed access time:,, 0 ns Low Active Power: mw (typical) Low Standby Power: mw (typical) CMOS
Document Title. Revision History. 256Kx16 bit Low Power and Low Voltage CMOS Static RAM. Draft Date. Revision No. History. Remark.
Document Title 256Kx16 bit Low Power and Low Voltage CMOS Static RAM Revision History Revision No History Draft Date Remark 0.0 Initial draft July 29, 2002 Preliminary 0.1 Revised - Added Commercial product
IS61WV25616ALL/ALS IS61WV25616BLL/BLS IS64WV25616BLL/BLS
IS61WV25616ALL/ALS IS61WV25616BLL/BLS 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM FEATURES HIGH SPEED: (IS61/64WV25616ALL/BLL) High-speed access time: 8, 10, 20 ns Low Active Power: 85 mw (typical)
IS61WV102416FALL IS61/64WV102416FBLL. 1Mx16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V/1.8V SUPPLY FUNCTIONAL BLOCK DIAGRAM
1Mx16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V/1.8V SUPPLY PRELIMINARY INFORMATION DECEMBER 2016 FEATURES High-speed access time: 8ns, 10ns, 20ns High- performance, low power CMOS process Multiple
IS64WV3216BLL IS61WV3216BLL
32K x 16 HIGH-SPEED CMOS STATIC RAM NOVEMBER 2005 FEATURES High-speed access time: 12 ns: 3.3V + 10% 15 ns: 2.5V-3.6V CMOS low power operation: 50 mw (typical) operating 25 µw (typical) standby TTL compatible
DESCRIPTION DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
28K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY JUNE 2005 FEATURES High-speed access time: 8, 0 ns CMOS low power operation 756 mw (max.) operating @ 8 ns 36 mw (max.) standby @ 8 ns TTL compatible
IS62C51216AL IS65C51216AL
IS62C51216AL IS65C51216AL 512K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FEATURES High-speed access time: 45ns, 55ns CMOS low power operation 36 mw (typical) operating 12 µw (typical) CMOS standby
IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL
1M x 16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY MAY 2012 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center power and ground pins for
IS62WV2568ALL IS62WV2568BLL
IS62WV2568ALL IS62WV2568BLL 256K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM Long-term Support NOVEMBER 2016 FEATURES High-speed access time: 45ns, 55ns, 70ns CMOS low power operation 36 mw (typical)
IS61/64WV25616FALL IS61/64WV25616FBLL. 256Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM APRIL 2018 KEY FEATURES DESCRIPTION
256Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM APRIL 2018 KEY FEATURES High-speed access time: 8, 10ns, 12ns Low Active Current: 35mA (Max., 10ns, I-temp) Low Standby Current: 10 ma (Max., I-temp) Single
IS61WV25616ALL/ALS IS61WV25616BLL/BLS IS64WV25616BLL/BLS
ISWVALL/ALS ISWVBLL/BLS K x HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM DEMBER 00 FEATURES HIGH SPEED: (IS/WVALL/BLL) High-speed access time:,, 0 ns Low Active Power: mw (typical) Low Standby Power: mw (typical)
256K X 36, 512K X V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Single Cycle Deselect
256K X 36 512K X 18 3.3V Synchronous SRAMs 2.5V I/O Burst Counter Pipelined Outputs Single Cycle Deselect IDT71V67602 IDT71V67802 Features 256K x 36 512K x 18 memory configuratio Supports high system speed:
Document Title. Revision History. 32Kx8 bit Low Power CMOS Static RAM. Remark. History. Revision No. Draft Data. Design target. Initial draft 0.
Document Title 32Kx8 bit Low Power CMOS Static RAM Revision History Revision No History Draft Data Remark 0.0 Initial draft May 18, 1997 Design target 0.1 First revision - KM62256DL/DLI ISB1 = 100 50µA
IS62/65WV2568DALL IS62/65WV2568DBLL
IS62/65WV2568DALL IS62/65WV2568DBLL 256K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM JANUARY 2013 FEATURES High-speed access time: 35ns, 45ns, 55ns CMOS low power operation 36 mw (typical) operating
IS62WV20488FALL/BLL IS65WV20488FALL/BLL. 2Mx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM NOVEMBER 2018
/BLL IS65WV20488FALL/BLL 2Mx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 35mA (max.) CMOS standby Current:
IS62WV2568ALL IS62WV2568BLL
IS62WV2568ALL IS62WV2568BLL 256K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM DECEMBER 2008 FEATURES High-speed access time: 55ns, 70ns CMOS low power operation 36 mw (typical) operating 9 µw (typical)
IS62WV5128EALL/EBLL/ECLL IS65WV5128EBLL/ECLL. 512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM APRIL 2017
512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 35ns, 45ns, 55ns CMOS low power operation Operating Current: 22 ma (max) at 85 C CMOS Standby Current: 3.7uA (typ)
IS62C25616EL, IS65C25616EL
256Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM AUGUST 2018 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 22 ma (max) at 85 C CMOS Standby Current: 5.0uA
FAST CMOS 8-BIT IDENTITY COMPARATOR
FAST CMOS 8-BIT IDENTITY COMPARATOR IDT74FCT521AT/CT FEATURES: A and C grades Low input and output leakage 1µA (max.) CMOS power levels True TTL input and output compatibility: VOH = 3. (typ.) VOL = 0.
IS61/64WV12816EFALL IS61/64WV12816EFBLL. 128Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM with ECC FUNCTIONAL BLOCK DIAGRAM APRIL 2018 KEY FEATURES
128Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM with ECC KEY FEATURES A0 A17 A16 High-speed access time: 8ns, 10ns, 12ns Single power supply 1.65V-2.2V (IS61/64WV12816EFALL) 2.4V-3.6V () Error Detection
FUNCTIONAL BLOCK DIAGRAM
128Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM MARCH 2018 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 26mA (max) at 125 C CMOS Standby Current: 3.0
IS61WV3216DALL/DALS IS61WV3216DBLL/DBLS IS64WV3216DBLL/DBLS
IS61WV3216DALL/DALS IS61WV3216DBLL/DBLS 32K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM MAY 2012 FEATURES HIGH SPEED: (IS61/64WV3216DALL/DBLL) High-speed access time: 8, 10, 12, 20 ns Low Active Power:
IS61WV6416DALL/DALS IS61WV6416DBLL/DBLS IS64WV6416DBLL/DBLS
ISWVDALL/DALS ISWVDBLL/DBLS K x HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM JANUARY 0 FEATURES HIGH SPEED: (IS/WVDALL/DBLL) High-speed access time:, 0,, 0 ns Low Active Power: mw (typical) Low Standby Power:
IS62WV102416FALL/BLL IS65WV102416FALL/BLL. 1Mx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM MARCH 2018
1Mx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM MARCH 2018 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 35mA (max.) CMOS standby Current: 5.5uA (typ.)
CEN. Binary Counter CLR CLK EN ADDRESS REGISTER 18/19. Byte 1 Write Register. Byte 2. Write Register. Byte 3. Write Register.
56K X 36 51K X 18 3.3V Synchronous SRAMs 3.3V I/O Burst Counter Flow-Through Outputs Single Cycle Deselect IDT71V67703 IDT71V67903 Features 56K x 36 51K x 18 memory configuratio Supports fast access times:
IDT71V67703 IDT71V K X 36, 512K X V Synchronous SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect
56K X 36 51K X 18 3.3V Synchronous SRAMs 3.3V I/O Burst Counter Flow-Through Outputs Single Cycle Deselect IDT71V67703 IDT71V67903 Features 56K x 36 51K x 18 memory configuratio Supports fast access times: