IDT74ALVC V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS

Transcription

1 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS IDT74ALVC16245 FEATURES: 0.5 MICRON CMOS Technology Typical tsk(o) (Output Skew) < 250ps ESD > 200 per MIL-STD-883, Method 3015; > 20 using machine model (C = 200pF, R = 0) = 3.3V ± 0.3V, Normal Range = 2.7V to 3.6V, Extended Range = 2.5V ± 0.2V CMOS power levels (0.4μ W typ. static) Rail-to-Rail output swing for increased noise margin Available in TSSOP package DRIVE FEATURES: High Output Drivers: ±24mA Suitable for heavy loads DESCRIPTION: This 16-bit bus transceiver is built using advanced dual metal CMOS technology. The ALVC16245 is designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements. This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. The ALVC16245 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. APPLICATIONS: 3.3V high speed systems 3.3V and lower voltage computing systems FUNCTIONAL BLOCK DIAGRAM 1 1DIR 2DIR OE 25 2OE 47 1A1 36 2A1 2 1B1 13 2B1 46 1A2 3 1B2 35 2A2 14 2B2 44 1A3 33 2A3 5 1B3 16 2B3 43 1A4 32 2A4 6 1B4 17 2B4 41 1A5 30 2A5 8 1B5 19 2B5 40 1A6 29 2A6 9 1B6 20 2B6 38 1A7 27 2A7 11 1B7 22 2B7 37 1A8 26 2A8 12 1B8 23 2B8 The IDT logo is a registered trademark of Integrated Device Technology, Inc. 1 JUNE Integrated Device Technology, Inc. DSC-4604/6

2 PIN CONFIGURATION 1DIR 1B1 1B2 1B3 1B4 1B5 1B B OE 1A1 1A2 1A3 1A4 1A5 1A6 1A7 ABSOLUTE MAXIMUM RATINGS (1) Symbol Description Max Unit ERM (2) Terminal Voltage with Respect to 0.5 to +4.6 V ERM (3) Terminal Voltage with Respect to 0.5 to +0.5 V TSTG Storage Temperature 65 to +150 C IOUT DC Output Current 50 to +50 ma IIK Continuous Clamp Current, ±50 ma VI < 0 or VI > IOK Continuous Clamp Current, VO < 0 50 ma ICC Continuous Current through each ±100 ma ISS or 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. terminals. 3. All terminals except. 1B8 2B1 2B2 2B3 2B A8 2A1 2A2 2A3 2A4 CAPACITANCE (TA = +25 C, F = 1.0MHz) Symbol Parameter (1) Conditions Typ. Max. Unit CIN Input Capacitance VIN = 5 7 pf COUT Output Capacitance VOUT = 7 9 pf COUT I/O Port Capacitance VIN = 7 9 pf 1. As applicable to the device type. 2B5 2B6 2B7 2B8 2DIR A5 2A6 2A7 2A8 2OE PIN DESCRIPTION Pin Names Description xoe Output Enable Inputs (Active LOW) xdir xax xbx Direction Control Inputs Side A Inputs or 3-State Outputs Side B Inputs or 3-State Outputs TSSOP TOP VIEW FUNCTION TABLE (EACH 8-BIT SECTION) (1) Inputs xoe xdir Outputs L L Bus B Data to Bus A L H Bus A Data to Bus B H X Z 1. H = HIGH Voltage Level X = Don t Care L = LOW Voltage Level Z = High-Impedance 2

3 DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 40 C to +85 C Symbol Parameter Test Conditions Min. Typ. (1) Max. Unit Input HIGH Voltage Level = 2.3V to 2.7V 1.7 V = 2.7V to 3.6V 2 VIL Input LOW Voltage Level = 2.3V to 2.7V 0.7 V = 2.7V to 3.6V 0.8 IIH Input HIGH Current = 3.6V VI = ±5 µa IIL Input LOW Current = 3.6V VI = ±5 µa IOZH High Impedance Output Current = 3.6V VO = ±10 µ A IOZL (3-State Output pins) VO = ±10 VIK Clamp Diode Voltage = 2.3V, IIN = 18mA V VH Input Hysteresis = 3.3V 100 mv ICCL Quiescent Power Supply Current = 3.6V µ A ICCH VIN = or ICCZ ΔICC Quiescent Power Supply Current One input at - 0.6V, other inputs at or 750 µ A Variation 1. Typical values are at = 3.3V, +25 C ambient. OUTPUT DRIVE CHARACTERISTICS Symbol Parameter Test Conditions (1) Min. Max. Unit Output HIGH Voltage = 2.3V to 3.6V IOH = 0.1mA 0.2 V = 2.3V IOH = 6mA 2 = 2.3V IOH = 12mA 1.7 = 2.7V 2.2 = 3V 2.4 = 3V IOH = 24mA 2 Output LOW Voltage = 2.3V to 3.6V IOL = 0.1mA 0.2 V = 2.3V IOL = 6mA 0.4 IOL = 12mA 0.7 = 2.7V IOL = 12mA 0.4 = 3V IOL = 24mA and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate range. TA = 40 C to + 85 C. 3

4 OPERATING CHARACTERISTICS, TA = 25 C = 2.5V ± 0.2V = 3.3V ± 0.3V Symbol Parameter Test Conditions Typical Typical Unit CPD Power Dissipation Capacitance Outputs enabled CL = 0pF, f = 10Mhz pf CPD Power Dissipation Capacitance Outputs disabled 4 5 SWITCHING CHARACTERISTICS (1) = 2.5V ± 0.2V = 2.7V = 3.3V ± 0.3V Symbol Parameter Min. Max. Min. Max. Min. Max. Unit tplh Propagation Delay ns tphl xax to xbx or xbx to xax tpzh Output Enable Time ns tpzl xoe to xax or xbx tphz Output Disable Time ns tplz xoe to xax or xbx tsk(o) Output Skew (2) 500 ps 1. See TEST CIRCUITS AND WAVEFORMS. TA = 40 C to + 85 C. 2. Skew between any two outputs of the same package and switching in the same direction. 4

5 TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS Symbol (1) = 3.3V±0.3V (1) = 2.7V (2) = 2.5V±0.2V Unit VLOAD x Vcc V Vcc V Vcc / 2 V VLZ mv VHZ mv CL pf SAME PHASE TRANSITION OUTPUT OPPOSITE PHASE TRANSITION tplh tplh Propagation Delay tphl tphl (1, 2) Pulse Generator VIN OUTPUT 1 OUTPUT 2 RT D.U.T. tplh1 VOUT tsk (x) CL Test Circuit for All Outputs tphl1 500Ω 500Ω DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 1. Pulse Generator for All Pulses: Rate 1.0MHz; tf 2.5ns; tr 2.5ns. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tf 2ns; tr 2ns. SWITCH POSITION Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD Open tsk (x) VLOAD Open CONTROL OUTPUT SWITCH NORMALLY CLOSED LOW OUTPUT NORMALLY HIGH DATA TIMING ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL ENABLE LOW-HIGH-LOW PULSE HIGH-LOW-HIGH PULSE tpzl tpzh SWITCH OPEN VLOAD/2 tsu tsu tphz trem tw DISABLE th tplz th VLOAD/2 + VLZ - VHZ Enable and Disable Times 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. Set-up, Hold, and Release Times tplh2 tphl2 tsk(x) = tplh2 - tplh1 or tphl2 - tphl1 Output Skew - tsk(x) 1. For tsk(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tsk(b) OUTPUT1 and OUTPUT2 are in the same bank. 5 Pulse Width

6 ORDERING INFORMATION XX ALVC X XX XXX XX Temp. Range Bus-Hold Family Device Type Package PA Thin Shrink Small Outline Package - Green Bit Bus Transceiver with 3-State Outputs 16 Double-Density, ±24mA Blank 74 No Bus-Hold 40 C to +85 C CORPORATE HEADQUARTERS for SALES: for Tech Support: 6024 Silver Creek Valley Road or logichelp@idt.com San Jose, CA fax: