FAST CMOS 8-BIT IDENTITY COMPARATOR
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1 FAST CMOS 8-BIT IDENTITY COMPARATOR IDT74FCT521AT/CT FEATURES: A and C grades Low input and output leakage 1µA (max.) CMOS power levels True TTL input and output compatibility: VOH = 3. (typ.) VOL = 0. (typ.) High Drive outputs (-15mA IOH, 48mA IOL) Meets or exceeds JEDEC standard 18 specifications Power off disable outputs permit "live insertion" Available in SOIC and QSOP packages DESCRIPTION: The IDT74FCT521T is an 8-bit identity comparator built using an advanced dual metal CMOS technology. These devices compare two words of up to eight bits each and provide a low output when the two words match bit for bit. The expansion input IA = B also serves as an active low enable input. FUNCTIONAL BLOCK DIAGRAM A0 B0 2 3 A1 B1 4 5 A2 B2 6 7 A3 B3 A4 B OA=B A5 B A6 B A7 B7 IA=B IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 MAY Integrated Device Technology, Inc. DSC-2572/15
2 PIN CONFIGURATION IA=B A0 B0 A1 B1 A VCC OA=B B7 A7 B6 A6 ABSOLUTE MAXIMUM RATINGS (1) Symbol Description Max Unit VTERM (2) Terminal Voltage with Respect to GND 0.5 to +7 V VTERM (3) Terminal Voltage with Respect to GND 0.5 to VCC+0.5 V TSTG Storage Temperature 65 to +150 C IOUT DC Output Current 60 to +120 ma 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. 2. Inputs and Vcc terminals only. 3. Output and I/O terminals only. B2 A B5 A5 CAPACITANCE (TA = +25 C, F = 1.0MHz) Symbol Parameter (1) Conditions Typ. Max. Unit B B4 CIN Input Capacitance VIN = 6 10 pf COUT Output Capacitance VOUT = 8 12 pf GND A4 NOTE: 1. This parameter is measured at characterization but not tested. TOP VIEW Package Type Package Code Order Code QSOP PCG20 QG SOIC PSG20 SOG PIN DESCRIPTION Pin Names Description A0 - A7 Word A Inputs B0 - B7 Word B Inputs IA = B Expansion or Enable Input (Active LOW) OA = B Identity Output (Active LOW) FUNCTION TABLE (1) Inputs Output IA = B A, B OA = B L A = B* L L A B H H A = B* H H A B H NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level *A0 = B0, A1 = B1, A2 = B2, etc. 2
3 DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: TA = 40 C to +85 C, VCC = 5. ±5% Symbol Parameter Test Conditions (1) Min. Typ. (2) Max. Unit VIH Input HIGH Level Guaranteed Logic HIGH Level 2 V VIL Input LOW Level Guaranteed Logic LOW Level 0.8 V IIH Input HIGH Current (4) VCC = Max. VI = 2.7V ±1 µa IIL Input LOW Current (4) VCC = Max. VI = 0.5V ±1 II Input HIGH Current (4) VCC = Max., VI = VCC (Max.) ±1 µa VIK Clamp Diode Voltage VCC = Min., IIN = 18mA V IOS Short Circuit Current VCC = Max., VO = GND (3) ma VOH Output HIGH Voltage VCC = Min IOH = 8mA V VIN = VIH or VIL IOH = 15mA 2 3 VOL Output LOW Voltage VCC = Min IOL = 48mA V VIN = VIH or VIL VH Input Hysteresis 200 mv ICC Quiescent Power Supply Current VCC = Max ma VIN = GND or VCC 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5., +25 C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. The test limit for this parameter is ±5µA at TA = 55 C. 3
4 POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions (1) Min. Typ. (2) Max. Unit ΔICC Quiescent Power Supply Current VCC = Max ma TTL Inputs HIGH VIN = 3.4V (3) ICCD Dynamic Power Supply VCC = Max. VIN = VCC ma/ Current (4) Outputs Open VIN = GND MHz One Input Toggling 50% Duty Cycle IC Total Power Supply Current (6) VCC = Max. VIN = VCC ma Outputs Open VIN = GND fi = 10MHz VIN = 3.4V One Bit Toggling VIN = GND 50% Duty Cycle 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5., +25 C ambient. 3. Per TTL driven input; (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of ΔICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ΔICC DHNT + ICCD (fcp/2+ fini) ICC = Quiescent Current ΔICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL) fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Output Frequency Ni = Number of Outputs at fi All currents are in milliamps and all frequencies are in megahertz. SWITCHING CHARACTERISTICS OVER OPERATING RANGE 74FCT521AT 74FCT521CT Symbol Parameter Condition (1) Min. (2) Max. Min. (2) Max. Unit tplh Propagation Delay CL = 50pF ns tphl Ax or Bx to OA = B RL = 500Ω tplh Propagation Delay ns tphl IA = B to OA = B 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 4
5 TEST CIRCUITS AND WAVEFORMS V CC 7. SWITCH POSITION Pulse Generator VIN R T D.U.T. VOUT 50pF C L 500W 500W Test Open Drain Disable Low Enable Low All Other Tests Switch Closed Open DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Test Circuits for All Outputs DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tsu tsu trem th th Set-Up, Hold, and Release Times LOW-HIGH-LOW PULSE HIGH-LOW-HIGH PULSE tw Pulse Width SAME PHASE INPUT TRANSITION OUTPUT OPPOSITE PHASE INPUT TRANSITION tplh tplh Propagation Delay tphl tphl VOH VOL CONTROL INPUT OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH ENABLE tpzl SWITCH CLOSED tpzh SWITCH OPEN 3.5V tphz DISABLE tplz Enable and Disable Times V VOL VOH 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tf 2.5ns; tr 2.5ns. 5
6 ORDERING INFORMATION XX FCT Temperature Range XXXX Device Type XX Package X Blank 8 Tube Tape and Reel SOG PYG QG Small Outline IC - Green Shrink Small Outline Package - Green Quarter-size Small Outline Package - Green 521AT 521CT Fast CMOS 8-Bit Identity Comparator C to +85 C Orderable Part Information Speed Grade Orderable Part ID Pkg. Code Pkg. Type Temp. Grade A 74FCT521ATQG PCG20 QSOP I 74FCT521ATQG8 PCG20 QSOP I 74FCT521ATSOG PSG20 SOIC I 74FCT521ATSOG8 PSG20 SOIC I C 74FCT521CTQG PCG20 QSOP I 74FCT521CTQG8 PCG20 QSOP I 74FCT521CTSOG PSG20 SOIC I 74FCT521CTSOG8 PSG20 SOIC I Datasheet Document History 10/03/2009 Pg. 6 Updated the ordering information by removing the "IDT" notation and non RoHS part. 05/10/2018 Pg. 2, 6 Added table under pin configuration diagram with detailed package information. Updated the ordering information diagram by deleting PYG package and adding Tube, Tape and Reel. Added new table of orderable part information. CORPORATE HEADQUARTERS for SALES: for Tech Support: 6024 Silver Creek Valley Road or logichelp@idt.com San Jose, CA fax:
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Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays description These hex buffers/drivers feature
SN54ALS00A, SN54AS00, SN74ALS00A, SN74AS00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES
Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These devices contain four independent 2-input positive-nand
IDT CMOS Static RAM 1 Meg (256K x 4-Bit)
CMOS Static RAM 1 Meg (256K x 4-Bit) IDT71028 Features 256K x 4 advanced high-speed CMOS static RAM Equal access and cycle times Commercial and Industrial: 12/15/20ns One Chip Select plus one Output Enable
MC3487 QUADRUPLE DIFFERENTIAL LINE DRIVER
Meets or Exceeds Requirements of ANSI EIA/TIA-422-B and ITU Recommendation V. -State, TTL-Compatible s Fast Transition Times High-Impedance Inputs Single -V Supply Power-Up and Power-Down Protection Designed
PO54G374A, PO74G374A
OCTAL EDGETRIGGERED DTYPE FLIPFLOP WITH 3STATE OUTPUTS FEATURES:. Patented technology. Specified From 40 C to 85 C, 40 C to 25 C, and 55 C to 25 C. Operating frequency is faster than 600MHz. VCC Operates
SN54ALS08, SN54AS08, SN74ALS08, SN74AS08 QUADRUPLE 2-INPUT POSITIVE-AND GATES
SNALS0, SNAS0, SN7ALS0, SN7AS0 Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These devices contain
74ACT11374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
Eight D-Type Flip-Flops in a Single Package -State Bus Driving True s Full Parallel Access for Loading Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and
SN54LS245, SN74LS245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
3-State s Drive Bus Lines Directly PNP s Reduce dc Loading on Bus Lines Hysteresis at Bus s Improves Noise Margins Typical Propagation Delay Times Port to Port, 8 ns TYPE IOL (SINK CURRENT) IOH (SOURCE
3.3V ZERO DELAY CLOCK MULTIPLIER
3.3V ZERO DELAY CLOCK MULTIPLIER IDT2308 FEATURES: Phase-Lock Loop Clock Distribution for Applications ranging from 10MHz to 1 operating frequency Distributes one clock input to two banks of four outputs
LOW POWER SCHOTTKY. MARKING DIAGRAMS GUARANTEED OPERATING RANGES
The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is
SN54ALS688, SN74ALS688 8-BIT IDENTITY COMPARATORS
Compare Two -Bit Words Totem-Pole Outputs () ALS Are Identical to ALS2 Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J)
3.3V ZERO DELAY CLOCK BUFFER
3.3V ZERO DELAY CLOCK BUFFER IDT2309 FEATURES: Phase-Lock Loop Clock Distribution 10MHz to 1 operating frequency Distributes one clock input to one bank of five and one bankd of four outputs Separate output
SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve
SN54LS06, SN74LS06, SN74LS16 HEX INVERTER BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays s Fully Compatible With Most TTL Circuits
PO74G553A. Pin Configuration. Logic Block Diagram. Pin Description. 800MHz Noise Cancellation TTL/CMOS Potato Chip
FEATURES:. Patented technology. Operating frequency up to 800Mz with 2pf load. Operating frequency up to 600Mz with 5pf load. Operating frequency up to 300Mz with 15pf load. Operating frequency up to 150Mz
CD74HCT4514, CD74HCT LINE TO 16-LINE DECODERS/DEMULTIPLEXERS WITH INPUT LATCHES
4.5-V to 5.5-V V CC Operation Fanout (Over Temperature Range) Standard s... 0 LSTTL Loads Bus-Driver s... 5 LSTTL Loads Wide Operating Temperature Range of 55 C to 25 C Balanced Propagation Delays and
SN75158 DUAL DIFFERENTIAL LINE DRIVER
SN78 Meets or Exceeds the Requirements of ANSI EIA/TIA--B and ITU Recommendation V. Single -V Supply Balanced-Line Operation TTL Compatible High Output Impedance in Power-Off Condition High-Current Active-Pullup
SN54AS825A, SN74AS825A 8-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS020B JUNE 1984 REVISED AUGUST 1995
Functionally Equivalent to AMD s AM2982 Improved I OH Specificatio Multiple Output Enables Allow Multiuser Control of the Interface Outputs Have Undershoot-Protection Circuitry Power-Up High-Impedance
EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at ore.hu.
EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at www.hest ore.hu. Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping
SN5407, SN5417, SN7407, SN7417 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS SDLS032A DECEMBER 1983 REVISED NOVEMBER 1997
Converts TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays s Fully Compatible With Most TTL Circuits
DIFFERENTIAL ECL-to-TTL TRANSLATOR
DIFFERENTIAL ECL-to-TTL TRANSLATOR FEATURES DESCRIPTION 2.6ns typical propagation delay Differential ECL inputs 24mA TTL outputs Flow-through pinouts Available in 8-pin SOIC package The is a differential
SN54ALS873B, SN54AS873A, SN74ALS873B, SN74AS873A DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS036D APRIL 1982 REVISED AUGUST 1995
3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs
Rad-hard 16-bit transceiver, 1.8 V to 3.3 V bidirectional level shifter. Description. Temp. range. Notes: (1) SMD = standard microcircuit drawing
Rad-hard 16-bit transceiver, 1.8 V to 3.3 V bidirectional level shifter Datasheet - production data Features Dual supply bidirectional level shifter Voltage range from 1.6 V to 3.6 V Separated enable pin
SN54ALS273, SN74ALS273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SDAS218A APRIL 1982 REVISED DECEMBER 1994
WITH CLEA SDAS2A APIL 2 EVISED DECEMBE 4 Contain Eight Flip-Flops With Single-ail Outputs Buffered Clock and Direct-Clear Inputs Individual Data Input to Each Flip-Flop Applications Include: Buffer/Storage
3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Description OBSOLESCENCE ORDER 71V016SA. Row / Column Decoders. Sense Amps and Write Drivers
3.3V CMOS Static RAM 1 Meg (4K x 1-Bit) IDT71V1 Features 4K x 1 advanced high-speed CMOS Static RAM Commercial ( to +7 C) and Industrial ( 4 C to +5 C) Equal access and cycle times Commercial and Industrial:
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK IDT5991A FEATURES: 4 pairs of programmable skew outputs Low skew: 200ps same pair, 250ps all outputs Selectable positive or negative edge synchronization:
SN54ALS873B, SN54AS873A, SN74ALS873B, SN74AS873A DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS036D APRIL 1982 REVISED AUGUST 1995
3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs
description V CC 2CLR 2D 2CLK 2PRE 2Q 2Q 1CLR 1D 1CLK 1PRE 1Q 1Q GND 2CLR 1CLR 1CLK NC 1PRE NC 1Q 2CLK 2PRE GND
Package Optio Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs TYPE TYPICAL MAXIMUM CLOCK FREUEY (CL = 0 pf) (MHz) TYPICAL POWER
SN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
Package Optio Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs TYPE TYPICAL MAXIMUM CLOCK FREUEY (CL = 0 pf) (MHz) TYPICAL POWER
SN5407, SN5417, SN7407, SN7417 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
Converts TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays s Fully Compatible With Most TTL Circuits
IDT71V424S/YS/VS IDT71V424L/YL/VL
.V CMOS Static RAM Meg (K x -Bit) IDT1V2S/YS/VS IDT1V2L/YL/VL Features K x advanced high-speed CMOS Static RAM JEDEC Center Power / GND pinout for reduced noise Equal access and cycle times Commercial
PI5C3384 PI5C3384C. 10-Bit, 2-Port Bus Switch
PI5C3384 PI5C3384C 0-Bit, 2-Port Bus Switch Features: Near-Zero propagation delay 5Ω switches connect inputs to outputs Direct bus connection when switches are ON Ultra-low quiescent power (0.2μA typical)
54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES
Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-Pin V CC and GND Configurations to Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS)
SN54ALS32, SN54AS32, SN74ALS32, SN74AS32 QUADRUPLE 2-INPUT POSITIVE-OR GATES
SN54ALS32, SN54AS32, SN74ALS32, SN74AS32 QUADRUPLE 2-INPUT POSITIVE-OR GATES SDAS113B APRIL 1982 REVISED DECEMBER 1994 Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers
SN74LVC1G06 SINGLE INVERTER BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT
and Open-Drain Accept Voltages up to 5.5 V Supports 5-V V CC Operation description This single inverter buffer/driver is designed for 1.65-V to 5.5-V V CC operation. DBV OR DCK PACKAGE (TOP VIEW) NC A
description 1G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND V CC 2G/2G 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 1Y1 2A4 1Y2 2A3 1Y3 1A2 2Y3 1A3 2Y2 1A4 2A2 2G/2G 2Y1
SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244 3-State s Drive Bus Lines or Buffer Memory Address Registers PNP s Reduce DC Loading Hysteresis at s Improves Noise Margins description These
SN54HC373, SN74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
Eight High-Current Latches in a Single Package High-Current -State True s Can Drive up to LSTTL Loads Full Parallel Access for Loading Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline
ORDERING INFORMATION PACKAGE
Member of Texas Instruments Widebus Family Latch-Up Performance Exceeds 250 ma Per JESD 17 ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) Bus Hold on Data