FAST CMOS OCTAL BUFFER/LINE DRIVER
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1 Integrated Device Technology, Inc. FAST CMOS OCTAL BUFFER/LINE DRIVER IDT4/4FCT240/A/C IDT4/4FCT241/A/C IDT4/4FCT244/A/C IDT4/4FCT40/A/C IDT4/4FCT41/A/C FEATURES: IDT4/4FCT240/241/244/40/41 equivalent to FAST TM speed and drive IDT4/4FCT240A/241A/244A/40A/41A 2% faster than FAST IDT4/4FCT240C/241C/244C/40C/41C up to % faster than FAST IOL = 64mA (commercial) and 4mA (military) CMOS power levels (1mW typ. static) Product available in Radiation Tolerant and Radiation Enhanced versions Military product compliant to MIL-STD-3, Class B Meets or exceeds JEDEC Standard 1 specifications DESCRIPTION: The IDT octal buffer/line drivers are built using an advanced dual metal CMOS technology. The IDT4/4FCT240/A/C, IDT4/4FCT241/A/C and IDT4/4FCT244/A/C are designed to be employed as memory and address drivers, clock drivers and bus-oriented transmitter/receivers which provide improved board density. The IDT4/4FCT40/A/C and IDT4/4FCT41/A/C are similar in function to the IDT4/4FCT240/A/C and IDT4/ 4FCT244/A/C, respectively, except that the inputs and outputs are on opposite sides of the package. This pinout arrangement makes these devices especially useful as output ports for microprocessors and as backplane drivers, allowing ease of layout and greater board density. FUNCTIONAL BLOCK DIAGRAMS 229 cnv* Only * D0 O0* D1 O1* D2 O2* D3 O3* D4 O4* D O* D6 O6* D O* IDT4/4FCT240 IDT4/4FCT241/244 * for 241, for 244 IDT4/4FCT40/41 *Logic diagram shown for 'FCT40. 'FCT41 is the non-inverting option dwg The IDT logo is a registered trademark of Integrated Device Technology, Inc. FAST is a trademark of National Semiconductor Co. MAY Integrated Device Technology, Inc.. DSC-4610/3 1
2 PIN CONFIGURATIONS IDT4/4FCT cnv* P20-1 D SO & E INDEX OB L DIP/SOIC/CERPACK LCC IDT4/4FCT241/ P20-1 D SO & E * INDEX * L * for 241, for 244 DIP/SOIC/CERPACK LCC IDT4/4FCT40/41 D0 D1 D2 D3 D4 D D6 D P20-1 D SO & E O0* O1* O2* O3* O4* O* O6* O* INDEX D1 D D O0* D3 O1* D4 6 L20-2 O2* D 1 O3* D6 O4* *OX for 40, OX for 41 DIP/SOIC/CERPACK D O* O6* O* LCC 2606 cnv*
3 PIN DESCRIPTION Pin Names, (1) Dxx Oxx Description 3 State Output Enable Inputs (Active LOW) 3 State Output Enable Input (Active HIGH) Inputs Outputs NOTE: 2606 tbl for 241 only. FUNCTION TABLE Inputs (1) Outputs (1) (2) D L L H L H L L H L L L H H L H H L H H H L X Z Z Z Z Z NOTES: 2606 tbl 0 1. H = High Voltage Level X = Don t Care L = Low Voltage Level Z = High Impedance 2. for 241 only. ABSOLUTE MAXIMUM RATINGS (1) Symbol Rating Commercial Military Unit VTERM (2) Terminal Voltage 0. to to +.0 V with Respect to VTERM (3) Terminal Voltage 0. to 0. to V with Respect to TA Operating 0 to +0 to +12 C Temperature TBIAS Temperature Under Bias to to +13 C TSTG Storage Temperature to to +10 C PT Power Dissipation W IOUT DC Output ma Current NOTES: 2606 tbl Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed by +0.V unless otherwise noted. 2. Input and terminals only. 3. Outputs and I/O terminals only. CAPACITANCE (TA = +2 C, f = 1.0MHz) Symbol Parameter (1) Conditions Typ. Max. Unit CIN Input VIN = 6 10 pf Capacitance COUT Output Capacitance VOUT = 12 pf NOTE: 2606 tbl This parameter is measured at characterization but not tested.. 3
4 DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = 0.2V Commercial: TA = 0 C to +0 C, =. ± %; Military: TA = C to +12 C, =. ± 10% Symbol Parameter Test Conditions (1) Min. Typ. (2) Max. Unit VIH Input HIGH Level Guaranteed Logic HIGH Level 2.0 V VIL Input LOW Level Guaranteed Logic LOW Level 0. V II H Input HIGH Current = Max. VI = µa VI = 2.V (4) II L Input LOW Current VI = 0.V (4) VI = IOZH Off State (High Impedance) = Max. VO = 10 µa Output Current VO = 2.V 10 (4) IOZL VO = 0.V 10 (4) VO = 10 VIK Clamp Diode Voltage = Min., IN = 1mA V IOS Short Circuit Current = Max. (3), VO = ma VOH Output HIGH Voltage =, VIN = VLC or VHC, IOH = 32µA VHC V = Min. IOH = 300µA VHC VIN = VIH or VIL IOH = 12mA MIL IOH = 1mA COM'L VOL Output LOW Voltage =, VIN = VLC or VHC, IOL = 300µA VLC V = Min. IOL = 300µA VLC (4) VIN = VIH or VIL IOL = 4mA MIL IOL = 64mA COM'L NOTES: 2606 tbl For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at =., +2 C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. 4. This parameter is guaranteed but not tested.. 4
5 POWER SUPPLY CHARACTERISTICS VLC = 0.2V; VHC = 0.2V Symbol Parameter Test Conditions (1) Min. Typ. (2) Max. Unit ICC Quiescent Power Supply Current = Max. VIN VHC; V IN VLC ma ICC ICCD Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current (4) = Max ma VIN = 3.4V (3) = Max. Outputs Open = = or =, = One Input Toggling 0% Duty Cycle IC Total Power Supply Current (6) = Max. Outputs Open fi = 10MHz 0% Duty Cycle = = or =, = One Bit Toggling = Max. Outputs Open fi = MHz 0% Duty Cycle = = or =, = Eight Bits Toggling VIN VHC VIN VLC VIN VHC VIN VLC (FCT) VIN = 3.4V VIN = VIN VHC VIN VLC (FCT) VIN = 3.4V VIN = ma/ MHz ma ().2. () NOTES: 2606 tbl For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at =., +2 C ambient. 3. Per TTL driven input (VIN = 3.4V); all other inputs at or. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fcp/2 + fini) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz..
6 SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR FCT240 (1,2) 4/4FCT240 4/4FCT240A 4/4FCT240C Com'l. Mil. Com'l. Mil. Com'l. Mil. Symbol Parameter Condition Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit tplh Propagation Delay CL = 0pF tphl DN to ON RL = 00Ω ns tpzh tpzl Output Enable Time ns tphz tplz Output Disable Time ns 2606 tbl 0 SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR FCT241 AND FCT244(1,2) SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR FCT241 AND FCT244 (1,2) 4/4FCT241/244 4/4FCT241A/244A 4/4FCT241C/244C Com'l. Mil. Com'l. Mil. Com'l. Mil. Symbol Parameter Condition Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit tplh Propagation Delay CL = 0pF tphl DN to ON RL = 00Ω ns tpzh tpzl Output Enable Time ns tphz tplz Output Disable Time ns 2606 tbl 0 SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR FCT40 AND FCT41 (1,2) 4/4FCT40/41 4/4FCT40A/41A 4/4FCT40C/41C Com'l. Mil. Com'l. Mil. Com'l. Mil. Symbol Parameter Condition Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit tplh tphl tplh tphl tpzh tpzl Propagation Delay DN to ON IDT4/4FCT40 Propagation Delay DN to ON IDT4/4FCT41 CL = 0pF RL = 00Ω ns ns Output Enable Time ns tphz Output Disable Time ns tplz NOTES: 2606 tbl See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays.. 6
7 TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS Pulse Generator VIN R T D.U.T. V OUT 0pF C L 00Ω 00Ω. SWITCH POSITION Test Open Drain Disable Low Enable Low All Other Tests Switch Closed Open DEFINITIONS: 2606 tbl 10 CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. t SU t SU t REM t H t H LOW-HIGH-LOW PULSE HIGH-LOW-HIGH PULSE t W PROPAGATION DELAY ENABLE AND DISABLE TIMES SAME PHASE INPUT TRANSITION OUTPUT OPPOSITE PHASE INPUT TRANSITION tplh t PLH t PHL tphl VOH VOL CONTROL INPUT OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH ENABLE tpzl SWITCH CLOSED tpzh SWITCH OPEN 3.V DISABLE tplz 0. tphz 0. 3.V V OL V OH NOTES 2606 drw Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate 1.0 MHz; ZO 0Ω; tf 2.ns; tr 2.ns..
8 ORDERING INFORMATION IDT XX FCT XXXX Temp. Range Device Type X Package X Process Blank B P D SO L E Commercial MIL-STD-3, Class B Plastic DIP CERDIP Small Outline IC Leadless Chip Carrier CERPACK A 241A 244A 40A 41A 240C 241C 244C 40C 41C 4 4 Inverting Octal Buffer/Line Driver Non-Inverting Octal Buffer/Line Driver Non-Inverting Octal Buffer/Line Driver Inverting Octal Buffer/Line Driver Non-Inverting Octal Buffer/Line Driver Fast Inverting Octal Buffer/Line Driver Fast Non-Inverting Octal Buffer/Line Driver Fast Non-Inverting Octal Buffer/Line Driver Fast Inverting Octal Buffer/Line Driver Fast Non-Inverting Octal Buffer/Line Driver Super Fast Inverting Octal Buffer/Line Driver Super Fast Non-Inverting Octal Buffer/Line Driver Super Fast Non-Inverting Octal Buffer/Line Driver Super Fast Inverting Octal Buffer/Line Driver Super Fast Non-Inverting Octal Buffer/Line Driver C to +12 C 0 C to +0 C 2606 cnv* 1.
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High-Current -State s Drive Bus Lines, Buffer Memory Address Registers, or Drive up to LSTTL Loads True s Package Options Include Plastic Small-Outline (D) and Ceramic Flat (W) Packages, Ceramic Chip Carriers
CMOS Static RAM 1 Meg (128K x 8-Bit) IDT71024S
CMOS Static RAM 1 Meg (128K x 8-Bit) IDT71024S Features 128K x 8 advanced high-speed CMOS static RAM Commercial (0 C to +70 C), Industrial ( 40 C to +85 C) Equal access and cycle times Commercial and Industrial:
SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SN54LS373, SN54LS374, SN54S373, SN54S374, Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving s Full Parallel Access for Loading Buffered Control s Clock-Enable Has
QUICKSWITCH PRODUCTS HIGH-SPEED CMOS QUICKSWITCH 8-BIT BUS SWITCH
FEATURES: Enhanced N channel FET with no inherent diode to Vcc 5Ω bidirectional switches connect inputs to outputs Pin compatible with the 74F245, 74FCT245, and 74FCT245T Low power CMOS proprietary technology
P54FCT240/74fct240 INVERTING OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS FEATURES DESCRIPTION
P54FCT240/74fct240 INVERTING OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS FEATURES Function, Pinout and Drive Compatible with the FCT and F Logic FCT-A speed at 5.1ns max (MIL) Output levels compatible
SN54HC573A, SN74HC573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS147B DECEMBER 1982 REVISED MAY 1997
High-Current -State s Drive Bus Lines Directly or up to LSTTL Loads Bus-Structured Pinout Package Options Include Plastic Small-Outline (DW) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and
SN54HC245, SN74HC245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
High-Current -State s Drive Bus Lines Directly or up to LSTTL Loads Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages,
P54FCT244/74fct244 OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS FEATURES DESCRIPTION. Function, Pinout and Drive Compatible with the FCT and F Logic
P54FCT244/74fct244 OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS FEATURES Function, Pinout and Drive Compatible with the FCT and F Logic FCT-A speed at 5.1ns max (MIL) Output levels compatible with TTL
54AC11241, 74AC11241 OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS
SCAS032A JUL 187 REVISED APRIL 13 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and Configuratio Minimize High-Speed
PO74G16240A. Pin Configuration. Logic Block Diagram. Truth Table. 74 Series Noise Cancellation GHz Logic DESCRIPTION: FEATURES:
FEATURES:. Patented technology. Operating frequency up to.25ghz with 2pf load. Operating frequency up to 700MHz with 5pf load. Operating frequency up to 300MHz with 5pf load. Operating frequency up to
MC3487 QUADRUPLE DIFFERENTIAL LINE DRIVER
Meets or Exceeds Requirements of ANSI EIA/TIA-422-B and ITU Recommendation V. -State, TTL-Compatible s Fast Transition Times High-Impedance Inputs Single -V Supply Power-Up and Power-Down Protection Designed
SN54HC373, SN74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
Eight High-Current Latches in a Single Package High-Current -State True s Can Drive up to LSTTL Loads Full Parallel Access for Loading Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline
PO54G374A, PO74G374A
OCTAL EDGETRIGGERED DTYPE FLIPFLOP WITH 3STATE OUTPUTS FEATURES:. Patented technology. Specified From 40 C to 85 C, 40 C to 25 C, and 55 C to 25 C. Operating frequency is faster than 600MHz. VCC Operates
MC3486 QUADRUPLE DIFFERENTIAL LINE RECEIVER WITH 3-STATE OUTPUTS
Meets or Exceeds the Requirements of ANSI Standards EIA/TIA-422-B and EIA/TIA-423-B and ITU Recommendations V.10 and V.11 3-State, TTL-Compatible s Fast Transition Times Operates From Single 5-V Supply
54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES
Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-Pin V CC and GND Configurations to Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS)
SN54HC373, SN74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS140B DECEMBER 1982 REVISED MAY 1997
Eight High-Current Latches in a Single Package High-Current -State True s Can Drive up to LSTTL Loads Full Parallel Access for Loading Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline
SN54ACT241, SN74ACT241 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
Inputs Are TTL Compatible EPIC (Enhanced-Performance Implanted CMOS) -µm Process Package Optio Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and DIP (N)
SN54ALS00A, SN54AS00, SN74ALS00A, SN74AS00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES
Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These devices contain four independent 2-input positive-nand
SN54LS245, SN74LS245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
3-State s Drive Bus Lines Directly PNP s Reduce dc Loading on Bus Lines Hysteresis at Bus s Improves Noise Margins Typical Propagation Delay Times Port to Port, 8 ns TYPE IOL (SINK CURRENT) IOH (SOURCE
P54FCT240T/74fct240T FEATURES DESCRIPTION. Function, Pinout and Drive Compatible with the FCT and F Logic. ESD protection exceeds 2000V
P54FCT240T/74fct240T inverting OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS FEATURES Function, Pinout and Drive Compatible with the FCT and F Logic FCT-A speed at 5.1ns max (MIL) Reduced VOH (typically
QUICKSWITCH PRODUCTS HIGH-SPEED 32-BIT BUS EXCHANGE SWITCH IN MILLIPAQ
QUICKSWITCH PRODUCTS HIGH-SPEED 3-BIT BUS EXCHANGE SWITCH IN MILLIPAQ IDTQS3X33 FEATURES: 5Ω switches connect inputs to outputs Zero propagation delay Direct bus connect Live insertion capability Low power
SN54ALS688, SN74ALS688 8-BIT IDENTITY COMPARATORS
Compare Two -Bit Words Totem-Pole Outputs () ALS Are Identical to ALS2 Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J)
QUICKSWITCH PRODUCTS HIGH-SPEED CMOS QUICKSWITCH 16:8 MULTIPLEXER
QUICKSWITCH PRODUCTS HIGH-SPEED CMOS QUICKSWITCH 16:8 MULTIPLEXER IDTQS32390 FEATURES: Enhanced N channel FET with no inherent diode to Vcc 16:8 multiplexer function with zero delay 5Ω bidirectional switches
SN54ALS244C, SN54AS244A, SN74ALS244C, SN74AS244A OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
SNALS2C, SNAS2A, SNALS2C, SNAS2A SDAS2C JUL 9 REISED AUGUST 99 -State Outputs Drive Bus Lines or Buffer Memory Address Registers pnp Inputs Reduce dc Loading Package Optio Include Plastic Small-Outline
SN54ALS08, SN54AS08, SN74ALS08, SN74AS08 QUADRUPLE 2-INPUT POSITIVE-AND GATES
SNALS0, SNAS0, SN7ALS0, SN7AS0 Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These devices contain
OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS
P54FCT241T/74fct241t OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS FEATURES Function, Pinout and Drive Compatible with the FCT and F Logic FCT-A speed at 5.1ns max (MIL) Reduced VOH (typically = 3.3V)
54AC16245, 74AC BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
4AC64, 74AC64 6-BIT BUS TRANSCEIVERS SCAS3A MARCH 990 REVISED APRIL 996 Members of the Texas Itruments Widebus Family 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Flow-Through Architecture
SN54ALS563B, SN74ALS563B OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
-State Buffer-Type s Drive Bus Lines Directly Bus-Structured Pinout Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), Standard Plastic (N) and Ceramic (J) 00-mil DIPs,
74AC11373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
74A7 Eight Latches in a Single Package -State Bus-Driving True s Full Parallel Access for Loading Buffered Control Inputs Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and Configuratio
CD74HCT4514, CD74HCT LINE TO 16-LINE DECODERS/DEMULTIPLEXERS WITH INPUT LATCHES
4.5-V to 5.5-V V CC Operation Fanout (Over Temperature Range) Standard s... 0 LSTTL Loads Bus-Driver s... 5 LSTTL Loads Wide Operating Temperature Range of 55 C to 25 C Balanced Propagation Delays and
PO54G14A, PO74G14A. Pin Configuration. 54, 74 Series Noise Cancellation GHz Logic FEATURES: DESCRIPTION: V CC 6A 6Y 5A 5Y 4A 4Y 1A 1Y 2A 2Y 3A 3Y GND
FEATURES:. Patented technology. Operating frequency up to 1.125GHz with 2pf load. Operating frequency up to 680MHz with 5pf load. Operating frequency up to 300MHz with 15pf load. Operating frequency up
AM26LS31 QUADRUPLE DIFFERENTIAL LINE DRIVER
AM6LS SLLSG JANUARY 979 REVISED FEBRUARY Meets or Exceeds the Requirements of ANSI TIA/EIA--B and ITU Recommendation V. Operates From a Single -V Supply TTL Compatible Complementary Outputs High Output
description V CC 2CLR 2D 2CLK 2PRE 2Q 2Q 1CLR 1D 1CLK 1PRE 1Q 1Q GND 2CLR 1CLR 1CLK NC 1PRE NC 1Q 2CLK 2PRE GND
Package Optio Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs TYPE TYPICAL MAXIMUM CLOCK FREUEY (CL = 0 pf) (MHz) TYPICAL POWER
SN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
Package Optio Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs TYPE TYPICAL MAXIMUM CLOCK FREUEY (CL = 0 pf) (MHz) TYPICAL POWER
3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Description OBSOLESCENCE ORDER 71V016SA. Row / Column Decoders. Sense Amps and Write Drivers
3.3V CMOS Static RAM 1 Meg (4K x 1-Bit) IDT71V1 Features 4K x 1 advanced high-speed CMOS Static RAM Commercial ( to +7 C) and Industrial ( 4 C to +5 C) Equal access and cycle times Commercial and Industrial:
SN74ALVCH V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 200 Per MIL-STD-883, Method 3015; Exceeds 20 Using Machine Model (C =
description 1G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND V CC 2G/2G 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 1Y1 2A4 1Y2 2A3 1Y3 1A2 2Y3 1A3 2Y2 1A4 2A2 2G/2G 2Y1
SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244 3-State s Drive Bus Lines or Buffer Memory Address Registers PNP s Reduce DC Loading Hysteresis at s Improves Noise Margins description These
SN74ALVCH BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 200 Per MIL-STD-883, Method 3015; Exceeds 20 Using Machine Model (C =
500MHz TTL/CMOS Potato Chip
FEATURES:. Patent pending technology. Max input frequency > 1GHz. Operating frequency up to 500MHz with 2pf load. Operating frequency up to 450MHz with 5pf load. Operating frequency up to 300MHz with 15pf
SN54HCT373, SN74HCT373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
Inputs Are TTL-Voltage Compatible Eight High-Current Latches in a Single Package High-Current -State True s Can Drive up to LSTTL Loads Full Parallel Access for Loading Package Optio Include Plastic Small-Outline
SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve
IDT71V424S/YS/VS IDT71V424L/YL/VL
.V CMOS Static RAM Meg (K x -Bit) IDT1V2S/YS/VS IDT1V2L/YL/VL Features K x advanced high-speed CMOS Static RAM JEDEC Center Power / GND pinout for reduced noise Equal access and cycle times Commercial
P54FCT373/74fct373 OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS FEATURES DESCRIPTION. Function, Pinout and Drive Compatible with the FCT and F Logic
P54FCT373/74fct373 OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS FEATURES Function, Pinout and Drive Compatible with the FCT and F Logic FCT-A speed at 5.6ns max (MIL) Output levels compatible with TTL
SN54LS07, SN74LS07, SN74LS17 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays description These hex buffers/drivers feature
QUICKSWITCH BASICS AND APPLICATIONS
QUICKSWITCH GENERAL INFORMATION QUICKSWITCH BASICS AND APPLICATIONS INTRODUCTION The QuickSwitch family of FET switches was pioneered in 1990 to offer designers products for high-speed bus connection and
QS54/74FCT373T, 2373T. High-Speed CMOS Bus Interface 8-Bit Latches MDSL QUALITY SEMICONDUCTOR, INC. 1 DECEMBER 28, 1998
Q QUALITY SEMICONDUCTOR, INC. QS54/74FCT373T, 2373T High-Speed CMOS Bus Interface 8-Bit Latches QS54/74FCT373T QS54/74FCT2373T FEATURES/BENEFITS Pin and function compatible to the 74F373 74FCT373 and 74ABT373
SN54ALS273, SN74ALS273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SDAS218A APRIL 1982 REVISED DECEMBER 1994
WITH CLEA SDAS2A APIL 2 EVISED DECEMBE 4 Contain Eight Flip-Flops With Single-ail Outputs Buffered Clock and Direct-Clear Inputs Individual Data Input to Each Flip-Flop Applications Include: Buffer/Storage
SN5414, SN54LS14, SN7414, SN74LS14 HEX SCHMITT-TRIGGER INVERTERS
Operation From Very Slow Edges Improved Line-Receiving Characteristics High Noise Immunity SN5414, SN54LS14, SN5414, SN54LS14...J OR W PACKAGE SN7414... D, N, OR NS PACKAGE SN74LS14... D, DB, OR N PACKAGE
SN54LS06, SN74LS06, SN74LS16 HEX INVERTER BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays s Fully Compatible With Most TTL Circuits