FAST CMOS 16-BIT REGISTER (3-STATE)
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- Horace Richard
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1 FAST CMOS 16-BIT REGISTER (3-STATE) IDT54/74FCT16374T/AT/CT/ET IDT54/74FCT162374T/AT/CT/ET Integrated Device Technology, Inc. FEATURES: Common features: 0.5 MICRON CMOS Technology High-speed, low-power CMOS replacement for ABT functions Typical tsk(o) (Output Skew) < 250ps Low input and output leakage 1µA (max.) ESD > 200 per MIL-STD-883, Method 3015; > 20 using machine model (C = 200pF, R = 0) Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack Extended commercial range of -40 C to +85 C = 5V ±10% Features for FCT16374T/AT/CT/ET: High drive outputs (-32mA IOH, 64mA IOL) Power off disable outputs permit live insertion Typical VOLP (Output Ground Bounce) < 1. at = 5V, TA = 25 C Features for FCT162374T/AT/CT/ET: Balanced Output Drivers: ±24mA (commercial), ±16mA (military) Reduced system switching noise Typical VOLP (Output Ground Bounce) < 0.6V at = 5V,TA = 25 C DESCRIPTION: The FCT16374T/AT/CT/ET and FCT162374T/AT/CT/ET 16-bit edge-triggered D-type registers are built using advanced dual metal CMOS technology. These high-speed, low-power registers are ideal for use as buffer registers for data synchronization and storage. The Output Enable (xoe) and clock (xclk) controls are organized to operate each device as two 8-bit registers or one 16-bit register with common clock. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The FCT16374T/AT/CT/ET are ideally suited for driving high-capacitance loads and low-impedance backplanes. The output buffers are designed with power off disable capability to allow "live insertion" of boards when used as backplane drivers. The FCT162374T/AT/CT/ET have balanced output drive with current limiting resistors. This offers low ground bounce, minimal undershoot, and controlled output fall times reducing the need for external series terminating resistors. The FCT162374T/AT/CT/ET are plug-in replacements for the FCT16374T/AT/CT/ET and ABT16374 for on-board bus interface applications. FUNCTIONAL BLOCK DIAGRAM 1OE 2OE 1CLK 2CLK 1D1 D 2D1 D 1O1 2O1 C C TO 7 OTHER CHANNELS 2542 drw 01 TO 7 OTHER CHANNELS 2542 drw 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc. FEBRUARY Integrated Device Technology, Inc. 5.8 DSC-2542/9 For the latest information regarding this part, please contact IDT's web site at or fax-on-demand service at (US) IDT-FAX / (International)
2 5.8 2 IDT54/74FCT16374T/AT/CT/ET, T/AT/CT/ET PIN CONFIGURATIONS 1O1 1O3 1OE 2O2 1O2 1O4 1O5 1O6 1O7 1O8 2O1 2O3 2O4 2O5 2O7 2O8 2O6 2OE 1CLK 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 2D1 2D2 2D3 2D4 2D5 2D7 2D8 2D6 2CLK drw 04 CERPACK TOP VIEW E48-1 1O1 1O3 1OE 2O2 1O2 1O4 1O5 1O6 1O7 1O8 2O1 2O3 2O4 2O5 2O7 2O8 2O6 2OE 1CLK 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 2D1 2D2 2D3 2D4 2D5 2D7 2D8 2D6 2CLK 2542 drw SSOP/ TSSOP/TVSOP TOP VIEW SO48-1 SO48-2 SO48-3
3 PIN DESCRIPTION FUNCTION TABLE (1) Pin Names xdx xclk xox Data Inputs Clock Inputs 3-State Outputs. Description xoe 3-State Output Enable Input (Active LOW) 2542 tbl 01 Inputs Function xdx xclk xoe Outputs Hi-Z X L H Z xox X H H Z Load L L L Register H L H NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don t Care Z = High Impedance = LOW-to-HIGH Transition L H Z H H Z 2542 tbl 02 ABSOLUTE MAXIMUM RATINGS (1) Symbol Description Max. Unit VTERM (2) Terminal Voltage with Respect to 0.5 to +7.0 V VTERM (3) Terminal Voltage with Respect to 0.5 to V +0.5 TSTG Storage Temperature 65 to +150 C IOUT DC Output Current 60 to +120 ma 2542 lnk Stresses greater than those listed under ABSOLUTE MAXIMUM RAT- INGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All device terminals except FCT162XXXT Output and I/O terminals. 3. Output and I/O terminals for FCT162XXXT. CAPACITANCE (TA = +25 C, f = 1.0MHz) Symbol Parameter (1) Conditions Typ. Max. Unit CIN Input VIN = pf Capacitance CI/O I/O Capacitance VOUT = pf NOTE: 2542 lnk This parameter is measured at characterization but not tested
4 DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 40 C to +85 C, = 5. ± 10%; Military: TA = 55 C to +125 C, = 5. ± 10% Symbol Parameter Test Conditions (1) Min. Typ. (2) Max. Unit VIH Input HIGH Level Guaranteed Logic HIGH Level 2.0 V VIL Input LOW Level Guaranteed Logic LOW Level 0.8 V II H Input HIGH Current (Input pins) (5) = Max. VI = ±1 µa Input HIGH Current (I/O pins) (5) ±1 II L Input LOW Current (Input pins) (5) VI = ±1 Input LOW Current (I/O pins) (5) ±1 IOZH High Impedance Output Current = Max. VO = 2.7V ±1 µa IOZL (3-State Output pins) (5) VO = 0.5V ±1 VIK Clamp Diode Voltage = Min., IIN = 18mA V IOS Short Circuit Current = Max., VO = (3) ma VH Input Hysteresis 100 mv ICCL ICCH ICCZ Quiescent Power Supply Current = Max., VIN = or µa OUTPUT DRIVE CHARACTERISTICS FOR FCT16374T 2542 lnk 05 Symbol Parameter Test Conditions (1) Min. Typ. (2) Max. Unit IO Output Drive Current = Max., VO = 2.5V (3) ma VOH Output HIGH Voltage = Min. IOH = 3mA V VIN = VIH or VIL IOH = 12mA MIL. IOH = 15mA COM'L V IOH = 24mA MIL V IOH = 32mA COM'L. (4) VOL Output LOW Voltage = Min. VIN = VIH or VIL IOL = 48mA MIL. IOL = 64mA COM'L V IOFF Input/Output Power Off Leakage (5) =, VIN or VO 4.5V ±1 µa OUTPUT DRIVE CHARACTERISTICS FOR FCT162374T 2542 lnk 06 Symbol Parameter Test Conditions (1) Min. Typ. (2) Max. Unit IODL Output LOW Current = 5V, VIN = VIH or VIL, VOUT = (3) ma IODH Output HIGH Current = 5V, VIN = VIH or VIL, VOUT = (3) ma VOH Output HIGH Voltage = Min. IOH = 16mA MIL V VIN = VIH or VIL IOH = 24mA COM'L. VOL Output LOW Voltage = Min. VIN = VIH or VIL IOL = 16mA MIL. IOL = 24mA COM'L V 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5., +25 C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. Duration of the condition can not exceed one second. 5. The test limit for this parameter is ± 5µA at TA = 55 C lnk
5 POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions (1) Min. Typ. (2) Max. Unit ICC ICCD Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current (4) = Max ma VIN = 3.4V (3) = Max. Outputs Open xoe = One Input Toggling IC Total Power Supply Current (6) = Max. Outputs Open fcp = 10MHz xoe = fi = 5MHz One Bit Toggling VIN = VIN = VIN = VIN = VIN = 3.4V VIN = µa/ MHz ma = Max. Outputs Open fcp = 10MHz xoe = Sixteen Bits Toggling fi = 2.5MHz VIN = VIN = VIN = 3.4V VIN = (5) (5) 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at = 5., +25 C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at or. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fcpncp/2 + fini) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fcp fi = Input Frequency Ni = Number of Inputs at fi 2542 tbl
6 SWITCHING CHARACTERISTICS OVER OPERATING RANGE FCT16374T/162374T FCT16374AT/162374AT Com'l. Mil. Com'l. Mil. Symbol Parameter Condition (1) Min. (2) Max. Min. (2) Max. Min. (2) Max. Min. (2) Max. Unit tplh tphl tpzh tpzl tphz tplz Propagation Delay xclk to xox CL = 50pF RL = 500Ω ns Output Enable Time ns Output Disable Time ns tsu Set-up Time HIGH ns or LOW, xdx to xclk th Hold Time HIGH ns or LOW, xdx to xclk tw xclk Pulse Width ns HIGH or LOW tsk(o) Output Skew (3) ns FCT16374CT/162374CT FCT16374ET/162374ET Com'l. Mil. Com'l. Mil. Symbol Parameter Condition (1) Min. (2) Max. Min. (2) Max. Min. (2) Max. Min. (2) Max. Unit tplh tphl tpzh tpzl tphz tplz Propagation Delay xclk to xox CL = 50pF RL = 500Ω ns Output Enable Time ns Output Disable Time ns tsu Set-up Time HIGH ns or LOW, xdx to xclk th Hold Time HIGH ns or LOW, xdx to xclk tw xclk Pulse Width (4) ns HIGH or LOW tsk(o) Output Skew (3) ns 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 4. This limit is guaranteed but not tested tbl
7 TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS SWITCH POSITION Pulse Generator VIN R T V CC D.U.T. VOUT 50pF C L 500Ω 500Ω 7. Test Open Drain Disable Low Enable Low All Other Tests Switch Closed Open DEFINITIONS: 2542 lnk 10 CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator drw 05 SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tsu tsu trem th th 2542 drw 06 LOW-HIGH-LOW PULSE HIGH-LOW-HIGH PULSE tw 2542 drw 07 PROPAGATION DELAY ENABLE AND DISABLE TIMES SAME PHASE INPUT TRANSITION OUTPUT OPPOSITE PHASE INPUT TRANSITION tplh tplh tphl tphl VOH VOL 2542 drw 08 CONTROL INPUT OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH ENABLE tpzl SWITCH CLOSED tpzh SWITCH OPEN 3.5V tphz DISABLE tplz V VOL VOH 2542 drw Diagram shown for input Control Enable-LOW and input Control Disable- HIGH 2. Pulse Generator for All Pulses: Rate 1.0MHz; tf 2.5ns; tr 2.5ns 5.8 7
8 ORDERING INFORMATION IDT XX Temp. Range FCT XXXX Device Type X Package X Process Blank B PV PA PF E 16374T 16374AT 16374CT 16374ET T AT CT ET Commercial MIL-STD-883, Class B Shrink Small Outline Package (SO48-1) Thin Shrink Small Outline Package (SO48-2) Thin Very Small Outline Package (SO48-3) CERPACK (E48-1) Non-Inverting 16-Bit Register 55 C to +125 C 40 C to +85 C 2542 drw
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FEATURES:. Patent pending technology. Max input frequency > 1GHz. Operating frequency up to 500MHz with 2pf load. Operating frequency up to 450MHz with 5pf load. Operating frequency up to 300MHz with 15pf
QUICKSWITCH BASICS AND APPLICATIONS
QUICKSWITCH GENERAL INFORMATION QUICKSWITCH BASICS AND APPLICATIONS INTRODUCTION The QuickSwitch family of FET switches was pioneered in 1990 to offer designers products for high-speed bus connection and
SN54ALS00A, SN54AS00, SN74ALS00A, SN74AS00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES
Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These devices contain four independent 2-input positive-nand
SN5414, SN54LS14, SN7414, SN74LS14 HEX SCHMITT-TRIGGER INVERTERS
Operation From Very Slow Edges Improved Line-Receiving Characteristics High Noise Immunity SN5414, SN54LS14, SN5414, SN54LS14...J OR W PACKAGE SN7414... D, N, OR NS PACKAGE SN74LS14... D, DB, OR N PACKAGE
SN54ALS873B, SN54AS873A, SN74ALS873B, SN74AS873A DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS036D APRIL 1982 REVISED AUGUST 1995
3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs
PO74G2308A FEATURES: DESCRIPTION: Description. 700MHz TTL/CMOS Potato Chip. BUF_IN OUTPUT 1 to OUTPUT 8. Outputs. 1.2V - 3.6V 1:8 CMOS Clock Driver
FEATURES:. Patented technology. Operating frequency up to 700MHz with 2pf load. Operating frequency up to 550MHz with 5pf load. Operating frequency up to 350MHz with 15pf load. Operating frequency up to
SN54ALS08, SN54AS08, SN74ALS08, SN74AS08 QUADRUPLE 2-INPUT POSITIVE-AND GATES
SNALS0, SNAS0, SN7ALS0, SN7AS0 Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These devices contain
QUICKSWITCH PRODUCTS HIGH-SPEED CMOS QUICKSWITCH 16:8 MULTIPLEXER
QUICKSWITCH PRODUCTS HIGH-SPEED CMOS QUICKSWITCH 16:8 MULTIPLEXER IDTQS32390 FEATURES: Enhanced N channel FET with no inherent diode to Vcc 16:8 multiplexer function with zero delay 5Ω bidirectional switches
ORDERING INFORMATION PACKAGE
Member of Texas Instruments Widebus Family State-of-the-Art Advanced Low-Voltage BiCMOS (ALB) Technology Design for.-v Operation Schottky Diodes on All s to Eliminate Overshoot and Undershoot Industry
SN54ALS873B, SN54AS873A, SN74ALS873B, SN74AS873A DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS036D APRIL 1982 REVISED AUGUST 1995
3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs
SN74ALVCH BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 200 Per MIL-STD-883, Method 3015; Exceeds 20 Using Machine Model (C =
CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM
Integrated Device Technology, Inc. CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM IDT6178S FEATURES: High-speed Address to Valid time Military: 12/15/20/25ns Commercial: 10/12/15/20/25ns (max.) High-speed
IDT CMOS Static RAM 1 Meg (256K x 4-Bit)
CMOS Static RAM 1 Meg (256K x 4-Bit) IDT71028 Features 256K x 4 advanced high-speed CMOS static RAM Equal access and cycle times Commercial and Industrial: 12/15/20ns One Chip Select plus one Output Enable
PO74G139A. Pin Configuration. Logic Block Diagram. Pin Description. 74 Series Noise Cancellation GHz Logic FEATURES: DESCRIPTION:
FEATURES:. Patented technology. Operating frequency up to 1.125GHz with 2pf load. Operating frequency up to 800MHz with 5pf load. Operating frequency up to 350MHz with 15pf load. VCC Operates from 1.65V
CMOS STATIC RAM 1 MEG (128K x 8-BIT)
CMOS STATIC RAM 1 MEG (12K x -BIT) IDT71024 Integrated Device Technology, Inc. FEATURES: 12K x advanced high-speed CMOS static RAM Commercial (0 to 70 C), Industrial (-40 to 5 C) and Military (-55 to 125
QUICKSWITCH PRODUCTS HIGH-SPEED 32-BIT BUS EXCHANGE SWITCH IN MILLIPAQ
QUICKSWITCH PRODUCTS HIGH-SPEED 3-BIT BUS EXCHANGE SWITCH IN MILLIPAQ IDTQS3X33 FEATURES: 5Ω switches connect inputs to outputs Zero propagation delay Direct bus connect Live insertion capability Low power
SN54LVC14A, SN74LVC14A HEX SCHMITT-TRIGGER INVERTERS
Typical V OLP ( Ground Bounce) 2 V at V CC = 3.3 V, T A = 25 C s Accept Voltages to 5.5 V Latch-Up Performance Exceeds 100 ma Per JESD
CMOS Static RAM 1 Meg (128K x 8-Bit) IDT71024S
CMOS Static RAM 1 Meg (128K x 8-Bit) IDT71024S Features 128K x 8 advanced high-speed CMOS static RAM Commercial (0 C to +70 C), Industrial ( 40 C to +85 C) Equal access and cycle times Commercial and Industrial:
SN5407, SN5417, SN7407, SN7417 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS SDLS032A DECEMBER 1983 REVISED NOVEMBER 1997
Converts TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays s Fully Compatible With Most TTL Circuits
SN54LS245, SN74LS245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
3-State s Drive Bus Lines Directly PNP s Reduce dc Loading on Bus Lines Hysteresis at Bus s Improves Noise Margins Typical Propagation Delay Times Port to Port, 8 ns TYPE IOL (SINK CURRENT) IOH (SOURCE
SN74ALVCHR BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process UBT (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in
MC3487 QUADRUPLE DIFFERENTIAL LINE DRIVER
Meets or Exceeds Requirements of ANSI EIA/TIA-422-B and ITU Recommendation V. -State, TTL-Compatible s Fast Transition Times High-Impedance Inputs Single -V Supply Power-Up and Power-Down Protection Designed
SN5407, SN5417, SN7407, SN7417 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
Converts TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays s Fully Compatible With Most TTL Circuits
AM26LS31 QUADRUPLE DIFFERENTIAL LINE DRIVER
AM6LS SLLSG JANUARY 979 REVISED FEBRUARY Meets or Exceeds the Requirements of ANSI TIA/EIA--B and ITU Recommendation V. Operates From a Single -V Supply TTL Compatible Complementary Outputs High Output
PI3C V/3.3V, High Bandwidth, Hot Insertion 10-Bit, 2-Port, Bus Switch
2.5V/3., High Bandwidth, Hot Insertion Features Near-Zero propagation delay 5-ohm switches connect inputs to outputs High Bandwidth (>400 MHz) Permits Hot Insertion. Rail-to-Rail, 3. or 2.5V ing 5V I/O
SN54HC365, SN74HC365 HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
High-Current -State s Drive Bus Lines, Buffer Memory Address Registers, or Drive up to LSTTL Loads True s Package Options Include Plastic Small-Outline (D) and Ceramic Flat (W) Packages, Ceramic Chip Carriers
ORDERING INFORMATION PACKAGE
Member of Texas Instruments Widebus Family Latch-Up Performance Exceeds 250 ma Per JESD 17 ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) Bus Hold on Data
Rad-hard 16-bit transceiver, 1.8 V to 3.3 V bidirectional level shifter. Description. Temp. range. Notes: (1) SMD = standard microcircuit drawing
Rad-hard 16-bit transceiver, 1.8 V to 3.3 V bidirectional level shifter Datasheet - production data Features Dual supply bidirectional level shifter Voltage range from 1.6 V to 3.6 V Separated enable pin
SN54HC373, SN74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
Eight High-Current Latches in a Single Package High-Current -State True s Can Drive up to LSTTL Loads Full Parallel Access for Loading Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline
description 1G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND V CC 2G/2G 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 1Y1 2A4 1Y2 2A3 1Y3 1A2 2Y3 1A3 2Y2 1A4 2A2 2G/2G 2Y1
SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244 3-State s Drive Bus Lines or Buffer Memory Address Registers PNP s Reduce DC Loading Hysteresis at s Improves Noise Margins description These
CDC LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS442B FEBRUARY 1994 REVISED NOVEMBER 1995
Low Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation pplications Operates at 3.3-V LVTTL-Compatible Inputs and s Supports Mixed-Mode Signal Operation (-V Input and Voltages With 3.3-V )
SN54HC245, SN74HC245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
High-Current -State s Drive Bus Lines Directly or up to LSTTL Loads Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages,
SN54LS06, SN74LS06, SN74LS16 HEX INVERTER BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays s Fully Compatible With Most TTL Circuits
SN54ACT16373, 74ACT BIT D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
Members of the Texas Itruments Widebus Family Inputs Are TTL-Voltage Compatible 3-State Bus Driving True s Full Parallel Access for Loading Flow-Through Architecture Optimizes PCB Layout Distributed and
SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving Outputs Full Parallel Access for Loading Buffered Control Inputs Clock-Enable Input Has Hysteresis to Improve
PO54G374A, PO74G374A
OCTAL EDGETRIGGERED DTYPE FLIPFLOP WITH 3STATE OUTPUTS FEATURES:. Patented technology. Specified From 40 C to 85 C, 40 C to 25 C, and 55 C to 25 C. Operating frequency is faster than 600MHz. VCC Operates
SN54LS07, SN74LS07, SN74LS17 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays description These hex buffers/drivers feature
SN54ALS688, SN74ALS688 8-BIT IDENTITY COMPARATORS
Compare Two -Bit Words Totem-Pole Outputs () ALS Are Identical to ALS2 Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J)
SN54ALS273, SN74ALS273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SDAS218A APRIL 1982 REVISED DECEMBER 1994
WITH CLEA SDAS2A APIL 2 EVISED DECEMBE 4 Contain Eight Flip-Flops With Single-ail Outputs Buffered Clock and Direct-Clear Inputs Individual Data Input to Each Flip-Flop Applications Include: Buffer/Storage
PO54G14A, PO74G14A. Pin Configuration. 54, 74 Series Noise Cancellation GHz Logic FEATURES: DESCRIPTION: V CC 6A 6Y 5A 5Y 4A 4Y 1A 1Y 2A 2Y 3A 3Y GND
FEATURES:. Patented technology. Operating frequency up to 1.125GHz with 2pf load. Operating frequency up to 680MHz with 5pf load. Operating frequency up to 300MHz with 15pf load. Operating frequency up
SN54HC373, SN74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS140B DECEMBER 1982 REVISED MAY 1997
Eight High-Current Latches in a Single Package High-Current -State True s Can Drive up to LSTTL Loads Full Parallel Access for Loading Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline
SN54ALS563B, SN74ALS563B OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
-State Buffer-Type s Drive Bus Lines Directly Bus-Structured Pinout Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), Standard Plastic (N) and Ceramic (J) 00-mil DIPs,
EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at ore.hu.
EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at www.hest ore.hu. Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping
LOW POWER SCHOTTKY. MARKING DIAGRAMS GUARANTEED OPERATING RANGES
The SN74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is
PO74G553A. Pin Configuration. Logic Block Diagram. Pin Description. 800MHz Noise Cancellation TTL/CMOS Potato Chip
FEATURES:. Patented technology. Operating frequency up to 800Mz with 2pf load. Operating frequency up to 600Mz with 5pf load. Operating frequency up to 300Mz with 15pf load. Operating frequency up to 150Mz
74AC11373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
74A7 Eight Latches in a Single Package -State Bus-Driving True s Full Parallel Access for Loading Buffered Control Inputs Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and Configuratio
description V CC 2CLR 2D 2CLK 2PRE 2Q 2Q 1CLR 1D 1CLK 1PRE 1Q 1Q GND 2CLR 1CLR 1CLK NC 1PRE NC 1Q 2CLK 2PRE GND
Package Optio Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs TYPE TYPICAL MAXIMUM CLOCK FREUEY (CL = 0 pf) (MHz) TYPICAL POWER
SN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
Package Optio Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs TYPE TYPICAL MAXIMUM CLOCK FREUEY (CL = 0 pf) (MHz) TYPICAL POWER
SN54AHCT174, SN74AHCT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR
Inputs Are TTL-Voltage Compatible EPIC (Enhanced-Performance Implanted CMOS) Process Contain Six Flip-Flops With Single-Rail s Applicatio Include: Buffer/Storage Registers Shift Registers Pattern Generators
54AC16245, 74AC BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
4AC64, 74AC64 6-BIT BUS TRANSCEIVERS SCAS3A MARCH 990 REVISED APRIL 996 Members of the Texas Itruments Widebus Family 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Flow-Through Architecture
ORDERING INFORMATION PACKAGE
Member of Texas Instruments Widebus Family Latch-Up Performance Exceeds 250 ma Per JESD 17 description This 16-bit (dual-octal) noninverting bus transceiver contains two separate supply rails; B port has