3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 5 VOLT TOLERANT I/O AND BUS-HOLD
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1 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 5 T TOLERANT I/O AND BUS-HOLD IDT74LVCH162245A FEATURES: Typical tsk(o) (Output Skew) < 250ps ESD > 200 per MIL-STD-883, Method 3015; > 20 using machine model (C = 200pF, R = 0) = 3.3V ± 0.3V, Normal Range = 2.7V to 3.6V, Extended Range CMOS power levels (0.4μ W typ. static) All inputs, outputs, and I/O are 5V tolerant Available in TSSOP package DRIVE FEATURES: Balanced Output Drivers: ±12mA (A port) High Output Drivers: ±24mA (B port) APPLICATIONS: 5V and 3.3V mixed voltage systems Data communication and telecommunication systems DESCRIPTION: This 16-bit bus transceiver is built using advanced dual metal CMOS technology. This high-speed, low power transceiver is ideal for asynchronous communication between two busses (A and B). The Direction and Output Enable controls are designed to operate this device as either two independent 8-bit transceivers or one 16-bit transceiver. The direction control pin (DIR) controls the direction of data flow. The output enable pin (OE) overrides the direction control and disables both ports. All inputs are designed with hysteresis for improved noise margin. All pins can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system. The LVCH162245A (B port) has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. The LVCH (A port) has series resistors in the device output structure which will significantly reduce line noise when used with light loads. The driver has been designed to drive ±12mA at the designated threshold levels. The LVCH162245A has bus-hold which retains the inputs last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors. FUNCTIONAL BLOCK DIAGRAM 1DIR DIR 47 1A OE 1B1 36 2A OE 2B1 46 1A2 44 1A3 43 1A4 41 1A5 40 1A B2 1B3 1B4 1B5 1B6 35 2A2 33 2A3 32 2A4 30 2A5 29 2A B2 2B3 2B4 2B5 2B6 38 1A7 11 1B7 2A B7 37 1A8 26 2A8 12 1B8 23 2B8 The IDT logo is a registered trademark of Integrated Device Technology, Inc. 1 OCTOBER Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-4597/5
2 PIN CONFIGURATION 1DIR 1B1 1B2 1B3 1B4 1B OE 1A1 1A2 1A3 1A4 1A5 ABSOLUTE MAXIMUM RATINGS (1) Symbol Description Max Unit ERM Terminal Voltage with Respect to 0.5 to +6.5 V TSTG Storage Temperature 65 to +150 C IOUT DC Output Current 50 to +50 ma IIK Continuous Clamp Current, 50 ma IOK VI < 0 or VO < 0 ICC Continuous Current through each ±100 ma ISS or 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 1B6 1B7 1B8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 2DIR A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 2OE CAPACITANCE (TA = +25 C, F = 1.0MHz) Symbol Parameter (1) Conditions Typ. Max. Unit CIN Input Capacitance VIN = pf COUT Output Capacitance VOUT = pf CI/O I/O Port Capacitance VIN = pf 1. As applicable to the device type. PIN DESCRIPTION Pin Names Description xoe Output Enable Input (Active LOW) xdir 1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os. FUNCTION TABLE (EACH 8-BIT SECTION) (1) Inputs Direction Control Output x A x Side A Inputs or 3-State Outputs (1) x B x Side B Inputs or 3-State Outputs (1) TSSOP TOP VIEW xoe xdir Outputs L L B Data to A Bus L H A Data to B Bus H X High Z State 1. H = HIGH Voltage Level X = Don t Care L = LOW Voltage Level Z = High-Impedance 2
3 DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 40 C to +85 C Symbol Parameter Test Conditions Min. Typ. (1) Max. Unit Input HIGH Voltage Level = 2.3V to 2.7V 1.7 V = 2.7V to 3.6V 2 VIL Input LOW Voltage Level = 2.3V to 2.7V 0.7 V = 2.7V to 3.6V 0.8 IIH Input Leakage Current = 3.6V VI = 0 to 5.5V ±5 μa IIL IOZH High Impedance Output Current = 3.6V VO = 0 to 5.5V ±10 μa IOZL (3-State Output pins) IOFF Input/Output Power Off Leakage =, VIN or VO 5.5V ±50 μa VIK Clamp Diode Voltage = 2.3V, IIN = 18mA V VH Input Hysteresis = 3.3V 100 mv ICCL Quiescent Power Supply Current = 3.6V VIN = or 10 μa ICCH ICCZ 3.6 VIN 5.5V (2) 10 ΔICC Quiescent Power Supply Current One input at - 0.6V, other inputs at or 500 μa Variation 1. Typical values are at = 3.3V, +25 C ambient. 2. This applies in the disabled state only. BUS-HOLD CHARACTERISTICS Symbol Parameter (1) Test Conditions Min. Typ. (2) Max. Unit IBHH Bus-Hold Input Sustain Current = 3V VI = 2V 75 μa IBHL VI = 0.8V 75 IBHH Bus-Hold Input Sustain Current = 2.3V VI = 1.7V μa IBHL VI = 0.7V IBHHO Bus-Hold Input Overdrive Current = 3.6V VI = 0 to 3.6V ±500 μa IBHLO 1. Pins with Bus-Hold are identified in the pin description. 2. Typical values are at = 3.3V, +25 C ambient. 3
4 OUTPUT DRIVE CHARACTERISTICS (A PORT) Symbol Parameter Test Conditions (1) Min. Max. Unit Output HIGH Voltage = 2.3V to 3.6V IOH = 0.1mA 0.2 V = 2.3V IOH = 4mA 1.9 IOH = 6mA 1.7 = 2.7V IOH = 4mA 2.2 IOH = 8mA 2 = 3V IOH = 6mA 2.4 IOH = 12mA 2 Output LOW Voltage = 2.3V to 3.6V IOL = 0.1mA 0.2 V = 2.3V IOL = 4mA 0.4 IOL = 6mA 0.55 = 2.7V IOL = 4mA 0.4 IOL = 8mA 0.6 = 3V IOL = 6mA 0.55 IOL = 12mA and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate range. TA = 40 C to + 85 C. OUTPUT DRIVE CHARACTERISTICS (B PORT) Symbol Parameter Test Conditions (1) Min. Max. Unit Output HIGH Voltage = 2.3V to 3.6V IOH = 0.1mA 0.2 V = 2.3V IOH = 6mA 2 = 2.3V IOH = 12mA 1.7 = 2.7V 2.2 = 3V 2.4 = 3V IOH = 24mA 2 Output LOW Voltage = 2.3V to 3.6V IOL = 0.1mA 0.2 V = 2.3V IOL = 6mA 0.4 IOL = 12mA 0.7 = 2.7V IOL = 12mA 0.4 = 3V IOL = 24mA and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate range. TA = 40 C to + 85 C. 4
5 OPERATING CHARACTERISTICS, = 3.3V ± 0.3V, TA = 25 C Symbol Parameter Test Conditions Typical Unit CPD Power Dissipation Capacitance per Transceiver Outputs enabled CL = 0pF, f = 10Mhz 39 pf CPD Power Dissipation Capacitance per Transceiver Outputs disabled 4 SWITCHING CHARACTERISTICS (A PORT) (1) = 2.7V = 3.3V ± 0.3V Symbol Parameter Min. Max. Min. Max. Unit tplh Propagation Delay ns xbx to xax tpzh Output Enable Time ns tpzl xoe to xax tphz Output Disable Time ns tplz xoe to xax tsk(o) Output Skew (2) 500 ps 1. See TEST CIRCUITS AND WAVEFORMS. TA = 40 C to + 85 C. 2. Skew between any two outputs of the same package and switching in the same direction. SWITCHING CHARACTERISTICS (B PORT) (1) = 2.7V = 3.3V ± 0.3V Symbol Parameter Min. Max. Min. Max. Unit tplh Propagation Delay ns xax to xbx tpzh Output Enable Time ns tpzl xoe to xbx tphz Output Disable Time ns tplz xoe to xbx tsk(o) Output Skew (2) 500 ps 1. See TEST CIRCUITS AND WAVEFORMS. TA = 40 C to + 85 C. 2. Skew between any two outputs of the same package and switching in the same direction. 5
6 TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS Symbol (1) = 3.3V±0.3V (1) = 2.7V (2) = 2.5V±0.2V Unit VLOAD x Vcc V Vcc V Vcc / 2 V VLZ mv VHZ mv CL pf Pulse Generator (1, 2) VIN RT D.U.T. VOUT CL Test Circuit for All Outputs DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 1. Pulse Generator for All Pulses: Rate 10MHz; tf 2.5ns; tr 2.5ns. 2. Pulse Generator for All Pulses: Rate 10MHz; tf 2ns; tr 2ns. VLOAD Open SAME PHASE TRANSITION OUTPUT OPPOSITE PHASE TRANSITION CONTROL tplh tplh OUTPUT SWITCH NORMALLY CLOSED LOW tpzh OUTPUT NORMALLY HIGH Propagation Delay ENABLE tpzl SWITCH OPEN VLOAD/2 DISABLE tphz tplz VLOAD/2 +VLZ -VHZ Enable and Disable Times 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. SWITCH POSITION Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests OUTPUT 1 OUTPUT 2 tplh1 tplh2 tsk (x) 1 2 tsk (x) tsk(x) = tplh2 - tplh1 or 2-1 Output Skew - tsk(x) Switch VLOAD 1. For tsk(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tsk(b) OUTPUT1 and OUTPUT2 are in the same bank. Open 6 DATA TIMING ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL LOW-HIGH-LOW PULSE HIGH-LOW-HIGH PULSE tsu tsu trem tw th th Set-up, Hold, and Release Times Pulse Width
7 ORDERING INFORMATION XX LVC X XX XXXX XX Temp. Range Bus-Hold Family Device Type Package X Blank 8 PAG PFG Tube or Tray Tape and Reel Thin Shrink Small Outline Package - Green Thin Very Small Outline Package - Green 245A 162 H Bit Bus Transceiver Double-Density with Resistors, ±24mA (B Port) ±12mA (A Port) Bus-hold -40 C to +85 C DATASHEET DOCUMENT HISTORY 10/06/2015 Pg. 1,2, 7 Updated the ordering information by removing IDT notation, non RoHS parts and adding Tape and Reel information. CORPORATE HEADQUARTERS for SALES: for Tech Support: 6024 Silver Creek Valley Road or logichelp@idt.com San Jose, CA fax:
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