SN54ALS563B, SN74ALS563B OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
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1 -State Buffer-Type s Drive Bus Lines Directly Bus-Structured Pinout Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), Standard Plastic (N) and Ceramic (J) 00-mil DIPs, and Ceramic Flat (W) Packages description These -bit D-type traparent latches feature -state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable () input is high, the outputs follow the complements of data (D) inputs. When is taken low, the outputs are latched at the inverses of the levels set up at the D inputs. A buffered output-enable () input places the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased high logic level provide the capability to drive bus lines without interface or pullup components. SNALSB, SNALSB does not affect internal operatio of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SNALSB is characterized for operation over the full military temperature range of C to C. The SNALSB is characterized for operation from 0 C to 0 C. FUNCTION TAB (each latch) INPUTS OUTPUT D L H H L L H H H L L X 0 H X X Z SNALSB...J OR W PACKAGE SNALSB... DW OR N PACKAGE (TOP VIEW) D D D D D GND V CC SNALSB... FK PACKAGE (TOP VIEW) D D D D V CC D GND PRODUCTION DATA information is current as of publication date. Products conform to specificatio per the terms of Texas Itruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 99, Texas Itruments Incorporated POST OFFICE BOX 0 DALLAS, TEXAS
2 SNALSB, SNALSB logic symbol logic diagram (positive logic) D D D D D 9 EN C 9 C To Seven Other Channels 9 This symbol is in accordance with ANSI/IEEE Std 9-9 and IEC Publication -. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC V voltage, V I V Voltage applied to a disabled -state output V Operating free-air temperature range, T A : SNALSB C to C SNALSB C to 0 C Storage temperature range C to 0 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. recommended operating conditio SNALSB SNALSB MIN NOM MAX MIN NOM MAX VCC Supply voltage.... V VIH High-level input voltage V VIL Low-level input voltage V IOH High-level output current. ma IOL Low-level output current ma tw Pulse duration, high tsu Setup time, data before 0 0 th Hold time, data after 0 TA Operating free-air temperature 0 0 C POST OFFICE BOX 0 DALLAS, TEXAS
3 SNALSB, SNALSB electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SNALSB SNALSB MIN TYP MAX MIN TYP MAX VIK VCC =. V, II = ma.. V VCC =. V to. V, IOH = 0. ma VCC VCC VCC =V. VCC =V. IOH = ma.. V IOH =. ma.. IOL = ma IOL = ma IOZH VCC =. V, VO =. V 0 0 µa IOZL VCC =. V, VO = 0. V 0 0 µa II VCC =. V, VI = V ma IIH VCC =. V, VI =. V 0 0 µa IIL VCC =. V, VI = 0. V ma IO VCC =. V, VO =. V 0 0 ma s high 0 0 ICC VCC =. V s low ma s disabled 9 9 All typical values are at VCC = V, TA = C. The output conditio have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. switching characteristics (see Figure ) V PARAMETER FROM (INPUT) TO (OUTPUT) VCC =. V to. V, = 0 pf, R = 00 Ω, R = 00 Ω, TA = MIN to MAX SNALSB SNALSB MIN MAX MIN MAX D 9 tpzh tpzl tphz 0 tplz For conditio shown as MIN or MAX, use the appropriate value specified under recommended operating conditio. POST OFFICE BOX 0 DALLAS, TEXAS
4 SNALSB, SNALSB PARAMETER MEASUREMENT INFORMATION SERIES ALS/ALS AND AS/AS DEVICES VCC V RL = R = R S RL Under RL Under Under R R LOAD CIRCUIT FOR BI-STATE TOTEM-PO OUTPUTS LOAD CIRCUIT FOR OPEN-COLCTOR OUTPUTS LOAD CIRCUIT FOR -STATE OUTPUTS Timing High-Level Pulse Data tsu th Low-Level Pulse tw SETUP AND HOLD TIMES PULSE DURATIONS Control (low-level enabling) Waveform S Closed (see Note B) Waveform S Open (see Note B) tpzl tpzh tphz tplz ENAB AND DISAB TIMES, -STATE OUTPUTS 0 V In-Phase Out-of-Phase (see Note C) PROPAGATION DELAY TIMES NOTES: A. includes probe and jig capacitance. B. Waveform is for an output with internal conditio such that the output is low except when disabled by the output control. Waveform is for an output with internal conditio such that the output is high except when disabled by the output control. C. When measuring propagation delay items of -state outputs, switch S is open. D. All input pulses have the following characteristics: PRR MHz, tr = tf =, duty cycle = 0%. E. The outputs are measured one at a time with one traition per measurement. Figure. Load Circuits and Voltage Waveforms POST OFFICE BOX 0 DALLAS, TEXAS
5 IMPORTANT NOTICE Texas Itruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditio of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specificatio applicable at the time of sale in accordance with TI s standard warranty. ing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ( CRITICAL APPLICATIONS ). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITAB FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK. In order to minimize risks associated with the customer s applicatio, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applicatio assistance or customer product design. TI does not warrant or represent that any licee, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not cotitute TI s approval, warranty or endorsement thereof. Copyright 99, Texas Itruments Incorporated
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Meets or Exceeds the Requirements of ANSI Standards EIA/TIA-422-B and EIA/TIA-423-B and ITU Recommendations V.10 and V.11 3-State, TTL-Compatible s Fast Transition Times Operates From Single 5-V Supply
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Inputs Are TTL-Voltage ompatible EPI (Enhanced-Performance Implanted MOS) Process ontain Eight Flip-Flops With Single-ail s Direct lear Input Individual Data Input to Each Flip-Flop Applicatio Include:
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Typical V OLP ( Ground Bounce) 2 V at V CC = 3.3 V, T A = 25 C s Accept Voltages to 5.5 V Latch-Up Performance Exceeds 100 ma Per JESD
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EPIC (Enhanced-Performance Implanted CMOS) Process Operating Range 2-V to 5.5-V V CC Schmitt-Trigger Circuitry On A, B, and CLR Inputs for Slow Input Traition Rates Edge Triggered From Active-High or Active-Low
More informationDistributed by: www.jameco.com 1-800-81-4242 The content and copyrights of the attached material are the property of its owner. Operating Range 2-V to.-v V CC Latch-Up Performance Exceeds 20 ma Per JESD
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Inputs Are TTL-Voltage Compatible Contain Six Flip-Flops With Single-Rail s Applicatio Include: Buffer/Storage Registers Shift Registers Pattern Generators Latch-Up Performance Exceeds 250 ma Per JESD
More informationEN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at ore.hu.
EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at www.hest ore.hu. Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping
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