SN54ALS86, SN54AS86A, SN74ALS86, SN74AS86A QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
|
|
- Frank Henry
- 5 years ago
- Views:
Transcription
1 Package Optio Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These devices contain four independent 2-input exclusive-or gates. They perform the Boolean functio = A B or = AB + AB in positive logic. A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the output. The SN4ALS86 and SN4AS86A are characterized for operation over the full military temperature range of C to 12 C. The SN74ALS86 and SN74AS86A are characterized for operation from 0 C to 70 C. FUTION TABLE (each gate) INPUTS OUTPUT A B L L L L H H H L H H H L SN4ALS86, SN4AS86A...J PACKAGE SN74ALS86, SN74AS86A...D OR N PACKAGE (TOP VIEW) 1A 1B 1 2A 2B 2 GND V CC 4B 4A 4 B A SN4ALS86, SN4AS86A... FK PACKAGE (TOP VIEW) 1 2A 2B 1B 1A GND V CC 4B A No internal connection 4A 4 B logic symbol 1 1A 2 1B 4 2A 2B 9 A 10 B 12 4A 1 4B = This symbol is in accordance with ANSI/IEEE Std and IEC Publication Pin numbers shown are for the D, J, and N packages. PRODUCTION DATA information is current as of publication date. Products conform to specificatio per the terms of Texas Itruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 1994, Texas Itruments Incorporated POST OFFICE BOX 60 DALLAS, TEXAS 726 1
2 exclusive-or logic An exclusive-or gate has many applicatio, some of which can be represented better by alternative logic symbols. = 1 EXCLUSIVE-OR These are five equivalent exclusive-or symbols valid for an ALS86 or AS86A gate in positive logic. Negation may be shown at any two ports. LOGIC-IDENTIT ELEMENT EVEN-PARIT ELEMENT ODD-PARIT ELEMENT = 2k 2k + 1 The output is active (low) if all inputs are at the same logic level (i.e., A = B). The output is active (low) if an even number of inputs (i.e., 0 or 2) are active. The output is active (high) if an odd number of inputs (i.e., only 1 of the 2) are active. 2 POST OFFICE BOX 60 DALLAS, TEXAS 726
3 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC V Input voltage, V I V Operating free-air temperature range, T A : SN4ALS C to 12 C SN74ALS C to 70 C Storage temperature range C to 10 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. recommended operating conditio SN4ALS86 SN74ALS86 MIN NOM MAX MIN NOM MAX VCC Supply voltage V VIH High-level input voltage 2 2 V VIL Low-level input voltage V IOH High-level output current ma IOL Low-level output current 4 8 ma TA Operating free-air temperature C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS SN4ALS86 SN74ALS86 MIN TP MAX MIN TP MAX VIK VCC = 4. V, II = 18 ma V VOH VCC = 4. V to. V, IOH = 0.4 ma VCC 2 VCC 2 V VCC =4V 4. IOL = 4 ma IOL = 8 ma II VCC =. V, VI = 7 V ma IIH VCC =. V, VI = 2.7 V µa IIL VCC =. V, VI = 0.4 V ma IO VCC =. V, VO = 2.2 V ma ICC VCC =. V, All inputs at 4. V ma All typical values are at VCC = V, TA = 2 C. The output conditio have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. switching characteristics (see Figure 1) V FROM (INPUT) TO (OUTPUT) VCC = 4. V to. V, CL = 0 pf, RL = 00 Ω, TA = MIN to MAX SN4ALS86 SN74ALS86 MIN MAX MIN MAX (other input low) (other input high) For conditio shown as MIN or MAX, use the appropriate value specified under recommended operating conditio. POST OFFICE BOX 60 DALLAS, TEXAS 726
4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC V Input voltage, V I V Operating free-air temperature range, T A : SN4AS86A C to 12 C SN74AS86A C to 70 C Storage temperature range C to 10 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. recommended operating conditio SN4AS86A SN74AS86A MIN NOM MAX MIN NOM MAX VCC Supply voltage V VIH High-level input voltage 2 2 V VIL Low-level input voltage V IOH High-level output current 2 2 ma IOL Low-level output current ma TA Operating free-air temperature C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS SN4AS86A SN74AS86A MIN TP MAX MIN TP MAX VIK VCC = 4. V, II = 18 ma V VOH VCC = 4. V to. V, IOH = 2 ma VCC 2 VCC 2 V VCC = 4. V, IOL = 20 ma V II VCC =. V, VI = 7 V ma IIH VCC =. V, VI = 2.7 V µa IIL VCC =. V, VI = 0.4 V ma IO VCC =. V, VO = 2.2 V ma ICCH VCC =. V, VI(A) = 4. V, VI(B) = ma ICCL VCC =. V, VI = 4. V ma All typical values are at VCC = V, TA = 2 C. The output conditio have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. switching characteristics (see Figure 1) FROM (INPUT) TO (OUTPUT) VCC = 4. V to. V, CL = 0 pf, RL = 00 Ω, TA = MIN to MAX SN4AS86A SN74AS86A MIN MAX MIN MAX (other input low) (other input high) For conditio shown as MIN or MAX, use the appropriate value specified under recommended operating conditio. 4 POST OFFICE BOX 60 DALLAS, TEXAS 726
5 MEASUREMENT INFORMATION SERIES 4ALS/74ALS AND 4AS/74AS DEVICES VCC 7 V RL = R1 = R2 S1 RL From Output Under Test CL (see Note A) RL Test Point From Output Under Test CL (see Note A) Test Point From Output Under Test CL (see Note A) R1 R2 Test Point LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS LOAD CIRCUIT FOR -STATE OUTPUTS Timing Input 1. V. V 0. V High-Level Pulse 1. V 1. V. V 0. V Data Input tsu 1. V th 1. V. V 0. V Low-Level Pulse tw 1. V 1. V. V 0. V TAGE WAVEFORMS SETUP AND HOLD TIMES TAGE WAVEFORMS PULSE DURATIONS Output Control (low-level enabling) Waveform 1 S1 Closed (see Note B) tpzl 1. V 1. V tphz 1. V tplz. V 0. V. V 0. V tpzh Waveform 2 VOH S1 Open 1. V 0. V (see Note B) 0 V TAGE WAVEFORMS ENABLE AND DISABLE TIMES, -STATE OUTPUTS Input In-Phase Output Out-of-Phase Output (see Note C) 1. V 1. V 1. V. V 0. V VOH 1. V VOH 1. V 1. V TAGE WAVEFORMS PROPAGATION DELA TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditio such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditio such that the output is high except when disabled by the output control. C. When measuring propagation delay items of -state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR 1 MHz, tr = tf = 2, duty cycle = 0%. E. The outputs are measured one at a time with one traition per measurement. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 60 DALLAS, TEXAS 726
6 IMPORTANT NOTICE Texas Itruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditio of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specificatio applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MA INVE POTENTIAL RISKS OF DEATH, PERSONAL INJUR, OR SEVERE PROPERT OR ENVIRONMENTAL DAMAGE ( CRITICAL APPLICATIONS ). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SSTEMS OR OTHER CRITICAL APPLICATIONS. ILUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULL AT THE CUSTOMER S RISK. In order to minimize risks associated with the customer s applicatio, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applicatio assistance or customer product design. TI does not warrant or represent that any licee, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not cotitute TI s approval, warranty or endorsement thereof. Copyright 1998, Texas Itruments Incorporated
SN54ALS08, SN54AS08, SN74ALS08, SN74AS08 QUADRUPLE 2-INPUT POSITIVE-AND GATES
SNALS0, SNAS0, SN7ALS0, SN7AS0 Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These devices contain
More informationSN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
Package Optio Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs TYPE TYPICAL MAXIMUM CLOCK FREUEY (CL = 0 pf) (MHz) TYPICAL POWER
More informationSN54AS825A, SN74AS825A 8-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS020B JUNE 1984 REVISED AUGUST 1995
Functionally Equivalent to AMD s AM2982 Improved I OH Specificatio Multiple Output Enables Allow Multiuser Control of the Interface Outputs Have Undershoot-Protection Circuitry Power-Up High-Impedance
More informationSN54ALS00A, SN54AS00, SN74ALS00A, SN74AS00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES
Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These devices contain four independent 2-input positive-nand
More informationdescription V CC 2CLR 2D 2CLK 2PRE 2Q 2Q 1CLR 1D 1CLK 1PRE 1Q 1Q GND 2CLR 1CLR 1CLK NC 1PRE NC 1Q 2CLK 2PRE GND
Package Optio Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs TYPE TYPICAL MAXIMUM CLOCK FREUEY (CL = 0 pf) (MHz) TYPICAL POWER
More informationSN54ALS873B, SN54AS873A, SN74ALS873B, SN74AS873A DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS036D APRIL 1982 REVISED AUGUST 1995
3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs
More informationSN54ALS563B, SN74ALS563B OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
-State Buffer-Type s Drive Bus Lines Directly Bus-Structured Pinout Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), Standard Plastic (N) and Ceramic (J) 00-mil DIPs,
More informationSN54ALS244C, SN54AS244A, SN74ALS244C, SN74AS244A OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
SNALS2C, SNAS2A, SNALS2C, SNAS2A SDAS2C JUL 9 REISED AUGUST 99 -State Outputs Drive Bus Lines or Buffer Memory Address Registers pnp Inputs Reduce dc Loading Package Optio Include Plastic Small-Outline
More informationSN54ALS873B, SN54AS873A, SN74ALS873B, SN74AS873A DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS036D APRIL 1982 REVISED AUGUST 1995
3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs
More informationSN54ALS688, SN74ALS688 8-BIT IDENTITY COMPARATORS
Compare Two -Bit Words Totem-Pole Outputs () ALS Are Identical to ALS2 Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J)
More information54AC11241, 74AC11241 OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS
SCAS032A JUL 187 REVISED APRIL 13 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and Configuratio Minimize High-Speed
More informationSN5407, SN5417, SN7407, SN7417 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
Converts TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays s Fully Compatible With Most TTL Circuits
More information54ACT11109, 74ACT11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and GND Configuratio Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-µm
More informationSN54AHCT174, SN74AHCT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR
Inputs Are TTL-Voltage Compatible EPIC (Enhanced-Performance Implanted CMOS) Process Contain Six Flip-Flops With Single-Rail s Applicatio Include: Buffer/Storage Registers Shift Registers Pattern Generators
More informationSN54ACT241, SN74ACT241 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
Inputs Are TTL Compatible EPIC (Enhanced-Performance Implanted CMOS) -µm Process Package Optio Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and DIP (N)
More information74AC11373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
74A7 Eight Latches in a Single Package -State Bus-Driving True s Full Parallel Access for Loading Buffered Control Inputs Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and Configuratio
More informationSN54HCT373, SN74HCT373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
Inputs Are TTL-Voltage Compatible Eight High-Current Latches in a Single Package High-Current -State True s Can Drive up to LSTTL Loads Full Parallel Access for Loading Package Optio Include Plastic Small-Outline
More information54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES
Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-Pin V CC and GND Configurations to Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS)
More informationSN5407, SN5417, SN7407, SN7417 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS SDLS032A DECEMBER 1983 REVISED NOVEMBER 1997
Converts TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays s Fully Compatible With Most TTL Circuits
More informationSN54ALS273, SN74ALS273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR
WITH CLEA SDAS2A APIL 92 EVISED DECEMBE 99 Contain Eight Flip-Flops With Single-ail Outputs Buffered Clock and Direct-Clear Inputs Individual Data Input to Each Flip-Flop Applications Include: Buffer/Storage
More informationSN54ACT00, SN74ACT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCAS AUGUST 99 REVISED MAY 99 Inputs Are TTL-Voltage Compatible EPIC (Enhanced-Performance Implanted CMOS) -µm Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin
More informationSN54ALS244C, SN54AS244A, SN74ALS244C, SN74AS244A OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
SNALS2C, SNAS2A, SNALS2C, SNAS2A SDAS2C JUL 9 REISED AUGUST 99 -State Outputs Drive Bus Lines or Buffer Memory Address Registers pnp Inputs Reduce dc Loading Package Optio Include Plastic Small-Outline
More informationSN54ACT16373, 74ACT BIT D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
Members of the Texas Itruments Widebus Family Inputs Are TTL-Voltage Compatible 3-State Bus Driving True s Full Parallel Access for Loading Flow-Through Architecture Optimizes PCB Layout Distributed and
More informationSN54HC365, SN74HC365 HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
High-Current -State s Drive Bus Lines, Buffer Memory Address Registers, or Drive up to LSTTL Loads True s Package Options Include Plastic Small-Outline (D) and Ceramic Flat (W) Packages, Ceramic Chip Carriers
More informationSN54HC175, SN74HC175 QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
Contain Four Flip-Flops With Double-Rail Outputs Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators Package Options Include Plastic Small-Outline (D), Thin Shrink Small-Outline
More information54AC16245, 74AC BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
4AC64, 74AC64 6-BIT BUS TRANSCEIVERS SCAS3A MARCH 990 REVISED APRIL 996 Members of the Texas Itruments Widebus Family 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Flow-Through Architecture
More informationSN54AHCT132, SN74AHCT132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS
Inputs Are TTL-oltage Compatible EPIC (Enhanced-Performance Implanted CMOS) Process Operation From ery Slow Input Traitio Temperature-Compeated Threshold Levels High Noise Immunity Same Pinouts as AHCT00
More informationSN54ALS273, SN74ALS273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SDAS218A APRIL 1982 REVISED DECEMBER 1994
WITH CLEA SDAS2A APIL 2 EVISED DECEMBE 4 Contain Eight Flip-Flops With Single-ail Outputs Buffered Clock and Direct-Clear Inputs Individual Data Input to Each Flip-Flop Applications Include: Buffer/Storage
More informationMC3487 QUADRUPLE DIFFERENTIAL LINE DRIVER
Meets or Exceeds Requirements of ANSI EIA/TIA-422-B and ITU Recommendation V. -State, TTL-Compatible s Fast Transition Times High-Impedance Inputs Single -V Supply Power-Up and Power-Down Protection Designed
More information54AC11533, 74AC11533 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
5A1533, 7A1533 TAL D-TYPE TRANSPARENT LATHES SAS00 D257, JULY 187 REVISED APRIL 13 8-Latches in a Single Package 3-State Bus-Driving Inverting s Full Parallel Access for Loading Buffered ontrol Inputs
More informationSN54HC373, SN74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
Eight High-Current Latches in a Single Package High-Current -State True s Can Drive up to LSTTL Loads Full Parallel Access for Loading Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline
More informationSN54HC245, SN74HC245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
High-Current -State s Drive Bus Lines Directly or up to LSTTL Loads Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages,
More informationSN54HC00, SN74HC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES
Package Options Include Plastic Small-Outline (D), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description
More informationPRODUCT PREVIEW SN54AHCT257, SN74AHCT257 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS. description
Inputs Are TTL-Voltage Compatible EPIC (Enhanced-Performance Implanted CMOS) Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), Thin Shrink
More information74ACT11652 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
74ACT62 Independent Registers and Enables for A and B Buses Multiplexed Real-Time and Stored Data Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and Configuratio Minimize High-Speed Switching
More informationSN55451B, SN55452B, SN55453B, SN55454B SN75451B, SN75452B, SN75453B, SN75454B DUAL PERIPHERAL DRIVERS
PERIPHERAL DRIVERS FOR HIGH-CURRENT SWITCHING AT VERY HIGH SPEEDS Characterized for Use to 00 ma High-Voltage Outputs No Output Latch-Up at 0 V (After Conducting 00 ma) High-Speed Switching Circuit Flexibility
More informationSN54HC377, SN74HC377 OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE
Eight Flip-Flops With Single-Rail Outputs Clock Enable Latched to Avoid False Clocking Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators Package Options Include Plastic
More informationSN74S ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH 3-STATE OUTPUTS
Independent Asychronous Inputs and Outputs 16 Words by 5 Bits DC to 10-MHz Rate 3-State Outputs Packaged in Standard Plastic 300-mil DIPs description This 80-bit active-element memory is a monolithic Schottky-clamped
More information74ACT11374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
Eight D-Type Flip-Flops in a Single Package -State Bus Driving True s Full Parallel Access for Loading Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and
More informationSN54HC373, SN74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS140B DECEMBER 1982 REVISED MAY 1997
Eight High-Current Latches in a Single Package High-Current -State True s Can Drive up to LSTTL Loads Full Parallel Access for Loading Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline
More informationCDC337 CLOCK DRIVER WITH 3-STATE OUTPUTS
Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and CMOS-Compatible Outputs Distributes One Clock Input to Eight Outputs Four Same-Frequency
More informationSN74ACT STROBED FIRST-IN, FIRST-OUT MEMORY
Member of the Texas Itruments idebus Family Load Clock and Unload Clock Can Be Asynchronous or Coincident 256 ords by 18 Bits Low-Power Advanced CMOS Technology Full, Empty, and Half-Full Flags Programmable
More informationSN54HC573A, SN74HC573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS147B DECEMBER 1982 REVISED MAY 1997
High-Current -State s Drive Bus Lines Directly or up to LSTTL Loads Bus-Structured Pinout Package Options Include Plastic Small-Outline (DW) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and
More informationSN54HC132, SN74HC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS
Operation From Very Slow Input Transitions Temperature-Compensated Threshold Levels High Noise Immunity Same Pinouts as HC00 Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB),
More informationSN54F74, SN74F74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
WITH LEAR AND PRESET SDFS0A MARH 197 REVISED OTOBER 199 Package Optio Include Plastic Small-Outline Packages, eramic hip arriers, and Standard Plastic and eramic 00-mil DIPs description These devices contain
More informationSN75158 DUAL DIFFERENTIAL LINE DRIVER
SN78 Meets or Exceeds the Requirements of ANSI EIA/TIA--B and ITU Recommendation V. Single -V Supply Balanced-Line Operation TTL Compatible High Output Impedance in Power-Off Condition High-Current Active-Pullup
More information74AC11873 DUAL 4-BIT D-TYPE LATCH WITH 3-STATE OUTPUTS SCAS095 JANUARY 1990 REVISED APRIL 1993
3-State Buffer-Type s Drive Bus Lines Directly Bus-Structured Pinout Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and Configuratio Minimize High-Speed Switching Noise EPIC (Enhanced-Performance
More informationSN54HC04, SN74HC04 HEX INVERTERS
SCLS07B DECEMBER 92 REVISED MAY 997 Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK),
More informationSN74ALVCH V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 200 Per MIL-STD-883, Method 3015; Exceeds 20 Using Machine Model (C =
More informationSN74LVC1G06 SINGLE INVERTER BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT
and Open-Drain Accept Voltages up to 5.5 V Supports 5-V V CC Operation description This single inverter buffer/driver is designed for 1.65-V to 5.5-V V CC operation. DBV OR DCK PACKAGE (TOP VIEW) NC A
More informationua9637ac DUAL DIFFERENTIAL LINE RECEIVER
ua967ac Meets or Exceeds the Requirements of ANSI Standards EIA/TIA--B and EIA/TIA--B and ITU Recommendations V. and V. Operates From Single -V Power Supply Wide Common-Mode Voltage Range High Input Impedance
More informationSN QUADRUPLE HALF-H DRIVER
-A -Current Capability Per Driver Applications Include Half-H and Full-H Solenoid Drivers and Motor Drivers Designed for Positive-Supply Applications Wide Supply-Voltage Range of 4.5 V to 6 V TTL- and
More informationSN75174 QUADRUPLE DIFFERENTIAL LINE DRIVER
SN Meets or Exceeds the Requirements of ANSI Standards EIA/TIA--B and RS-8 and ITU Recommendation V.. Designed for Multipoint Transmission on Long Bus Lines in Noisy Environments -State s Common-Mode Voltage
More informationAM26LS31 QUADRUPLE DIFFERENTIAL LINE DRIVER
AM6LS SLLSG JANUARY 979 REVISED FEBRUARY Meets or Exceeds the Requirements of ANSI TIA/EIA--B and ITU Recommendation V. Operates From a Single -V Supply TTL Compatible Complementary Outputs High Output
More informationDistributed by: www.jameco.com 1-800-81-4242 The content and copyrights of the attached material are the property of its owner. Operating Range 2-V to.-v V CC Latch-Up Performance Exceeds 20 ma Per JESD
More informationEN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at ore.hu.
EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at www.hest ore.hu. Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping
More informationSN75150 DUAL LINE DRIVER
Meets or Exceeds the Requirement of TIA/EIA-232-F and ITU Recommendation V.28 Withstands Sustained Output Short Circuit to Any Low-Impedance Voltage Between 25 V and 25 V 2-µs Maximum Transition Time Through
More informationSN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SN54LS373, SN54LS374, SN54S373, SN54S374, Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving s Full Parallel Access for Loading Buffered Control s Clock-Enable Has
More informationSN54LS245, SN74LS245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
3-State s Drive Bus Lines Directly PNP s Reduce dc Loading on Bus Lines Hysteresis at Bus s Improves Noise Margins Typical Propagation Delay Times Port to Port, 8 ns TYPE IOL (SINK CURRENT) IOH (SOURCE
More informationSN74ALVCH BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 200 Per MIL-STD-883, Method 3015; Exceeds 20 Using Machine Model (C =
More informationSN54ALS299, SN74ALS299 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS
Multiplexed I/O Ports Provide Improved Bit Deity Four Modes of Operation: old (Store) Shift Right Shift eft oad Data Operate With Outputs Enabled or at igh Impedance -State Outputs Drive Bus ines Directly
More informationSN55115, SN75115 DUAL DIFFERENTIAL RECEIVERS
SN, SN7 Choice of Open-Collector or Active Pullup (Totem-Pole) Outputs Single -V Supply Differential Line Operation Dual-Channel Operation TTL Compatible ± -V Common-Mode Input Voltage Range Optional-Use
More informationSN54LVC14A, SN74LVC14A HEX SCHMITT-TRIGGER INVERTERS
Typical V OLP ( Ground Bounce) 2 V at V CC = 3.3 V, T A = 25 C s Accept Voltages to 5.5 V Latch-Up Performance Exceeds 100 ma Per JESD
More informationSN54AHC123A, SN74AHC123A DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS
EPIC (Enhanced-Performance Implanted CMOS) Process Operating Range 2-V to 5.5-V V CC Schmitt-Trigger Circuitry On A, B, and CLR Inputs for Slow Input Traition Rates Edge Triggered From Active-High or Active-Low
More informationMC3486 QUADRUPLE DIFFERENTIAL LINE RECEIVER WITH 3-STATE OUTPUTS
Meets or Exceeds the Requirements of ANSI Standards EIA/TIA-422-B and EIA/TIA-423-B and ITU Recommendations V.10 and V.11 3-State, TTL-Compatible s Fast Transition Times Operates From Single 5-V Supply
More informationSN54AHCT174, SN74AHCT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR
Inputs Are TTL-Voltage Compatible Contain Six Flip-Flops With Single-Rail s Applicatio Include: Buffer/Storage Registers Shift Registers Pattern Generators Latch-Up Performance Exceeds 250 ma Per JESD
More informationSN5404, SN54LS04, SN54S04, SN7404, SN74LS04, SN74S04 HEX INVERTERS
Dependable Texas Instruments Quality and Reliability description These devices contain six independent inverters. SN5404, SN54LS04, SN54S04, SN5404... J PACKAGE SN54LS04, SN54S04... J OR W PACKAGE SN7404...
More informationSN74FB2033A 8-BIT TTL/BTL REGISTERED TRANSCEIVER
Compatible With IEEE Std 1194.1-1991 (TL) TTL A Port, ackplane Traceiver Logic (TL) Port Open-Collector -Port Outputs Sink 100 ma IAS V CC Pin Minimizes Signal Distortion During Live Iertion or Withdrawal
More informationCDC391 1-LINE TO 6-LINE CLOCK DRIVER WITH SELECTABLE POLARITY AND 3-STATE OUTPUTS
WITH SELECTBLE POLRITY ND -STTE OUTPUTS SCS4 DECEMBER 99 REVISED NOVEMBER 99 Low Skew for Clock-Distribution and Clock-Generation pplicatio TTL-Compatible Inputs and s Distributes One Clock Input to Six
More informationSN75150 DUAL LINE DRIVER
Meets or Exceeds the Requirement of ANSI EIA/TIA-232-E and ITU Recommendation V.28 Withstands Sustained Output Short Circuit to Any Low-Impedance Voltage Between 25 V and 25 V 2-µs Max Transition Time
More informationSN74AHC1G04 SINGLE INVERTER GATE
Operating Range 2-V to 5.5-V V CC Latch-Up Performance Exceeds 250 m Per JESD 17 description The SN74HC1G04 contai one inverter gate. The device performs the Boolean function =. DBV OR DCK PCKGES (TOP
More informationSN75374 QUADRUPLE MOSFET DRIVER
SLRS28 SEPTEMBER 1988 Quadruple Circuits Capable of Driving High-Capacitance Loads at High Speeds Output Supply Voltage Range From 5 V to 24 V Low Standby Power Dissipation V CC3 Supply Maximizes Output
More informationSN54ALS32, SN54AS32, SN74ALS32, SN74AS32 QUADRUPLE 2-INPUT POSITIVE-OR GATES
SN54ALS32, SN54AS32, SN74ALS32, SN74AS32 QUADRUPLE 2-INPUT POSITIVE-OR GATES SDAS113B APRIL 1982 REVISED DECEMBER 1994 Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers
More informationdescription 1G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND V CC 2G/2G 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 1Y1 2A4 1Y2 2A3 1Y3 1A2 2Y3 1A3 2Y2 1A4 2A2 2G/2G 2Y1
SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244 3-State s Drive Bus Lines or Buffer Memory Address Registers PNP s Reduce DC Loading Hysteresis at s Improves Noise Margins description These
More informationSN54AHCT273, SN74AHCT273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR
Inputs Are TTL-Voltage ompatible EPI (Enhanced-Performance Implanted MOS) Process ontain Eight Flip-Flops With Single-ail s Direct lear Input Individual Data Input to Each Flip-Flop Applicatio Include:
More informationSN75C1406 TRIPLE LOW-POWER DRIVERS/RECEIVERS
Meet or Exceed the Requirements of TIA/EIA-232-F and ITU Recommendation V.28 Very Low Power Consumption... 5 mw Typ Wide Driver Supply Voltage Range... ±4.5 V to ±15 V Driver Output Slew Rate Limited to
More informationSN54221, SN54LS221, SN74221, SN74LS221 DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS
Dual Versions of Highly Stable SN542 and SN742 One Shots SN5422 and SN7422 Demonstrate Electrical and Switching Characteristics That Are Virtually Identical to the SN542 and SN742 One Shots Pinout Is Identical
More informationORDERING INFORMATION PACKAGE
Member of Texas Instruments Widebus Family Latch-Up Performance Exceeds 250 ma Per JESD 17 ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) Bus Hold on Data
More informationORDERING INFORMATION PACKAGE SOT (SC-70) DCK
Operating Range of 2 V to 5.5 V Max t pd of 10 at 5 V Low Power Coumption, 10-µ Max I CC ±8-m Drive at 5 V Latch-Up Performance Exceeds 250 m Per JESD 17 description/ordering information DBV OR DCK PCKGE
More informationSN74ALVCHR BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process UBT (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in
More informationSN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS
Single Down/Up Count-Control Line Look-Ahead Circuitry Enhances Speed of Cascaded Counters Fully Synchronous in Count Modes Asynchronously Presettable With Load Control Package Options Include Plastic
More informationORDERING INFORMATION PACKAGE
Member of Texas Instruments Widebus Family State-of-the-Art Advanced Low-Voltage BiCMOS (ALB) Technology Design for.-v Operation Schottky Diodes on All s to Eliminate Overshoot and Undershoot Industry
More informationSN54AHC573, SN74AHC573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
Operating Range 2-V to 5.5-V V CC 3-State s Directly Drive Bus Lines Latch-Up Performance Exceeds 250 ma Per JESD 17 description The AHC573 devices are octal traparent D-type latches designed for 2-V to
More informationDistributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. Operating Range 2-V to 5.5-V V CC 3-State s Drive Bus Lines Directly Latch-Up
More informationSN54ALS05A, SN74ALS05A HEX INVERTERS WITH OPEN-COLLECTOR OUTPUTS
SN54ALS05A, SN74ALS05A HEX INVERTERS WITH OPEN-COLLECTOR OUTPUTS SDAS190A APRIL 1982 REVISED DECEMBER 1994 Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard
More informationSN65176B, SN75176B DIFFERENTIAL BUS TRANSCEIVERS
SN676B, SN776B Bidirectional Transceivers Meet or Exceed the Requirements of ANSI Standards TIA/EIA--B and TIA/EIA-8-A and ITU Recommendations V. and X.7 Designed for Multipoint Transmission on Long Bus
More informationMAX232, MAX232I DUAL EIA-232 DRIVER/RECEIVER
Operates With Single -V Power Supply LinBiCMOS Process Technology Two Drivers and Two Receivers ± 0-V Input Levels Low Supply Current...8 ma Typical Meets or Exceeds TIA/EIA-22-F and ITU Recommendation
More informationSN75C185 LOW-POWER MULTIPLE DRIVERS AND RECEIVERS
Meets or Exceeds the Requirements of ANSI EIA/TIA-232-E and ITU Recommendation V.28 Single Chip With Easy Interface Between UART and Serial Port Connector Less Than 9-mW Power Consumption Wide Driver Supply
More informationMC1489, MC1489A, SN55189, SN55189A, SN75189, SN75189A QUADRUPLE LINE RECEIVERS
MC89, MC89A, SN89, SN89A, SN789, SN789A SLLS9B SEPTEMPER 97 REVISED MAY 99 Input Resistance... kω to 7 kω Input Signal Range...± V Operate From Single -V Supply Built-In Input Hysteresis (Double Thresholds)
More informationSN75C185 LOW-POWER MULTIPLE DRIVERS AND RECEIVERS
Meets or Exceeds the Requirements of TIA/EIA-232-F and ITU Recommendation V.28 Single Chip With Easy Interface Between UART and Serial-Port Connector Less Than 9-mW Power Consumption Wide Driver Supply
More informationSN75C1406 TRIPLE LOW-POWER DRIVERS/RECEIVERS
Meet or Exceed the Requirements of ANSI EIA/TIA-232-E and ITU Recommendation V.28 Very Low Power Consumption 5 mw Typ Wide Driver Supply Voltage Range ±4.5 V to ±15 V Driver Output Slew Rate Limited to
More informationCD74HCT4514, CD74HCT LINE TO 16-LINE DECODERS/DEMULTIPLEXERS WITH INPUT LATCHES
4.5-V to 5.5-V V CC Operation Fanout (Over Temperature Range) Standard s... 0 LSTTL Loads Bus-Driver s... 5 LSTTL Loads Wide Operating Temperature Range of 55 C to 25 C Balanced Propagation Delays and
More informationPCA8550 NONVOLATILE 5-BIT REGISTER WITH I 2 C INTERFACE
EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Useful for Jumperless Configuration of PC Motherboard Inputs Accept Voltages to 5.5 V Signals are 2.5-V Outputs Signal is a 3.3-V Output Minimum
More informationCDC LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS442B FEBRUARY 1994 REVISED NOVEMBER 1995
Low Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation pplications Operates at 3.3-V LVTTL-Compatible Inputs and s Supports Mixed-Mode Signal Operation (-V Input and Voltages With 3.3-V )
More informationSN5414, SN54LS14, SN7414, SN74LS14 HEX SCHMITT-TRIGGER INVERTERS
Operation From Very Slow Edges Improved Line-Receiving Characteristics High Noise Immunity SN5414, SN54LS14, SN5414, SN54LS14...J OR W PACKAGE SN7414... D, N, OR NS PACKAGE SN74LS14... D, DB, OR N PACKAGE
More informationORDERING INFORMATION PACKAGE
Member of Texas Instruments Widebus Family Latch-Up Performance Exceeds 250 ma Per JESD 17 description This 16-bit (dual-octal) noninverting bus transceiver contains two separate supply rails; B port has
More informationSN54LS06, SN74LS06, SN74LS16 HEX INVERTER BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays s Fully Compatible With Most TTL Circuits
More informationSN54LS07, SN74LS07, SN74LS17 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays description These hex buffers/drivers feature
More informationTL5632C 8-BIT 3-CHANNEL HIGH-SPEED DIGITAL-TO-ANALOG CONVERTER
8-Bit Resolution Linearity... ±1/2 LSB Maximum Differential Nonlinearity...±1/2 LSB Maximum Conversion Rate...60 MHz Min Nominal Output Signal Operating Range V CC to V CC 1 V TTL Digital Input Voltage
More informationThese devices contain four independent 2-input NAND gates. The devices perform the Boolean function Y = A B or Y = A + B in positive logic.
Package Optio Include Plastic Small-Outline (D, NS, PS), Shrink Small-Outline (D), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) DIPs SN00...J PCKGE
More information