These devices contain four independent 2-input NAND gates. The devices perform the Boolean function Y = A B or Y = A + B in positive logic.

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1 Package Optio Include Plastic Small-Outline (D, NS, PS), Shrink Small-Outline (D), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) DIPs SN00...J PCKGE SNLS00, SNS00...J OR W PCKGE SN00, SNS00... D, N, OR NS PCKGE SNLS00... D, D, N, OR NS PCKGE lso vailable as Dual 2-Input Positive-NND Gate in Small-Outline (PS) Package SNLS00, SNS00...PS PCKGE SN00...W PCKGE SNLS00, SNS00... FK PCKGE description/ordering information 2 No internal connection These devices contain four independent 2-input NND gates. The devices perform the oolean function = or = + in positive logic. Please be aware that an important notice concerning availability, standard warranty, and use in critical applicatio of Texas Itruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 200, Texas Itruments Incorporated POST OFFICE OX 0 DLLS, TEXS 2

2 description/ordering information (continued) T ORDERING INFORMTION PCKGE ORDERLE PRT NUMER SN00N TOP-SIDE MRKING SN00N PDIP N SNLS00N SNLS00N SNS00N SNS00N SN00D Tape and reel SN00DR 00 SNLS00D SOIC D Tape and reel SNLS00DR LS00 0 C to 0 C SNS00D Tape and reel SNS00DR S00 C to 2 C SN00NSR SN00 SOP NS Tape and reel SNLS00NSR LS00 SOP PS Tape and reel SNS00NSR SNLS00PSR SNS00PSR S00 LS00 S00 SSOP D Tape and reel SNLS00DR LS00 SNJ00J SNJ00J CDIP J SNJLS00J SNJLS00J SNJS00J SNJ00W SNJS00J SNJ00W CFP W SNJLS00W SNJLS00W LCCC FK SNJS00W SNJLS00FK SNJS00FK SNJS00W SNJLS00FK SNJS00FK Package drawings, standard packing quantities, thermal data, symbolization, and PC design guidelines are available at FUTION TLE (each gate) INPUTS OUTPUT H H L L X H X L H logic diagram, each gate (positive logic) 2 POST OFFICE OX 0 DLLS, TEXS 2

3 schematic 00 kω. kω 0 Ω kω LS00 S00 20 kω kω 20 Ω 2. kω 900 Ω 0 Ω 2 kω kω. kω 00 Ω 20 Ω. kω kω Resistor values shown are nominal. POST OFFICE OX 0 DLLS, TEXS 2

4 absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage, (see Note ) V Input voltage: 00, S V LS V Package thermal impedance, θ J (see Note 2): D package C/W D package C/W N package C/W NS package C/W PS package C/W Storage temperature range, T stg C to 0 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. NOTES:. Voltage values are with respect to network ground terminal. 2. The package termal impedance is calculated in accordance with JESD -. recommended operating conditio (see Note ) SN00 SN00 MIN NOM MX MIN NOM MX Supply voltage....2 V VIH High-level input voltage 2 2 V VIL Low-level input voltage V IOH High-level output current m IOL Low-level output current m T Operating free-air temperature C NOTE : ll unused inputs of the device must be held at or to eure proper device operation. Refer to the TI application report, Implicatio of Slow or Floating CMOS Inputs, literature number SC00. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS SN00 SN00 MIN TP MX MIN TP MX VIK = MIN, II = 2 m.. V VOH = MIN, VIL = 0. V, IOH = 0. m V VOL = MIN, VIH = 2 V, IOL = m V II = MX, VI =. V m IIH = MX, VI = 2. V 0 0 µ IIL = MX, VI = 0. V.. m IOS = MX 20 m ICCH = MX, VI = m ICCL = MX, VI =. V m For conditio shown as MIN or MX, use the appropriate value specified under recommended operating conditio. ll typical values are at = V, T = 2 C. Not more than one output should be shorted at a time. POST OFFICE OX 0 DLLS, TEXS 2

5 switching characteristics, = V, T = 2 C (see Figure ) FROM (INPUT) TO (OUTPUT) TEST CONDITIONS SN00 SN00 MIN TP MX or RL = 00 Ω, CL = pf 22 recommended operating conditio (see Note ) SNLS00 SNLS00 MIN NOM MX MIN NOM MX Supply voltage....2 V VIH High-level input voltage 2 2 V VIL Low-level input voltage V IOH High-level output current m IOL Low-level output current m T Operating free-air temperature C NOTE : ll unused inputs of the device must be held at or to eure proper device operation. Refer to the TI application report, Implicatio of Slow or Floating CMOS Inputs, literature number SC00. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS SNLS00 SNLS00 MIN TP MX MIN TP MX VIK = MIN, II = m.. V VOH = MIN, VIL = MX, IOH = 0. m V VOL = MIN, VIH = 2 V IOL = m IOL = m II = MX, VI = V m IIH = MX, VI = 2.V µ IIL = MX, VI = 0. V m IOS = MX m ICCH = MX, VI = m ICCL = MX, VI =. V m For conditio shown as MIN or MX, use the appropriate value specified under recommended operating conditio. ll typical values are at = V, T = 2 C. Not more than one output should be shorted at a time. switching characteristics, = V, T = 2 C (see Figure ) V FROM (INPUT) TO (OUTPUT) TEST CONDITIONS SNLS00 SNLS00 MIN TP MX or RL = 2 kω, CL = pf 9 0 POST OFFICE OX 0 DLLS, TEXS 2

6 recommended operating conditio (see Note ) SNS00 SNS00 MIN NOM MX MIN NOM MX Supply voltage....2 V VIH High-level input voltage 2 2 V VIL Low-level input voltage V IOH High-level output current m IOL Low-level output current m T Operating free-air temperature C NOTE : ll unused inputs of the device must be held at or to eure proper device operation. Refer to the TI application report, Implicatio of Slow or Floating CMOS Inputs, literature number SC00. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS SNS00 SNS00 MIN TP MX MIN TP MX VIK = MIN, II = m.2.2 V VOH = MIN, VIL = 0. V, IOH = m V VOL = MIN, VIH = 2 V, IOL = 20 m V II = MX, VI =. V m IIH = MX, VI = 2. V 0 0 µ IIL = MX, VI = 0.V 2 2 m IOS = MX m ICCH = MX, VI = 0 0 m ICCL = MX, VI =. V m For conditio shown as MIN or MX, use the appropriate value specified under recommended operating conditio. ll typical values are at = V, T = 2 C. Not more than one output should be shorted at a time. switching characteristics, = V, T = 2 C (see Figure ) FROM (INPUT) TO (OUTPUT) TEST CONDITIONS SNS00 SNS00 MIN TP MX or RL = 20 Ω, CL = pf. or RL = 20 Ω, CL = 0 pf. POST OFFICE OX 0 DLLS, TEXS 2

7 From Output Under Test Test Point CL (see Note ) RL MESUREMENT INFORMTION SERIES / DEVICES (see Note ) From Output Under Test CL (see Note ) RL Test Point From Output Under Test CL (see Note ) Test Point RL kω S (see Note ) S2 LOD CIRCUIT FOR 2-STTE TOTEM-POLE OUTPUTS LOD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS LOD CIRCUIT FOR -STTE OUTPUTS High-Level Pulse Low-Level Pulse tw PULSE DURTIONS Timing Input Data Input tsu. V th SETUP ND HOLD TIMES V V Input V Output Control (low-level enabling) tpzl tplz V In-Phase Output (see Note D) Out-of-Phase Output (see Note D) PROPGTION DEL TIMES VOH VOL VOH VOL Waveform (see Notes C and D) Waveform 2 (see Notes C and D) tpzh. V. V VOL + 0. V VOL tphz. V VOH VOH 0. V. V ENLE ND DISLE TIMES, -STTE OUTPUTS NOTES:. CL includes probe and jig capacitance.. ll diodes are N0 or equivalent. C. Waveform is for an output with internal conditio such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditio such that the output is high except when disabled by the output control. D. S and S2 are closed for,, tphz, and tplz; S is open and S2 is closed for tpzh; S is closed and S2 is open for tpzl. E. ll input pulses are supplied by generators having the following characteristics: PRR MHz, ZO 0 Ω; tr and tf for Series / devices and tr and tf 2. for Series S/S devices. F. The outputs are measured one at a time with one input traition per measurement. Figure. Load Circuits and Voltage Waveforms POST OFFICE OX 0 DLLS, TEXS 2

SN5404, SN54LS04, SN54S04, SN7404, SN74LS04, SN74S04 HEX INVERTERS

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