SN54GTL16612, SN74GTL BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS

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1 18-IT LTTL-TO-GTL/GTL+ UNIERSL US TRNSCEIERS Members of Texas Itruments Widebus Family UT Traceivers Combine D-Type Latches and D-Type Flip-Flops for Operation in Traparent, Latched, Clocked, or Clock-Enabled Modes OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Tralate etween GTL/GTL+ Signal Levels and LTTL Logic Levels Support Mixed-Mode (3.3 and 5 ) Signal Operation on -Port and Control Inputs Identical to Function I off Supports Partial-Power-Down Mode Operation us Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors on Port Distributed CC and Pi Minimize High-Speed Switching Noise Latch-Up Performance Exceeds 500 m Per JESD 17 description The GTL16612 devices are 18-bit UT traceivers that provide LTTL-to-GTL/GTL+ and GTL/GTL+-to-LTTL signal-level tralation. They combine D-type flip-flops and D-type latches to allow for traparent, latched, clocked, and clock-enabled modes of data trafer identical to the function. The devices provide an interface between cards operating at LTTL logic levels and a backplane operating at GTL/GTL+ signal levels. Higher-speed operation is a direct result of the reduced output swing (<1 ), reduced input threshold levels, and OEC circuitry. SCS480K JUNE 1994 REISED UGUST 2001 SN54GTL WD PCKGE SN74GTL DGG OR DL PCKGE (TOP IEW) OE LE CC (3.3 ) CC (3.3 ) OE LE The user has the flexibility of using these devices at either GTL ( TT = 1.2 and REF = 0.8 ) or the preferred higher noise margin GTL+ ( TT = 1.5 and REF = 1 ) signal levels. GTL+ is the Texas Itruments derivative of the Gunning Traceiver Logic (GTL) JEDEC standard JESD 8-3. The port normally operates at GTL or GTL+ signal levels, while the -port and control inputs are compatible with LTTL logic levels and are 5- tolerant. REF is the reference input voltage for the port. CC (5 ) supplies the internal and GTL circuitry while CC (3.3 ) supplies the LTTL output buffers CE CLK CC (5 ) REF CLK CE Please be aware that an important notice concerning availability, standard warranty, and use in critical applicatio of Texas Itruments semiconductor products and disclaimers thereto appears at the end of this data sheet. OEC, UT, and Widebus are trademarks of Texas Itruments. PRODUCTION DT information is current as of publication date. Products conform to specificatio per the terms of Texas Itruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE OX DLLS, TEXS Copyright 2001, Texas Itruments Incorporated On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. 1

2 18-IT LTTL-TO-GTL/GTL+ UNIERSL US TRNSCEIERS SCS480K JUNE 1994 REISED UGUST 2001 description (continued) Data flow in each direction is controlled by output-enable (OE and OE), latch-enable(le and LE), and clock (CLK and CLK) inputs. The clock can be controlled by the clock-enable (CE and CE) inputs. For -to- data flow, the devices operate in the traparent mode when LE is high. When LE is low, the data is latched if CE is low and CLK is held at a high or low logic level. If LE is low, the data is stored in the latch/flip-flop on the low-to-high traition of CLK if CE also is low. When OE is low, the outputs are active. When OE is high, the outputs are in the high-impedance state. Data flow for to is similar to that for to, but uses OE, LE, CLK, and CE. These devices are fully specified for partial-power-down applicatio using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ctive bus-hold circuitry holds unused or undriven LTTL inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. T 40 C to 85 C SSOP DL ORDERING INFORMTION PCKGE Tube Tape and reel ORDERLE PRT NUMER SN74GTL16612DL SN74GTL16612DLR TOP-SIDE MRKING GTL16612 TSSOP DGG Tape and reel SN74GTL16612DGGR GTL C to 125 C CFP WD Tube SNJ54GTL16612WD SNJ54GTL16612WD Package drawings, standard packing quantities, thermal data, symbolization, and PC design guidelines are available at FUNCTION TLE INPUTS OUTPUT MODE CE OE LE CLK X H X X X Z Isolation L L L H X 0 L L L L X 0 Latched storage of data X L H X L L X L H X H H L L L L L L L L H H Traparent Clocked storage of data H L L X X 0 Clock inhibit -to- data flow is shown. -to- data flow is similar but uses OE, LE, CLK, and CE. level before the indicated steady-state input conditio were established, provided that CLK was high before LE went low level before the indicated steady-state input conditio were established 2 POST OFFICE OX DLLS, TEXS 75265

3 18-IT LTTL-TO-GTL/GTL+ UNIERSL US TRNSCEIERS SCS480K JUNE 1994 REISED UGUST 2001 logic diagram (positive logic) 35 OE 1 CE 56 CLK 55 LE 2 LE 28 CLK 30 CE 29 OE CE 1D C1 CLK CE 1D C1 CLK 54 1 To 17 Other Channels POST OFFICE OX DLLS, TEXS

4 18-IT LTTL-TO-GTL/GTL+ UNIERSL US TRNSCEIERS SCS480K JUNE 1994 REISED UGUST 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, CC : to to 7 Input voltage range, I (see Note 1): -port and control inputs to 7 port and REF to 4.6 oltage range applied to any output in the high or power-off state, O (see Note 1): port to 7 port to 4.6 Current into any output in the low state, I O : port m port m Current into any -port output in the high state, I O (see Note 2) m Continuous current through each CC or ±100 m Input clamp current, I IK ( I < 0) m clamp current, I OK ( O < 0) m Package thermal impedance, θ J (see Note 3): DGG package C/W DL package C/W Storage temperature range, T stg C to 150 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and O > CC. 3. The package thermal impedance is calculated in accordance with JESD recommended operating conditio (see Notes 4 through 7) SN54GTL16612 SN74GTL16612 MIN NOM MX MIN NOM MX CC Supply voltage TT Termination GTL voltage GTL Reference voltage GTL GTL I Input voltage port TT TT Except port IH High-level port +50 m +50 m input voltage Except port 2 2 Low-level port 50 m 50 m IL input voltage Except port IIK Input clamp current m IOH High-level output current port m Low-level port IOL output current port T Operating free-air temperature C NOTES: 4. ll unused inputs of the device must be held at CC or to eure proper device operation. Refer to the TI application report, Implicatio of Slow or Floating CMOS Inputs, literature number SC Normal connection sequence is first, CC = 5 second, and CC = 3.3, I/O, control inputs, TT and (any order) last. 6. TT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded. 7. can be adjusted to optimize noise margi, but normally is two-thirds TT. m 4 POST OFFICE OX DLLS, TEXS 75265

5 18-IT LTTL-TO-GTL/GTL+ UNIERSL US TRNSCEIERS SCS480K JUNE 1994 REISED UGUST 2001 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PRMETER IK OH port OL III CC (3.3 ) = 3.15, CC (5 ) = 4.75 TEST CONDITIONS CC (3.3 )= 3.15 to 3.45, CC (5 ) = 4.75 to 5.25 SN54GTL16612 SN74GTL16612 MIN TYP MX MIN TYP MX II = 18 m IOH = 100 µ CC (3.3 ) 0.2 CC (3.3 ) 0.2 CC (3.3 ) = 3.15, IOH = 8 m CC (5 ) = 4.75 IOH = 32 m 2 2 IOL = 100 µ CC (3.3 ) = 3.15, IOL = 16 m port CC (5 ) = 4.75 IOL = 32 m IOL = 64 m port CC (3.3 ) = 3.15, CC (5 ) = 4.75, IOL = 40 m Control inputs port CC (3.3 ) = 0 or 3.45, CC (5 ) = 0 or 5.25 CC (33) (3.3 = , CC (5 ) = 5.25 I = I = I = CC (3.3 ) 1 1 µ I = CC (3.3 ) = 3.45, I = CC (3.3 ) 5 5 port CC (5 ) = 5.25 I = Ioff CC = 0, I or O = 0 to µ (33) 315 II(hold) port CC (3.3 = 3.15, ( CC (5 ) = 4.75 IOZH IOZL ICC or (3.33 ) port I = I = µ I = 0 to CC (3.3 ) ±500 ±500 port CC (3.3 ) = 3.45, CC (5 ) = 5.25, O = port CC (3.3 ) = 3.45, CC (5 ) = 5.25, O = port CC (3.3 ) = 3.45, CC (5 ) = 5.25, O = port CC (3.3 ) = 3.45, CC (5 ) = 5.25, O = s high 1 1 CC (3.3 ) = 3.45, CC (5 ) = 5.25, IO = 0, s low 5 5 m I = CC (3.3 ) or s disabled 1 1 µ µ ICC or (5 ) port s high CC (3.3 ) = 3.45, CC (5 ) = 5.25, IO = 0, s low m I = CC (3.3 ) or s disabled ICC CC (3.3 ) = 3.45, CC (5 ) = 5.25, -port or control inputs at CC (3.3 ) or, One input at 2.7 Ci Cio Control inputs port port 1 1 m I = 3.15 or pf O =315or ll typical values are at CC (3.3 ) = 3.3, CC (5 ) = 5, T = 25 C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. This is the increase in supply current for each input that is at the specified TTL voltage level rather than CC or. pf POST OFFICE OX DLLS, TEXS

6 18-IT LTTL-TO-GTL/GTL+ UNIERSL US TRNSCEIERS SCS480K JUNE 1994 REISED UGUST 2001 timing requirements over recommended ranges of supply voltage and operating free-air temperature, TT = 1.2 and REF = 0.8 for GTL (unless otherwise noted) (see Figure 1) SN54GTL16612 SN74GTL16612 MIN MX MIN MX fclock Clock frequency MHz tw tsu th Pulse duration Setup time Hold time LE or LE high CLK or CLK high or low before CLK before CLK before LE before LE 1 1 CE before CLK CE before CLK after CLK after CLK after LE after LE CE after CLK CE after CLK switching characteristics over recommended ranges of supply voltage and operating free-air temperature, TT = 1.2 and REF = 0.8 for GTL (see Figure 1) PRMETER FROM TO SN54GTL16612 SN74GTL16612 (INPUT) (OUTPUT) MIN TYP MX MIN TYP MX fmax MHz LE CLK ten OE tdis tr Traition time, outputs (0.5 to 1 ) tf Traition time, outputs (1 to 0.5 ) LE CLK ten OE tdis ll typical values are at CC (3.3 ) = 3.3, CC (5 ) = 5, T = 25 C POST OFFICE OX DLLS, TEXS 75265

7 18-IT LTTL-TO-GTL/GTL+ UNIERSL US TRNSCEIERS SCS480K JUNE 1994 REISED UGUST 2001 timing requirements over recommended ranges of supply voltage and operating free-air temperature, TT = 1.5 and REF = 1 for GTL+ (unless otherwise noted) (see Figure 1) SN54GTL16612 SN74GTL16612 MIN MX MIN MX fclock Clock frequency MHz tw tsu th Pulse duration Setup time Hold time LE or LE high CLK or CLK high or low before CLK before CLK before LE before LE CE before CLK CE before CLK after CLK after CLK after LE after LE CE after CLK CE after CLK switching characteristics over recommended ranges of supply voltage and operating free-air temperature, TT = 1.5 and REF = 1 for GTL+ (see Figure 1) PRMETER FROM TO SN54GTL16612 SN74GTL16612 (INPUT) (OUTPUT) MIN TYP MX MIN TYP MX fmax MHz LE CLK OE tr Traition time, outputs (0.5 to 1 ) tf Traition time, outputs (1 to 0.5 ) LE CLK ten OE tdis ll typical values are at CC (3.3 ) = 3.3, CC (5 ) = 5, T = 25 C POST OFFICE OX DLLS, TEXS

8 18-IT LTTL-TO-GTL/GTL+ UNIERSL US TRNSCEIERS SCS480K JUNE 1994 REISED UGUST 2001 PRMETER MESUREMENT INFORMTION TT = 1.2, REF = 0.8 FOR GTL ND TT = 1.5, REF = 1 FOR GTL+ From Under Test CL = 50 pf (see Note ) 500 Ω 500 Ω S1 6 Open TEST / tplz/tpzl tphz/tpzh S1 Open 6 25 Ω From Under Test CL = 30 pf (see Note ) TT Test Point LOD CIRCUIT FOR OUTPUTS LOD CIRCUIT FOR OUTPUTS Input Input (see Note ) M tw M OLTGE WEFORMS PULSE DURTION (M = 1.5 for port and for port) Timing Input Data Input Port Data Input Port tsu th OLTGE WEFORMS SETUP ND HOLD TIMES TT 0 Input (see Note ) OLTGE WEFORMS PROPGTION DELY TIMES ( port to port) TT OL TT 0 Control (see Note ) Waveform 1 S1 at 6 (see Note C) tpzl tplz OL OL OLTGE WEFORMS PROPGTION DELY TIMES ( port to port) OH OL Waveform 2 S1 at (see Note C) tpzh 1.5 OLTGE WEFORMS ENLE ND DISLE TIMES ( port) tphz OH OH ll control inputs are TTL levels. NOTES:. CL includes probe and jig capacitance.. ll input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 Ω, tr 2.5, tf 2.5. C. Waveform 1 is for an output with internal conditio such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditio such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one traition per measurement. Figure 1. Load Circuits and oltage Waveform 8 POST OFFICE OX DLLS, TEXS 75265

9 IMPORTNT NOTICE Texas Itruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. ll products are sold subject to the terms and conditio of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its products to the specificatio applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are respoible for their applicatio using TI components. In order to minimize risks associated with the customer s applicatio, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applicatio assistance or customer product design. TI does not warrant or represent that any licee, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such products or services might be or are used. TI s publication of information regarding any third party s products or services does not cotitute TI s approval, licee, warranty or endorsement thereof. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditio, limitatio and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated TI product or service, is an unfair and deceptive business practice, and TI is not respoible nor liable for any such use. Resale of TI s products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service, is an unfair and deceptive business practice, and TI is not respoible nor liable for any such use. lso see: Standard Terms and Conditio of Sale for Semiconductor Products. Mailing ddress: Texas Itruments Post Office ox Dallas, Texas Copyright 2001, Texas Itruments Incorporated

SN74AHC1G04 SINGLE INVERTER GATE

SN74AHC1G04 SINGLE INVERTER GATE Operating Range 2-V to 5.5-V V CC Latch-Up Performance Exceeds 250 m Per JESD 17 description The SN74HC1G04 contai one inverter gate. The device performs the Boolean function =. DBV OR DCK PCKGES (TOP