CD54AC74, CD74AC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

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1 A Types Feature.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Speed of Bipolar F, AS, and S, With Significantly Reduced Power oumption Balanced Propagation Delays ±24-mA Output Drive urrent Fanout to 5 F Devices SR-Latchup-Resistant MOS Process and ircuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 305 D54A74, D74A74 WITH LEAR AND PRESET SHS23D SEPTEMBER 998 REVISED DEEMBER 2002 D54A74...F PAKAGE D74A74...E OR M PAKAGE (TOP VIEW) LR D LK PRE Q Q GND V 2LR 2D 2LK 2PRE 2Q 2Q description/ordering information The A74 dual positive-edge-triggered devices are D-type flip-flops. A low level at the preset (PRE) or clear (LR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and LR are inactive (high), data at the data (D) input meeting the setup time requirements is traferred to the outputs on the positive-going edge of the clock pulse. lock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. TA ORDERING INFORMATION PAKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP E Tube D74A74E D74A74E Tube D74A74M 55 to25 SOI M A74M Tape and reel D74A74M96 DIP F Tube D54A74F3A D54A74F3A Package drawings, standard packing quantities, thermal data, symbolization, and PB design guidelines are available at FUNTION TABLE (each flip-flop) INPUTS OUTPUTS PRE LR LK D Q Q L H X X H L H L X X L H L L X X H H H H H H L H H L L H H H L X Q0 Q0 This configuration is notable; that is, it does not persist when PRE or LR retur to its inactive (high) level. Please be aware that an important notice concerning availability, standard warranty, and use in critical applicatio of Texas Itruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUTION DATA information is current as of publication date. Products conform to specificatio per the terms of Texas Itruments standard warranty. Production processing does not necessarily include testing of all parameters. opyright 2002, Texas Itruments Incorporated On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFIE BOX DALLAS, TEXAS 75265

2 D54A74, D74A74 WITH LEAR AND PRESET SHS23D SEPTEMBER 998 REVISED DEEMBER 2002 logic diagram, each flip-flop (positive logic) PRE LK TG Q D TG TG TG Q LR absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V V to 6 V Input clamp current, I IK (V I < 0 or V I > V ) (see Note ) ±20 ma Output clamp current, I OK (V O < 0 or V O > V ) (see Note ) ±50 ma ontinuous output current, I O (V O = 0 to V ) ±50 ma ontinuous current through V or GND ±00 ma Package thermal impedance, θ JA (see Note 2): E package /W M package /W Storage temperature range, T stg to 50 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. NOTES:. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD POST OFFIE BOX DALLAS, TEXAS 75265

3 recommended operating conditio (see Note 3) D54A74, D74A74 WITH LEAR AND PRESET SHS23D SEPTEMBER 998 REVISED DEEMBER 2002 TA = to to 85 UNIT MIN MAX V Supply voltage V V =.5 V VIH High-level input voltage V = 3 V V V = 5.5 V V =.5 V VIL Low-level input voltage V = 3 V V V = 5.5 V VI Input voltage V VO Output voltage V IOH High-level output current V = 4.5 V to 5.5 V ma IOL Low-level output current V = 4.5 V to 5.5 V ma t/ v NOTE 3: Input traition rise or fall rate V =.5 V to 3 V V = 3.6 V to 5.5 V All unused inputs of the device must be held at V or GND to eure proper device operation. Refer to the TI application report, Implicatio of Slow or Floating MOS Inputs, literature number SBA004. /V electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST ONDITIONS V TA = to to 85 UNIT MIN MAX.5 V IOH = 50 µa 3 V V VOH VI = VIH or VIL IOH = 4 ma 3 V V IOH = 24 ma 4.5 V IOH = 50 ma 5.5 V 3.85 IOH = 75 ma 5.5 V V IOL = 50 µa 3 V V VOL VI = VIH or VIL IOL = 2 ma 3 V V IOL = 24 ma 4.5 V IOL = 50 ma 5.5 V.65 IOL = 75 ma 5.5 V.65 II VI = V or GND 5.5 V ±0. ± ± µa I VI = V or GND, IO = V µa i pf Test one output at a time, not exceeding -second duration. Measurement is made by forcing indicated current and measuring voltage to minimize power dissipation. Test verifies a minimum 50-Ω tramission-line drive capability at 85 and 75-Ω tramission-line drive capability at 25. POST OFFIE BOX DALLAS, TEXAS

4 D54A74, D74A74 WITH LEAR AND PRESET SHS23D SEPTEMBER 998 REVISED DEEMBER 2002 timing requirements over recommended operating free-air temperature range, V =.5 V (unless otherwise noted) 55 to to 85 UNIT fclock lock frequency 9 0 MHz tw Pulse duration PRE or LR low LK tsu Setup time Data PRE or LR inactive th Hold time Data after LK 0 0 trec Recovery time, before LK LR or PRE timing requirements over recommended operating free-air temperature range, V = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure ) 55 to to 85 UNIT fclock lock frequency MHz tw Pulse duration PRE or LR low LK tsu Setup time Data PRE or LR inactive th Hold time Data after LK 0 0 trec Recovery time, before LK LR or PRE timing requirements over recommended operating free-air temperature range, V = 5 V ± 0.5 V (unless otherwise noted) (see Figure ) 55 to to 85 UNIT fclock lock frequency 0 25 MHz tw Pulse duration PRE or LR low LK tsu Setup time Data PRE or LR inactive th Hold time Data after LK 0 0 trec Recovery time, before LK LR or PRE POST OFFIE BOX DALLAS, TEXAS 75265

5 D54A74, D74A74 WITH LEAR AND PRESET SHS23D SEPTEMBER 998 REVISED DEEMBER 2002 switching characteristics over recommended operating free-air temperature range, V =.5 V, L = 50 pf (unless otherwise noted) (see Figure ) PARAMETER FROM (INPUT) TO (OUTPUT) 55 to to 85 UNIT fmax 9 0 MHz LK Q or Q PRE or LR QorQ Q switching characteristics over recommended operating free-air temperature range, V = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure ) PARAMETER FROM (INPUT) TO (OUTPUT) 55 to to 85 UNIT fmax MHz LK Q or Q PRE or LR QorQ Q switching characteristics over recommended operating free-air temperature range, V = 5 V ± 0.5 V (unless otherwise noted) (see Figure ) PARAMETER FROM (INPUT) TO (OUTPUT) 55 to to 85 UNIT fmax 0 25 MHz LK Q or Q PRE or LR QorQ Q operating characteristics, T A = 25 PARAMETER TYP UNIT pd Power dissipation capacitance 55 pf POST OFFIE BOX DALLAS, TEXAS

6 D54A74, D74A74 WITH LEAR AND PRESET SHS23D SEPTEMBER 998 REVISED DEEMBER 2002 PARAMETER MEASUREMENT INFORMATION From Output Under Test L = 50 pf (see Note A) R = 500 Ω R2 = 500 Ω S 2 V GND Open TEST / tplz/tpzl tphz/tpzh S Open 2 V GND When V =.5 V, R = R2 = kω LOAD IRUIT Input 50% V tw VOLTAGE WAVEFORMS PULSE DURATION V 50% V LR Input LK 50% V trec 50% V V V Reference Input Data Input 50% 0% 50% V tsu th 90% 90% tr V V 50% V 0% tf VOLTAGE WAVEFORMS REOVERY TIME VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES Input In-Phase Output Out-of-Phase Output 50% V 50% 0% 90% 90% 90% VOH 50% V 0% VOL tf VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES tr 50% V 50% V 50% 0% 0% tf V 90% VOH VOL tr Output ontrol Output Waveform S at 2 V (see Note B) Output Waveform 2 S at GND (see Note B) tpzl tpzh 50% V 50% V tplz 50% V 20% V VOL 50% V VOLTAGE WAVEFORMS OUTPUT ENABLE AND DISABLE TIMES tphz V V VOH 80% V NOTES: A. L includes probe and test-fixture capacitance. B. Waveform is for an output with internal conditio such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditio such that the output is high except when disabled by the output control.. All input pulses are supplied by generators having the following characteristics: PRR MHz, ZO = 50 Ω, tr = 3, tf = 3. Phase relatiohips between waveforms are arbitrary. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input traition per measurement. F. and are the same as tpd. G. tpzl and tpzh are the same as ten. H. tplz and tphz are the same as tdis. Figure. Load ircuit and Voltage Waveforms 6 POST OFFIE BOX DALLAS, TEXAS 75265

7 MEHANIAL DATA MER002 JANUARY 995 REVISED JUNE 999 J (R-GDIP-T**) 4 LEADS SHOWN ERAMI DUAL-IN-LINE DIM PINS ** B 8 A MAX A MIN 0.30 (7,87) (7,37) 0.30 (7,87) (7,37) 0.30 (7,87) (7,37) B MAX B MIN (9,94) (9,8) (9,94) (9,8) (24,77) (23,62) (,65) (,4) 7 MAX MIN (7,62) (6,22) (7,62) (6,22) (7,62) (6,22) 0.00 (2,54) (,78) (0,5) MIN A (5,08) MAX Seating Plane 0.30 (3,30) MIN (0,58) 0.05 (0,38) (2,54) 0.04 (0,36) (0,20) /E 03/99 NOTES: A. All linear dimeio are in inches (millimeters). B. This drawing is subject to change without notice.. This package is hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 835 GDIP-T4, GDIP-T6, and GDIP-T20 POST OFFIE BOX DALLAS, TEXAS 75265

8 MEHANIAL MPDI002 JANUARY 995 REVISED DEEMBER N (R-PDIP-T**) 6 PINS SHOWN PLASTI DUAL-IN-LINE PAKAGE DIM PINS ** A A MAX (9,69) (9,69) (23,37).060 (26,92) 6 9 A MIN (8,92) (8,92) (2,59) (23,88) (6,60) (6,0) MS-00 VARIATION AA BB A AD (,78) MAX (0,89) MAX (0,5) MIN (8,26) (7,62) (5,08) MAX 0.05 (0,38) Gauge Plane Seating Plane 0.25 (3,8) MIN 0.00 (0,25) NOM 0.02 (0,53) 0.05 (0,38) 0.00 (0,25) 0.00 (2,54) M (0,92) MAX 4/8 PIN ONLY 20 pin vendor option D /E 2/2002 NOTES: A. All linear dimeio are in inches (millimeters). B. This drawing is subject to change without notice.. Falls within JEDE MS-00, except 8 and 20 pin minimum body lrngth (Dim A). D. The 20 pin end lead shoulder width is a vendor option, either half or full width. POST OFFIE BOX DALLAS, TEXAS 75265

9 MEHANIAL DATA MSOI002B JANUARY 995 REVISED SEPTEMBER 200 D (R-PDSO-G**) PLASTI SMALL-OUTLINE PAKAGE 8 PINS SHOWN (,27) (0,5) 0.04 (0,35) 0.00 (0,25) (6,20) (5,80) (0,20) NOM 0.57 (4,00) 0.50 (3,8) Gage Plane 4 A (0,25) (,2) 0.06 (0,40) Seating Plane (,75) MAX 0.00 (0,25) (0,0) (0,0) DIM PINS ** A MAX 0.97 (5,00) (8,75) (0,00) A MIN (4,80) (8,55) (9,80) /E 09/0 NOTES: A. All linear dimeio are in inches (millimeters). B. This drawing is subject to change without notice.. Body dimeio do not include mold flash or protrusion, not to exceed (0,5). D. Falls within JEDE MS-02 POST OFFIE BOX DALLAS, TEXAS 75265

10 IMPORTANT NOTIE Texas Itruments Incorporated and its subsidiaries (TI) reserve the right to make correctio, modificatio, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. ustomers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditio of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specificatio applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applicatio assistance or customer product design. ustomers are respoible for their products and applicatio using TI components. To minimize the risks associated with customer products and applicatio, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any licee, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third party products or services does not cotitute a licee from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a licee from a third party under the patents or other intellectual property of the third party, or a licee from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditio, limitatio, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not respoible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not respoible or liable for any such statements. Mailing Address: Texas Itruments Post Office Box Dallas, Texas opyright 2002, Texas Itruments Incorporated

CD54AC74, CD74AC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

CD54AC74, CD74AC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET A Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Speed of Bipolar F, AS, and S, With Significantly Reduced Power oumption Balanced Propagation Delays ±24-mA Output