SN54HC74, SN74HC74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
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1 Wide Operating Voltage Range of 2 V to 6 V Outputs an Drive Up To 0 LSTTL Loads Low Power onsumption, 40-µA Max I Typical t pd = 5 ns ±4-mA Output Drive at 5 V Low Input urrent of µa Max description/ordering information The H74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (LR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and LR are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (LK) pulse. lock triggering occurs at a voltage level and is not directly related to the rise time of LK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. SN54H74, SN74H74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH LEAR AND PRESET SLS094D DEEMBER 92 REVISED JULY 2003 SN54H74...J OR W PAKAGE SN74H74... D, DB, N, NS, OR PW PAKAGE (TOP VIEW) LK N PRE N Q LR D LK PRE Q Q GND V 2LR 2D 2LK 2PRE 2Q 2Q SN54H74... FK PAKAGE (TOP VIEW) D LR N V 2LR D N 2LK N 2PRE Q GND N 2Q 2Q TA ORDERING INFORMATION PAKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP N Tube of 25 SN74H74N SN74H74N Tube of 50 SN74H74D SOI D Reel of 2500 SN74H74DR H74 Reel of 250 SN74H74DT 40 to 5 SOP NS Reel of 2000 SN74H74NSR H74 SSOP DB Reel of 2000 SN74H74DBR H74 Tube of 90 SN74H74PW TSSOP PW Reel of 2000 SN74H74PWR H74 Reel of 250 SN74H74PWT N No internal connection DIP J Tube of 25 SNJ54H74J SNJ54H74J 55 to 25 FP W Tube of 50 SNJ54H74W SNJ54H74W L FK Tube of 55 SNJ54H74FK SNJ54H74FK Package drawings, standard packing quantities, thermal data, symbolization, and PB design guidelines are available at Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. opyright 2003, Texas Instruments Incorporated On products compliant to MIL-PRF-3535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFIE BOX DALLAS, TEXAS 75265
2 SN54H74, SN74H74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH LEAR AND PRESET SLS094D DEEMBER 92 REVISED JULY 2003 logic diagram (positive logic) PRE FUNTION TABLE INPUTS OUTPUTS PRE LR LK D Q Q L H X X H L H L X X L H L L X X H H H H H H L H H L L H H H L X Q0 Q0 This configuration is nonstable; that is, it does not persist when PRE or LR returns to its inactive (high) level. LK TG Q D TG TG TG LR Q absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V V to 7 V Input clamp current, I IK (V I < 0 or V I > V ) (see Note ) ±20 ma Output clamp current, I OK (V O < 0 or V O > V ) (see Note ) ±20 ma ontinuous output current, I O (V O = 0 to V ) ±25 ma ontinuous current through V or GND ±50 ma Package thermal impedance, θ JA (see Note 2): D package /W DB package /W N package /W NS package /W PW package /W Storage temperature range, T stg to 50 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD POST OFFIE BOX DALLAS, TEXAS 75265
3 recommended operating conditions (see Note 3) SN54H74, SN74H74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH LEAR AND PRESET SLS094D DEEMBER 92 REVISED JULY 2003 SN54H74 SN74H74 MIN NOM MAX MIN NOM MAX V Supply voltage V V = 2 V.5.5 VIH High-level input voltage V = 4.5 V V V = 6 V V = 2 V VIL Low-level input voltage V = 4.5 V V V = 6 V.. VI Input voltage 0 V 0 V V VO Output voltage 0 V 0 V V V = 2 V t/ v Input transition rise/fall time V = 4.5 V ns V = 6 V TA Operating free-air temperature NOTE 3: All unused inputs of the device must be held at V or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating MOS Inputs, literature number SBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST ONDITIONS V TA = 25 SN54H74 SN74H74 MIN TYP MAX MIN MAX MIN MAX 2 V IOH = 20 µa 4.5 V VOH VI = VIH or VIL 6 V V IOH = 4 ma 4.5 V IOH = 5.2 ma 6 V V IOL = 20 µa 4.5 V VOL VI = VIH or VIL 6 V V IOL = 4 ma 4.5 V IOL = 5.2 ma 6 V II VI = V or 0 6 V ±0. ±00 ±000 ±000 na I VI = V or 0, IO = 0 6 V µa i 2 V to 6 V pf UNIT UNIT POST OFFIE BOX DALLAS, TEXAS
4 SN54H74, SN74H74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH LEAR AND PRESET SLS094D DEEMBER 92 REVISED JULY 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) V TA = 25 SN54H74 SN74H74 MIN MAX MIN MAX MIN MAX 2 V fclock lock frequency 4.5 V MHz tw tsu Pulse duration Setup time before LK 6 V V PRE or LR low 4.5 V V V LK high or low 4.5 V V V Data 4.5 V V V PRE or LR inactive 4.5 V V V th Hold time, data after LK 4.5 V ns 6 V UNIT ns ns switching characteristics over recommended operating free-air temperature range, L = 50 pf (unless otherwise noted) (see Figure ) PARAMETER FROM (INPUT) TO (OUTPUT) V TA = 25 SN54H74 SN74H74 MIN TYP MAX MIN MAX MIN MAX 2 V fmax 4.5 V MHz tpd 6 V V PRE or LR Q or Q 4.5 V V V LK Q or Q 4.5 V V V tt Q or Q 4.5 V ns 6 V UNIT ns operating characteristics, T A = 25 PARAMETER TEST ONDITIONS TYP UNIT pd Power dissipation capacitance per flip-flop No load 35 pf 4 POST OFFIE BOX DALLAS, TEXAS 75265
5 SN54H74, SN74H74 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH LEAR AND PRESET SLS094D DEEMBER 92 REVISED JULY 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test LOAD IRUIT Test Point L = 50 pf (see Note A) High-Level Pulse Low-Level Pulse tw V 0 V V 0 V VOLTAGE WAVEFORMS PULSE DURATIONS Reference Input tsu th V 0 V Input tplh tphl V 0 V Data Input 0% 90% 90% tr V 0% 0 V VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES tf In-Phase Output Out-of-Phase Output 0% tphl 90% 90% 90% tr 0% 0% tf tplh VOH 0% VOL tf VOH 90% VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. L includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.. For clock inputs, fmax is measured when the input duty cycle is. D. The outputs are measured one at a time with one input transition per measurement. E. tplh and tphl are the same as tpd. Figure. Load ircuit and Voltage Waveforms POST OFFIE BOX DALLAS, TEXAS
6
7 MEHANIAL DATA MFP002A JANUARY 995 REVISED FEBRUARY 2002 W (R-GDFP-F4) ERAMI DUAL FLATPAK (,4) (0,66) (6,60) (5,97) Base and Seating Plane 0.00 (2,03) (,4) 0.00 (0,20) (0,0) 0.20 (7,) MAX (0,4) 0.05 (0,3) (,27) (9,9) (,5) (0,3) MIN 4 Places (9,4) (6,35) (9,4) (6,35) / 02/02 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice.. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification only. E. Falls within MIL STD 35 GDFP-F4 and JEDE MO-092AB POST OFFIE BOX DALLAS, TEXAS 75265
8 MEHANIAL DATA ML006B OTOBER 996 FK (S-Q-N**) 2 TERMINAL SHOWN LEADLESS ERAMI HIP ARRIER NO. OF TERMINALS ** MIN A MAX MIN B MAX (,69) 0.35 (9,09) (7,0) 0.35 (9,09) A SQ B SQ (,23) (6,26) (,7) 0.93 (23,3).4 (2,99) 0.45 (,63) (6,76) 0.76 (9,32) (24,43).65 (29,59) (0,3) (2,5) (2,5) 0.50 (2,6).047 (26,6) 0.45 (,63) (4,22) (4,22) 0.5 (2,).063 (27,0) (0,5) 0.00 (0,25) 0.00 (2,03) (,63) (0,5) 0.00 (0,25) (,40) (,4) (,4) (0,9) 0.02 (0,7) (0,54) (,27) (,4) (0,9) / D 0/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice.. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDE MS-004 POST OFFIE BOX DALLAS, TEXAS 75265
9 MPDI002 JANUARY 995 REVISED DEEMBER N (R-PDIP-T**) 6 PINS SHOWN PLASTI DUAL-IN-LINE PAKAGE DIM PINS ** A A MAX (9,69) (9,69) (23,37).060 (26,92) 6 9 A MIN (,92) (,92) 0.50 (2,59) (23,) (6,60) (6,0) MS-00 VARIATION AA BB A AD (,7) (,4) D (,4) (0,76) D (0,5) MIN (,26) (7,62) 0.05 (0,3) (5,0) MAX Gauge Plane Seating Plane 0.25 (3,) MIN 0.00 (0,25) NOM 0.02 (0,53) 0.05 (0,3) 0.00 (0,25) 0.00 (2,54) M (0,92) MAX 4/ PIN ONLY 20 pin vendor option D /E 2/2002 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice.. Falls within JEDE MS-00, except and 20 pin minimum body lrngth (Dim A). D. The 20 pin end lead shoulder width is a vendor option, either half or full width. POST OFFIE BOX DALLAS, TEXAS 75265
10 MEHANIAL DATA MSOI002B JANUARY 995 REVISED SEPTEMBER 200 D (R-PDSO-G**) PLASTI SMALL-OUTLINE PAKAGE PINS SHOWN (,27) (0,5) 0.04 (0,35) 0.00 (0,25) (6,20) 0.22 (5,0) 0.00 (0,20) NOM 0.57 (4,00) 0.50 (3,) Gage Plane 4 A (0,25) (,2) 0.06 (0,40) Seating Plane (,75) MAX 0.00 (0,25) (0,0) (0,0) DIM PINS ** 4 6 A MAX 0.97 (5,00) (,75) (0,00) A MIN (4,0) (,55) 0.36 (9,0) /E 09/0 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice.. Body dimensions do not include mold flash or protrusion, not to exceed (0,5). D. Falls within JEDE MS-02 POST OFFIE BOX DALLAS, TEXAS 75265
11
12 MEHANIAL DATA MSSO002E JANUARY 995 REVISED DEEMBER 200 DB (R-PDSO-G**) 2 PINS SHOWN PLASTI SMALL-OUTLINE 0,65 0,3 0,22 0,5 M 2 5 5,60 5,00,20 7,40 0,25 0,09 Gage Plane 4 0,25 A 0 0,95 0,55 2,00 MAX 0,05 MIN Seating Plane 0,0 DIM PINS ** A MAX 6,50 6,50 7,50,50 0,50 0,50 2,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 2, /E 2/0 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice.. Body dimensions do not include mold flash or protrusion not to exceed 0,5. D. Falls within JEDE MO-50 POST OFFIE BOX DALLAS, TEXAS 75265
13 MEHANIAL DATA MTSS00 JANUARY 995 REVISED FEBRUARY 999 PW (R-PDSO-G**) 4 PINS SHOWN PLASTI SMALL-OUTLINE PAKAGE 0,30 0,65 0,0 M 0,9 4 4,50 4,30 6,60 6,20 0,5 NOM Gage Plane A 7 0 0,25 0,75 0,50,20 MAX 0,5 0,05 Seating Plane 0,0 DIM PINS ** A MAX 3,0 5,0 5,0 6,60 7,90 9,0 A MIN 2,90 4,90 4,90 6,40 7,70 9, /F 0/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice.. Body dimensions do not include mold flash or protrusion not to exceed 0,5. D. Falls within JEDE MO-53 POST OFFIE BOX DALLAS, TEXAS 75265
14 IMPORTANT NOTIE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. ustomers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. ustomers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio Data onverters dataconverter.ti.com Automotive DSP dsp.ti.com Broadband Interface interface.ti.com Digital ontrol Logic logic.ti.com Military Power Mgmt power.ti.com Optical Networking Microcontrollers microcontroller.ti.com Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box Dallas, Texas opyright 2003, Texas Instruments Incorporated
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Operating Range 2-V to 5.5-V V CC 3-State s Directly Drive Bus Lines Latch-Up Performance Exceeds 250 ma Per JESD 17 description The AHC573 devices are octal traparent D-type latches designed for 2-V to
More informationDistributed by: www.jameco.com 1-800-81-4242 The content and copyrights of the attached material are the property of its owner. Operating Range 2-V to.-v V CC Latch-Up Performance Exceeds 20 ma Per JESD
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AM6LS SLLSG JANUARY 979 REVISED FEBRUARY Meets or Exceeds the Requirements of ANSI TIA/EIA--B and ITU Recommendation V. Operates From a Single -V Supply TTL Compatible Complementary Outputs High Output
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A Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage Speed of Bipolar F, AS, and S, With Significantly Reduced Power oumption Balanced Propagation Delays ±24-mA
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CD54AC08, CD74AC08 QUADRUPLE 2-INPUT POSITIVE-AND GATES AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage Speed of Bipolar F, AS, and S, With Significantly
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Operation From Very Slow Input Transitions Temperature-Compensated Threshold Levels High Noise Immunity Same Pinouts as HC00 Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB),
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2-V to 5.5-V V CC Operation Typical V OLP (Output Ground Bounce) 2.3 V at V CC = 3.3 V, T A = 25 C Support Mixed-Mode Voltage
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Dependable Texas Instruments Quality and Reliability description These devices contain six independent inverters. SN5404, SN54LS04, SN54S04, SN5404... J PACKAGE SN54LS04, SN54S04... J OR W PACKAGE SN7404...
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Member of Texas Instruments Widebus Family State-of-the-Art Advanced Low-Voltage BiCMOS (ALB) Technology Design for.-v Operation Schottky Diodes on All s to Eliminate Overshoot and Undershoot Industry
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SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244 3-State s Drive Bus Lines or Buffer Memory Address Registers PNP s Reduce DC Loading Hysteresis at s Improves Noise Margins description These
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Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 200 Per MIL-STD-883, Method 3015; Exceeds 20 Using Machine Model (C =
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Member of Texas Instruments Widebus Family Latch-Up Performance Exceeds 250 ma Per JESD 17 description This 16-bit (dual-octal) noninverting bus transceiver contains two separate supply rails; B port has
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Member of Texas Instruments Widebus Family Latch-Up Performance Exceeds 250 ma Per JESD 17 ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) Bus Hold on Data
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ALS174 and AS174 Contain Six Flip-Flops With Single-Rail Outputs ALS175 and AS175B Contain Four Flip-Flops With Double-Rail Outputs Buffered Clock and Direct-Clear Inputs SN54ALS174, SN54ALS175, SN54AS174,
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Low Output Skew for Clock-Distribution and Clock-Generation Applications Operates at 3.3-V Distributes Differential LVPECL Clock Inputs to 12 TTL-Compatible Outputs Two Select Inputs Configure Up to Nine
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More informationDistributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. SN54HC04, SN74HC04 HEX INVERTERS SCLS078D DECEMBER 1982 REVISED JULY 2003
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