SN55110A, SN75110A, SN75112 DUAL LINE DRIVERS

Size: px

Start display at page:

Download "SN55110A, SN75110A, SN75112 DUAL LINE DRIVERS"

Jonah Warren
5 years ago
Views:

1 SN0A, SN70A, SN72 SLLS06F DECEMBER 97 REVISED JULY 2003 Improved Stability Over Supply Voltage and Temperature Ranges Constant-Current Outputs High Speed Standard Supply Voltages High Output Impedance High Common-Mode Output Voltage Range... 3 V to 0 V TTL-Input Compatibility Inhibitor Available for Driver Selection Glitch Free During Power Up/Power Down SN72 and External Circuit Meets or Exceeds the Requirements of CCITT Recommendation V.3 description/ordering information The SN0A, SN70A, and SN72 dual line drivers have improved output current regulation with supply-voltage and temperature variations. In addition, the higher current of the SN72 (27 ma) allows data to be transmitted over longer lines. These drivers offer optimum performance when used with the SN07A, SN707A, and SN708A line receivers. SN0A...J OR W PACKAGE SN70A... D, N, OR NS PACKAGE SN72...D OR N PACKAGE (TOP VIEW) C NC 2C NC 2A A B C 2C 2A 2B GND V CC+ Y Z V CC D 2Z 2Y SN0A... FK PACKAGE (TOP VIEW) B A NC B GND NC 2Y V CC+ 2Z Y NC No internal connection Z NC V CC NC D TA 0 C to 70 C C to2 C ORDERING INFORMATION PACKAGE PDIP (N) Tube of 2 SOIC (D) Tube of 0 Reel of 200 Tube of 0 Reel of 200 ORDERABLE PART NUMBER SN70AN SN72N SN70AD SN70ADR SN72D SN72DR TOP-SIDE MARKING SN70AN SN72N SN70A SN72A SOP (NS) Reel of 2000 SN70ANSR SN70A CDIP (J) Tube of 2 SN0AJ SNJ0AJ SN0AJ SNJ0AJ CFP (W) Tube of 0 SNJ0AW SNJ0AW LCCC (FK) Tube of SNJ0AFK SNJ0AFK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2003, Texas Instruments Incorporated On products compliant to MIL-PRF-383, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 6303 DALLAS, TEXAS 726

2 SN0A, SN70A, SN72 SLLS06F DECEMBER 97 REVISED JULY 2003 description/ordering information (continued) These drivers feature independent channels with common voltage supply and ground terminals. The significant difference between the three drivers is in the output-current specification. The driver circuits feature a constant output current that is switched to either of two output terminals by the appropriate logic levels at the input terminals. The output current can be switched off (inhibited) by low logic levels on the enable inputs. The output current is nominally 2 ma for the 0A devices, and is 27 ma for the SN72. The enable/inhibit feature is provided so the circuits can be used in party-line or data-bus applications. A strobe or inhibitor (enable D), common to both drivers, is included for increased driver-logic versatility. The output current in the inhibited mode, I O(off), is specified so that minimum line loading is induced when the driver is used in a party-line system with other drivers. The output impedance of the driver in the inhibited mode is very high. The output impedance of a transistor is biased to cutoff. The driver outputs have a common-mode voltage range of 3 V to 0 V, allowing common-mode voltage on the line without affecting driver performance. All inputs are diode clamped and are designed to satisfy TTL-system requirements. The inputs are tested at 2 V for high-logic-level input conditions and 0.8 V for low-logic-level input conditions. These tests ensure 400-mV noise margin when interfaced with TTL Series 4/74 devices. The SN0A is characterized for operation over the full military temperature range of C to 2 C. The SN70A and SN72 are characterized for operation from 0 C to 70 C. LOGIC INPUTS FUNCTION TABLE (each driver) ENABLE INPUTS OUTPUTS A B C D Y Z X X L X Off Off X X X L Off Off L X H H On Off X L H H On Off H H H H Off On H = high level, L = low level, X = irrelevant When using only one channel of the line drivers, the other channel should be inhibited and/or have its outputs grounded. 2 POST OFFICE BOX 6303 DALLAS, TEXAS 726

3 SN0A, SN70A, SN72 SLLS06F DECEMBER 97 REVISED JULY 2003 schematic (each driver) VCC kω NOM C D 3, 4 0 To Other Driver kω NOM A B GND, 2, 6 7 8, 3 9, 2 Y Z Common to Both Drivers + VCC +...VCC+ Bus...VCC Bus To Other Driver Pin numbers shown are for the D, J, N, NS, and W packages. POST OFFICE BOX 6303 DALLAS, TEXAS 726 3

4 SN0A, SN70A, SN72 SLLS06F DECEMBER 97 REVISED JULY 2003 absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage: V CC+ (see Note ) V V CC (see Note ) V Input voltage, V I V Output voltage range, V O V to 2 V Package thermal impedance, θ JA (see Notes 2 and 3): D package C/W N package C/W NS package C/W Package thermal impedance, θ JC (see Notes 4 and ): FK package C/W J package C/W W package C/W Case temperature for 60 seconds: FK package C Lead temperature,6 mm (/6 inch) from case for 60 seconds: J or W package C Lead temperature,6 mm (/6 inch) from case for 0 seconds: D, N, or NS package C Storage temperature range, T stg C to 0 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. Voltage values are with respect to network ground terminal. 2. Maximum power dissipation is a function of TJ(max), θ JA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) TA)/θ JA. Operating at the absolute maximum TJ of 0 C can affect reliability. 3. The package thermal impedance is calculated in accordance with JESD Maximum power dissipation is a function of TJ(max), θ JC, and TC. The maximum allowable power dissipation at any allowable case temperature is PD = (TJ(max) TC)/θ JC. Operating at the absolute maximum TJ of 0 C can affect reliability.. The package thermal impedance is calculated in accordance with MIL-STD-883. recommended operating conditions (see Note 6) SN0A SN70A SN72 UNIT MIN NOM MAX MIN NOM MAX VCC+ Supply voltage V VCC Supply voltage V Positive common-mode output voltage V Negative common-mode output voltage V VIH High-level input voltage 2 2 V VIL Low-level output current V TA Operating free-air temperature C NOTE 6: When using only one channel of the line drivers, the other channel should be inhibited and/or have its outputs grounded. 4 POST OFFICE BOX 6303 DALLAS, TEXAS 726

5 SN0A, SN70A, SN72 SLLS06F DECEMBER 97 REVISED JULY 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SN0A SN72 SN70A MIN TYP MAX MIN TYP MAX VIK Input clamp voltage VCC± = MIN, IL = 2 ma V VCC = MIN to MAX, IO(on) On-state output current VO = V to V, TA = 2 C VCC± = MAX, VO = 0 V VCC± = MIN, VO = 3 V UNIT ma IO(off) Off-state output current VCC± = MIN, VO = 0 V µa II IIH Input current at maximum input voltage High-level input current A, B, or C inputs D input A, B, or C inputs D input Low-level A, B, or C inputs IIL input current D input ICC+(on) ICC (on) ICC+(off) ICC (off) Supply current from VCC with driver enabled Supply current from VCC with driver enabled Supply current from VCC with driver inhibited Supply current from VCC± with driver inhibited VCC± = MAX, VI =V. VCC± = MAX, VI =24V 2.4 VCC± = MAX, VI =04V 0.4 VCC± = MAX, A and B inputs at 0.4 V, C and D inputs at 2 V ma µa ma ma VCC± = MAX, AandBinputs at 0.4 V, ma C and D inputs at 2 V VCC± = MAX, A, B, C, and D inputs at 0.4 V VCC± = MAX, A, B, C, and D inputs at 0.4 V For conditions shown as MIN or MAX, use appropriate value specified under recommended operating conditions. All typical values are at VCC+ = V, VCC = V, TA = 2 C. switching characteristics, V CC± = ± V, T A = 2 C (see Figure ) PARAMETER tplh tphl FROM (INPUT) TO (OUTPUT) AorB YorZ CL =40pF pf, RL =0Ω Ω, tplh CorD YorZ CL =40pF pf, RL =0Ω Ω, tphl tplh = Propagation delay time, low- to high-level output tphl = Propagation delay time, high- to low-level output 2 30 ma 7 32 ma TEST CONDITIONS MIN TYP MAX UNIT ns ns POST OFFICE BOX 6303 DALLAS, TEXAS 726

6 SN0A, SN70A, SN72 SLLS06F DECEMBER 97 REVISED JULY 2003 PARAMETER MEASUREMENT INFORMATION Input A or B VCC+ VCC 0 Ω Pulse Generator (See Note B) 890 Ω 890 Ω RL = 0 Ω Output Y CL = 40 pf (see Note A) Pulse Generator (See Note B) RL = 0 Ω Output Z CL = 40 pf (see Note A) Input C or D To Other Driver 0 Ω See Note C TEST CIRCUIT Input A or B 0% 0% 3 V 0 V Enable C or D tw tw2 0% 0% 3 V 0 V tplh tphl tplh tphl Output Y 0% 0% 0% 0% Off On tphl tplh Output Z 0% 0% VOLTAGE WAVEFORMS Off On NOTES: A. CL includes probe and jig capacitance. B. The pulse generators have the following characteristics: ZO = 0 Ω, tr = tf = 0 ± ns, tw = 00 ns, PRR MHz, tw2 = µs, PRR 00 khz. C. For simplicity, only one channel and the enable connections are shown. Figure. Test Circuit and Voltage Waveforms 6 POST OFFICE BOX 6303 DALLAS, TEXAS 726

7 SN0A, SN70A, SN72 SLLS06F DECEMBER 97 REVISED JULY 2003 TYPICAL CHARACTERISTICS I O(on) On-State Output Current ma SN0A, SN70A ON-STATE OUTPUT CURRENT vs NEGATIVE SUPPLY VOLTAGE VCC+ = 4. V VO = 3 V TA = 2 C I O(on) On-State Output Current ma SN72 ON-STATE OUTPUT CURRENT vs NEGATIVE SUPPLY VOLTAGE VCC+ = 4. V VO = 3 V TA = 2 C VCC Negative Supply Voltage V VCC Negative Supply Voltage V 7 Figure 2 Figure 3 POST OFFICE BOX 6303 DALLAS, TEXAS 726 7

8 SN0A, SN70A, SN72 SLLS06F DECEMBER 97 REVISED JULY 2003 APPLICATION INFORMATION special pulse-control circuit Figure 4 shows a circuit that can be used as a pulse-generator output or in many other testing applications. INPUT A OUTPUTS Y Z High Low Off On On Off V Input 2. V A B C VCC+ Y Z D GND /2 0A or SN72 VCC To Other Logic and Strobe Inputs V Output Input Pulse Switch Position 0 V Output Pulse 0 V Figure 4. Pulse-Control Circuit 8 POST OFFICE BOX 6303 DALLAS, TEXAS 726

9 SN0A, SN70A, SN72 SLLS06F DECEMBER 97 REVISED JULY 2003 APPLICATION INFORMATION using the SN72 as a CCITT-recommended V.3 line driver The SN72 dual line driver, the SN707A dual line receiver, and some external resistors can be used to implement the data-interchange circuit of CCITT recommendation V.3 (976) modem specification. The circuit of one channel is shown in Figure and meets the requirement of the interface as specified by Appendix of CCITT V.3 and is summarized in Table (V.3 has been replaced by ITU V.). Table. CCITT V.3 Electrical Requirements GENERATOR MIN MAX UNIT Source impedance, Zsource 0 0 Ω Resistance to ground, R 3 6 Ω Differential output voltage, VOD mv 0% to 90% rise time, tr 40 ns or 0.0 ui Common-mode output voltage, VOC V LOAD (RECEIVER) MIN MAX UNIT Input impedance, ZI 90 0 Ω Resistance to ground, R 3 6 Ω ui = unit interval or minimum signal-element pulse duration V V V R3 390 Ω A Data In B Enable C /2 SN R4 390 Ω 00 pf Y Z 00 pf R.3 kω R 7 Ω R2.3 kω R6 0 Ω R8 2 Ω R7 0 Ω A B 2 Strobe 6 /2 SN707A 4 Data Out Y Enable G All resistors are %, /4 W. V Figure. CCITT-Recommended V.3 Interface Using the SN72 and SN707A POST OFFICE BOX 6303 DALLAS, TEXAS 726 9

11 MECHANICAL DATA MCFP002A JANUARY 99 REVISED FEBRUARY 2002 W (R-GDFP-F4) CERAMIC DUAL FLATPACK 0.04 (,4) (0,66) (6,60) 0.23 (,97) Base and Seating Plane (2,03) 0.04 (,4) (0,20) (0,0) (7,) MAX (0,48) 0.0 (0,38) 0.00 (,27) (9,9) 0.33 (8,) 0.00 (0,3) MIN 4 Places (9,4) 0.20 (6,3) (9,4) 0.20 (6,3) / C 02/02 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification only. E. Falls within MIL STD 83 GDFP-F4 and JEDEC MO-092AB POST OFFICE BOX 6303 DALLAS, TEXAS 726

12 MECHANICAL DATA MLCC006B OCTOBER 996 FK (S-CQCC-N**) 28 TERMINAL SHOWN LEADLESS CERAMIC CHIP CARRIER NO. OF TERMINALS ** MIN A MAX MIN B MAX (8,69) 0.38 (9,09) (7,80) 0.38 (9,09) A SQ B SQ (,23) (6,26) (8,78) (23,83).4 (28,99) 0.48 (,63) (6,76) 0.76 (9,32) (24,43).6 (29,9) (0,3) 0.49 (2,8) 0.49 (2,8) 0.80 (2,6).047 (26,6) 0.48 (,63) 0.60 (4,22) 0.60 (4,22) 0.88 (2,8).063 (27,0) (0,) 0.00 (0,2) (2,03) (,63) (0,) 0.00 (0,2) 0.0 (,40) 0.04 (,4) 0.04 (,4) 0.03 (0,89) (0,7) (0,4) 0.00 (,27) 0.04 (,4) 0.03 (0,89) / D 0/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-004 POST OFFICE BOX 6303 DALLAS, TEXAS 726

13 MPDI002C JANUARY 99 REVISED DECEMBER N (R-PDIP-T**) 6 PINS SHOWN PLASTIC DUAL-IN-LINE PACKAGE DIM PINS ** A A MAX 0.77 (9,69) 0.77 (9,69) (23,37).060 (26,92) 6 9 A MIN 0.74 (8,92) 0.74 (8,92) 0.80 (2,9) (23,88) (6,60) (6,0) C MS-00 VARIATION AA BB AC AD (,78) 0.04 (,4) D (,4) (0,76) D (0,) MIN 0.32 (8,26) (7,62) 0.0 (0,38) (,08) MAX Gauge Plane Seating Plane 0.2 (3,8) MIN 0.00 (0,2) NOM 0.02 (0,3) 0.0 (0,38) 0.00 (0,2) 0.00 (2,4) M (0,92) MAX 4/8 PIN ONLY 20 pin vendor option D /E 2/2002 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-00, except 8 and 20 pin minimum body lrngth (Dim A). D. The 20 pin end lead shoulder width is a vendor option, either half or full width. POST OFFICE BOX 6303 DALLAS, TEXAS 726

14 MECHANICAL DATA MSOI002B JANUARY 99 REVISED SEPTEMBER 200 D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 8 PINS SHOWN 0.00 (,27) (0,) 0.04 (0,3) 0.00 (0,2) (6,20) (,80) (0,20) NOM 0.7 (4,00) 0.0 (3,8) Gage Plane 4 A (0,2) (,2) 0.06 (0,40) Seating Plane (,7) MAX 0.00 (0,2) (0,0) (0,0) DIM PINS ** A MAX 0.97 (,00) (8,7) (0,00) A MIN (4,80) (8,) (9,80) /E 09/0 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed (0,). D. Falls within JEDEC MS-02 POST OFFICE BOX 6303 DALLAS, TEXAS 726

16 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio Data Converters dataconverter.ti.com Automotive DSP dsp.ti.com Broadband Interface interface.ti.com Digital Control Logic logic.ti.com Military Power Mgmt power.ti.com Optical Networking Microcontrollers microcontroller.ti.com Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box 6303 Dallas, Texas 726 Copyright 2003, Texas Instruments Incorporated

SN54HC00, SN74HC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES

SN54HC00, SN74HC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS181E DECEMBER 1982 REVISED AUGUST 2003 Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption,