SN55451B, SN55452B, SN55453B, SN55454B SN75451B, SN75452B, SN75453B, SN75454B DUAL PERIPHERAL DRIVERS

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1 PERIPHERAL DRIVERS FOR HIGH-CURRENT SWITCHING AT VERY HIGH SPEEDS Characterized for Use to 00 ma High-Voltage Outputs No Output Latch-Up at 0 V (After Conducting 00 ma) High-Speed Switching Circuit Flexibility for Varied Applications TTL-Compatible Diode-Clamped Inputs Standard Supply Voltages Plastic DIP (P) With Copper Lead Frame Provides Cooler Operation and Improved Reliability Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 00-mil DIPs SUMMARY OF DEVICES DEVICE LOGIC OF COMPLETE CIRCUIT PACKAGES SNB AND FK, JG SNB NAND JG SNB OR FK, JG SNB NOR JG SNB AND D, P SNB NAND D, P SNB OR D, P SNB NOR D, P SNB, SNB, SNB, SNB SNB, SNB, SNB, SNB DUAL PERIPHERAL DRIVERS SLRS0B DECEMBER 9 REVISED SEPTEMBER 999 SNB, SNB, SNB, SNB... JG PACKAGE SNB, SNB, SNB, SNB...D OR P PACKAGE (TOP VIEW) A B Y V CC B A Y SNB, SNB SNB, SNB... FK PACKAGE (TOP VIEW) B Y A Y VCC No internal connection B A description The SNB through SNB and SNB through SNB are dual peripheral drivers designed for use in systems that employ TTL logic. This family is functionally interchangeable with and replaces the SN0 family and the SN0A family devices manufactured previously. The speed of the devices is equal to that of the SN0 family, and the parts are designed to ensure freedom from latch-up. Diode-clamped inputs simplify circuit design. Typical applications include high-speed logic buffers, power drivers, relay drivers, lamp drivers, MOS drivers, line drivers, and memory drivers. The SNB/SNB, SNB/SNB, SNB/SNB, and SNB/SNB are dual peripheral AND, NAND, OR, and NOR drivers, respectively (assuming positive logic), with the output of the logic gates internally connected to the bases of the npn output transistors. The SN drivers are characterized for operation over the full military range of C to C. The SN drivers are characterized for operation from 0 C to 0 C. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 999, Texas Instruments Incorporated POST OFFICE BOX 0 DALLAS, TEXAS

2 SNB, SNB, SNB, SNB SNB, SNB, SNB, SNB DUAL PERIPHERAL DRIVERS SLRS0B DECEMBER 9 REVISED SEPTEMBER 999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) SN SN UNIT Supply voltage, VCC (see Note ) V Input voltage, VI.. V Inter-emitter voltage (see Note ).. V Off-state output voltage, VO 0 0 V Continuous collector or output current, IOK (see Note ) ma Peak collector or output current, II (tw 0 ms, duty cycle 0%, see Note ) ma Continuous total power dissipation See Dissipation Rating Table Operating free-air temperature range, TA to 0 to 0 C Storage temperature range, Tstg to 0 to 0 C Case temperature for 0 seconds FK package 0 C Lead temperature, mm (/ inch) from case for 0 seconds JG package 00 C Lead temperature, mm (/ inch) from case for 0 seconds D or P package 0 C NOTES:. Voltage values are with respect to network, unless otherwise specified.. This is the voltage between two emitters of a multiple-emitter transistor.. This value applies when the base-emitter resistance (RBE) is equal to or less than 00 Ω.. Both halves of these dual circuits may conduct rated current simultaneously; however, power dissipation averaged over a short time interval must fall within the continuous dissipation rating. PACKAGE DISSIPATION RATING TABLE TA C DERATING FACTOR TA = 0 C TA = C POWER RATING ABOVE TA = C POWER RATING POWER RATING D mw.8 mw/ C mw FK mw.0 mw/ C 880 mw mw JG 00 mw 8. mw/ C mw 0 mw P 000 mw 8.0 mw/ C 0 mw recommended operating conditions SN SN MIN NOM MAX MIN NOM MAX UNIT Supply voltage, VCC.... V High-level input voltage, VIH V Low-level input voltage, VIL V Operating free-air temperature, TA 0 0 C POST OFFICE BOX 0 DALLAS, TEXAS

3 SNB, SNB, SNB, SNB SNB, SNB, SNB, SNB DUAL PERIPHERAL DRIVERS SLRS0B DECEMBER 9 REVISED SEPTEMBER 999 logic symbol logic diagram (positive logic) A B A B & This symbol is in accordance with ANSI/IEEE Std 9-98 and IEC publication -. Pin numbers shown are for the D, JG, and P packages. FUTION TABLE (each driver) Y Y A B A B schematic (each driver) Y Y VCC A B Y kω. kω 0 Ω L L L (on state) L H L (on state) H L L (on state) H H H (off state) positive logic: Y = AB or A+B A B kω 00 Ω Y electrical characteristics over recommended operating free-air temperature range PARAMETER TEST CONDITIONS SNB SNB MIN TYP MAX MIN TYP MAX VIK Input clamp voltage VCC = MIN, II = ma.... V VOL IOH Low-level output voltage High-level output current VCC = MIN, VIL = 0.8 V, IOL = 00 ma VCC = MIN, VIL = 0.8 V, IOL = 00 ma VCC = MIN, VOH = 0 V VIH = MIN, UNIT V µa II Input current at maximum input voltage VCC = MAX, VI =. V ma IIH High-level input current VCC = MAX, VI =. V 0 0 µa IIL Low-level input current VCC = MAX, VI = 0. V.. ma ICCH Supply current, outputs high VCC = MAX, VI = V ma ICCL Supply current, outputs low VCC = MAX, VI = 0 ma For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. All typical values are at VCC = V, TA = C. switching characteristics, V CC = V, T A = C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tplh Propagation delay time, low-to-high-level output 8 tphl Propagation delay time, high-to-low-level output IO O 00 ma, CL L = pf, 8 ttlh Transition time, low-to-high-level output RL = 0 Ω, See Figure 8 tthl Transition time, high-to-low-level output VOH High-level output voltage after switching Resistor values shown are nominal. SNB VS = 0 V, IO 00 ma, VS. SNB See Figure VS. ns mv POST OFFICE BOX 0 DALLAS, TEXAS

4 SNB, SNB, SNB, SNB SNB, SNB, SNB, SNB DUAL PERIPHERAL DRIVERS SLRS0B DECEMBER 9 REVISED SEPTEMBER 999 logic symbol A B A B & This symbol is in accordance with ANSI/IEEE Std 9-98 and IEC publication -. Pin numbers shown are for the D, JG, and P packages. FUTION TABLE (each driver) A B Y L L H (off state) L H H (off state) H L H (off state) H H L (on state) positive logic: Y = AB or A+B Y Y logic diagram (positive logic) A B A B schematic (each driver). kω kω. kω A B kω kω Resistor values shown are nominal. Y Y 0 Ω 00 Ω VCC Y electrical characteristics over recommended operating free-air temperature range PARAMETER TEST CONDITIONS SNB SNB MIN TYP MAX MIN TYP MAX VIK Input clamp voltage VCC = MIN, II = ma.... V VOL Low-level output voltage VCC = MIN, IOL = 00 ma VCC = MIN, IOL = 00 ma VIH = MIN, VIH = MIN, VCC = MIN, VIL = 0.8 V, IOH High-level output current VOH = 0 V UNIT V µa II Input current at maximum input voltage VCC = MAX, VI =. V ma IIH High-level input current VCC = MAX, VI =. V 0 0 µa IIL Low-level input current VCC = MAX, VI = 0. V.... ma ICCH Supply current, outputs high VCC = MAX, VI = 0 ma ICCL Supply current, outputs low VCC = MAX, VI = V ma For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. All typical values are at VCC = V, TA = C. switching characteristics, V CC = V, T A = C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tplh Propagation delay time, low-to-high-level output tphl Propagation delay time, high-to-low-level output IO O 00 ma, CL L = pf, ttlh Transition time, low-to-high-level output RL = 0 Ω, See Figure 8 tthl Transition time, high-to-low-level output VOH High-level output voltage after switching SNB VS = 0 V, IO 00 ma, VS. SNB See Figure VS. ns mv POST OFFICE BOX 0 DALLAS, TEXAS

5 SNB, SNB, SNB, SNB SNB, SNB, SNB, SNB DUAL PERIPHERAL DRIVERS SLRS0B DECEMBER 9 REVISED SEPTEMBER 999 logic symbol logic diagram (positive logic) A B A B This symbol is in accordance with ANSI/IEEE Std 9-98 and IEC publication -. Pin numbers shown are for the D, JG, and P packages. FUTION TABLE (each driver) A B Y L L L (on state) L H H (off state) H L H (off state) H H H (off state) positive logic: Y = A+B or A B Y Y electrical characteristics over recommended operating free-air temperature range PARAMETER TEST CONDITIONS A B A B Y Y SNB SNB MIN TYP MAX MIN TYP MAX VIK Input clamp voltage VCC = MIN, II = ma.... V VOL Low-level output voltage VCC = MIN, IOH High-level output current VOH = 0 V VCC = MIN, VIL = 0.8 V, IOL = 00 ma VCC = MIN, VIL = 0.8 V, IOL = 00 ma VIH = MIN, UNIT V µa II Input current at maximum input voltage VCC = MAX, VI =. V ma IIH High-level input current VCC = MAX, VI =. V 0 0 µa IIL Low-level input current VCC = MAX, VI = 0. V.. ma ICCH Supply current, outputs high VCC = MAX, VI = V 8 8 ma ICCL Supply current, outputs low VCC = MAX, VI = ma For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. All typical values are at VCC = V, TA = C. switching characteristics, V CC = V, T A = C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tplh Propagation delay time, low-to-high-level output 8 tphl Propagation delay time, high-to-low-level output IO 00 ma, CL = pf, 8 ttlh Transition time, low-to-high-level output RL = 0 Ω, See Figure 8 tthl Transition time, high-to-low-level output VOH High-level output voltage after switching A B schematic (each driver) kω. kω kω 0 Ω kω Resistor values shown are nominal. 00 Ω SNB VS S = 0 V, IO O 00 ma, VS. SNB See Figure VS. VCC Y ns mv POST OFFICE BOX 0 DALLAS, TEXAS

6 SNB, SNB, SNB, SNB SNB, SNB, SNB, SNB DUAL PERIPHERAL DRIVERS SLRS0B DECEMBER 9 REVISED SEPTEMBER 999 logic symbol A B A B This symbol is in accordance with ANSI/IEEE Std 9-98 and IEC publication -. Pin numbers shown are for the D, JG, and P packages. FUTION TABLE (each driver) A B Y L L H (off state) L H L (on state) H L L (on state) H H L (on state) positive logic: Y = A+B or AB Y Y logic diagram (positive logic) electrical characteristics over recommended operating free-air temperature range PARAMETER TEST CONDITIONS A B A B Y Y SNB SNB MIN TYP MAX MIN TYP MAX VIK Input clamp voltage VCC = MIN, II = ma.... V VOL Low-level output voltage VCC = MIN, IOL = 00 ma VCC = MIN, IOL = 00 ma VIH = MIN, VIH = MIN, VCC = MIN, VIL = 0.8 V, IOH High-level output current VOH = 0 V UNIT V µa II Input current at maximum input voltage VCC = MAX, VI =. V ma IIH High-level input current VCC = MAX, VI =. V 0 0 µa IIL Low-level input current VCC = MAX, VI = 0. V.. ma ICCH Supply current, outputs high VCC = MAX, VI = 0 ma ICCL Supply current, outputs low VCC = MAX, VI = V 9 9 ma For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. All typical values are at VCC = V, TA = C. switching characteristics, V CC = V, T A = C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tplh Propagation delay time, low-to-high-level output tphl Propagation delay time, high-to-low-level output IO 00 ma, CL = pf, ttlh Transition time, low-to-high-level output RL = 0 Ω, See Figure 8 tthl Transition time, high-to-low-level output VOH High-level output voltage after switching A B schematic (each driver) kω kω kω kω Resistor values shown are nominal. kω kω. kω SNB VS S = 0 V, IO O 00 ma, VS. SNB See Figure VS. 0 Ω 00 Ω VCC Y ns mv POST OFFICE BOX 0 DALLAS, TEXAS

7 PARAMETER MEASUREMENT INFORMATION SNB, SNB, SNB, SNB SNB, SNB, SNB, SNB DUAL PERIPHERAL DRIVERS SLRS0B DECEMBER 9 REVISED SEPTEMBER 999 Pulse Generator (see Note A) Input. V B B B B 0. V TEST CIRCUIT RL = 0 Ω Circuit Under Test SUB 0 V Output CL = pf (see Note B) ns 90% Input B. V B Input B B 0% Output ns 90% 0 ns 90%. V 0% 0% 0. µs 0 ns 90% 90%. V. V 0% tphl tplh 90% 0% 0% 0% 0% tthl ttlh V 0 V V 0 V VOH VOL VOLTAGE WAVEFORMS NOTES: A. The pulse generator has the following characteristics: PRR MHz, ZO = 0 Ω. B. CL includes probe and jig capacitance. Figure. Test Circuit and Voltage Waveforms, Complete Drivers Pulse Generator (see Note A) Input. V B B B B V N0 Circuit Under Test VS = 0 V SUB mh Ω ns 90% Input B. V B Output Input B B 0% CL = pf (see Note B) Output 0% 0% 0 µs ns 90% 90%. V. V 0 ns 90%. V 0 ns 0% V 0 V V 0 V VOH 0. V VOL TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. The pulse generator has the following characteristics: PRR. khz, ZO = 0 Ω. B. CL includes probe and jig capacitance. Figure. Test Circuit and Voltage Waveforms for Latch-Up Test of Complete Drivers POST OFFICE BOX 0 DALLAS, TEXAS

8 SNB, SNB, SNB, SNB SNB, SNB, SNB, SNB DUAL PERIPHERAL DRIVERS SLRS0B DECEMBER 9 REVISED SEPTEMBER 999 TYPICAL CHARACTERISTICS VCE(sat) Collector-Emitter Saturation Voltage V TRANSISTOR COLLECTOR-EMITTER SATURATION VOLTAGE vs COLLECTOR CURRENT 0. IC = 0 IB 0. See Note A TA = 0 C TA = C TA = 0 C IC Collector Current ma 00 NOTE A: These parameters must be measured using pulse techniques, tw = 00 µs, duty cycle %. Figure 8 POST OFFICE BOX 0 DALLAS, TEXAS

9 PACKAGE OPTION ADDENDUM -Jan-00 PACKAGING INFORMATION Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan () Lead/Ball Finish MSL Peak Temp () 9-90QA ACTIVE LCCC FK 0 TBD POST-PLATE N / A for Pkg Type 9-90QPA ACTIVE CDIP JG 8 TBD A SNPB N / A for Pkg Type 090A ACTIVE LCCC FK 0 TBD POST-PLATE N / A for Pkg Type 090PA ACTIVE CDIP JG 8 TBD A SNPB N / A for Pkg Type 090A ACTIVE LCCC FK 0 TBD POST-PLATE N / A for Pkg Type 090PA ACTIVE CDIP JG 8 TBD A SNPB N / A for Pkg Type JM80/90BPA ACTIVE CDIP JG 8 TBD A SNPB N / A for Pkg Type JM80/90BPA ACTIVE CDIP JG 8 TBD A SNPB N / A for Pkg Type JM80/90BPA ACTIVE CDIP JG 8 TBD A SNPB N / A for Pkg Type SNBJG ACTIVE CDIP JG 8 TBD A SNPB N / A for Pkg Type SNBJG ACTIVE CDIP JG 8 TBD A SNPB N / A for Pkg Type SNBJG ACTIVE CDIP JG 8 TBD A SNPB N / A for Pkg Type SNBJG ACTIVE CDIP JG 8 TBD A SNPB N / A for Pkg Type SNBD ACTIVE SOIC D 8 Green (RoHS & SNBDE ACTIVE SOIC D 8 Green (RoHS & SNBDR ACTIVE SOIC D 8 00 Green (RoHS & SNBDRE ACTIVE SOIC D 8 00 Green (RoHS & SNBP ACTIVE PDIP P 8 0 Pb-Free (RoHS) SNBPE ACTIVE PDIP P 8 0 Pb-Free (RoHS) SNBPSR ACTIVE SO PS Green (RoHS & SNBPSRE ACTIVE SO PS Green (RoHS & SNBD ACTIVE SOIC D 8 Green (RoHS & SNBDE ACTIVE SOIC D 8 Green (RoHS & SNBDR ACTIVE SOIC D 8 00 Green (RoHS & SNBDRE ACTIVE SOIC D 8 00 Green (RoHS & SNBP ACTIVE PDIP P 8 0 Pb-Free (RoHS) SNBPE ACTIVE PDIP P 8 0 Pb-Free (RoHS) SNBPSR ACTIVE SO PS Green (RoHS & SNBPSRE ACTIVE SO PS Green (RoHS & SNBD ACTIVE SOIC D 8 Green (RoHS & N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type Addendum-Page

10 PACKAGE OPTION ADDENDUM -Jan-00 Orderable Device Status () Package Type Package Drawing Pins Package Qty SNBDE ACTIVE SOIC D 8 Green (RoHS & SNBDR ACTIVE SOIC D 8 00 Green (RoHS & SNBDRE ACTIVE SOIC D 8 00 Green (RoHS & SNBP ACTIVE PDIP P 8 0 Pb-Free (RoHS) SNBPE ACTIVE PDIP P 8 0 Pb-Free (RoHS) SNBPSR ACTIVE SO PS Green (RoHS & SNBPSRE ACTIVE SO PS Green (RoHS & SNBD ACTIVE SOIC D 8 Green (RoHS & SNBDE ACTIVE SOIC D 8 Green (RoHS & SNBDR ACTIVE SOIC D 8 00 Green (RoHS & SNBDRE ACTIVE SOIC D 8 00 Green (RoHS & SNBP ACTIVE PDIP P 8 0 Pb-Free (RoHS) SNBPE ACTIVE PDIP P 8 0 Pb-Free (RoHS) SNBPSR ACTIVE SO PS Green (RoHS & SNBPSRE ACTIVE SO PS Green (RoHS & Eco Plan () Lead/Ball Finish MSL Peak Temp () N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type SNJBFK ACTIVE LCCC FK 0 TBD POST-PLATE N / A for Pkg Type SNJBJG ACTIVE CDIP JG 8 TBD A SNPB N / A for Pkg Type SNJBFK ACTIVE LCCC FK 0 TBD POST-PLATE N / A for Pkg Type SNJBJG ACTIVE CDIP JG 8 TBD A SNPB N / A for Pkg Type SNJBFK ACTIVE LCCC FK 0 TBD POST-PLATE N / A for Pkg Type SNJBJG ACTIVE CDIP JG 8 TBD A SNPB N / A for Pkg Type SNJBFK OBSOLETE LCCC FK 0 TBD POST-PLATE N / A for Pkg Type SNJBJG ACTIVE CDIP JG 8 TBD A SNPB N / A for Pkg Type () The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. () Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all substances, including the requirement that lead not exceed 0.% by weight in homogeneous materials. Where designed to be soldered Addendum-Page

11 PACKAGE OPTION ADDENDUM -Jan-00 at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either ) lead-based flip-chip solder bumps used between the die and package, or ) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & : TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.% by weight in homogeneous material) () MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page

12 MECHANICAL DATA MCER00A JANUARY 99 REVISED JANUARY 99 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.00 (0,) 0. (9,00) (,) 0. (,) 0.0 (,) 0.0 (,) 0.0 (,0) 0.0 (0,8) 0.00 (0,) MIN 0.0 (,8) 0.90 (,) 0.00 (,08) MAX Seating Plane 0.0 (,0) MIN 0.00 (,) 0.0 (0,8) 0.0 (0,8) 0.0 (0,) (0,0) 0 000/C 08/9 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 8 GDIP-T8 POST OFFICE BOX 0 DALLAS, TEXAS

13 MECHANICAL DATA MLCC00B OCTOBER 99 FK (S-CQCC-N**) 8 TERMINAL SHOWN LEADLESS CERAMIC CHIP CARRIER 8 NO. OF TERMINALS ** MIN A MAX MIN B MAX (8,9) 0.8 (9,09) 0.0 (,80) 0.8 (9,09) A SQ B SQ (,) 0.0 (,) 0.9 (8,8) 0.98 (,8). (8,99) 0.8 (,) 0.0 (,) 0. (9,) 0.9 (,). (9,9) 0.0 (0,) 0.9 (,8) 0.9 (,8) 0.80 (,).0 (,) 0.8 (,) 0.0 (,) 0.0 (,) 0.88 (,8).0 (,0) 0.00 (0,) 0.00 (0,) (,0) 0.0 (,) 0.00 (0,) 0.00 (0,) 0.0 (,0) 0.0 (,) 0.0 (,) 0.0 (0,89) 0.08 (0,) 0.0 (0,) 0.00 (,) 0.0 (,) 0.0 (0,89) 000/ D 0/9 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-00 POST OFFICE BOX 0 DALLAS, TEXAS

14 MECHANICAL DATA MPDI00A JANUARY 99 REVISED JUNE 999 P (R-PDIP-T8) PLASTIC DUAL-IN-LINE (0,0) 0. (9,0) 0.0 (,0) 0.0 (,0) 0.00 (,8) MAX 0.00 (0,) MIN 0. (8,) 0.00 (,) 0.0 (0,8) 0.00 (,08) MAX Gage Plane Seating Plane 0. (,8) MIN 0.00 (0,) NOM 0.0 (0,) 0.0 (0,8) 0.00 (,) 0.00 (0,) M 0.0 (0,9) MAX 0008/D 0/98 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-00 For the latest package information, go to POST OFFICE BOX 0 DALLAS, TEXAS

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SN55451B, SN55452B, SN55453B, SN55454B SN75451B, SN75452B, SN75453B, SN75454B DUAL PERIPHERAL DRIVERS

SN55451B, SN55452B, SN55453B, SN55454B SN75451B, SN75452B, SN75453B, SN75454B DUAL PERIPHERAL DRIVERS PERIPHERAL DRIVERS FOR HIGH-CURRENT SWITCHING AT VERY HIGH SPEEDS Characterized for Use to 00 ma High-Voltage Outputs No Output Latch-Up at 0 V (After Conducting 00 ma) High-Speed Switching Circuit Flexibility