GENERAL-PURPOSE OPERATIONAL AMPLIFIERS

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1 µa71, µa71y Short-Circuit Protection Offset-Voltage Null Capability Large Common-Mode and Differential Voltage Ranges No Frequency Compensation Required Low Power Consumption No Latch-Up Designed to Be Interchangeable With Fairchild µa71 OFFSET N1 IN IN+ V CC µa71m...j PACKAGE (TOP VIEW) V CC + OUT OFFSET N2 description symbol The µa71 is a general-purpose operational amplifier featuring offset-voltage null capability. The high common-mode input voltage range and the absence of latch-up make the amplifier ideal for voltage-follower applications. The device is short-circuit protected and the internal frequency compensation ensures stability without external components. A low value potentiometer may be connected between the offset null inputs to null out the offset voltage as shown in Figure 2. The µa71c is characterized for operation from C to 7 C. The µa71i is characterized for operation from C to 5 C.The µa71m is characterized for operation over the full military temperature range of 55 C to 125 C. OFFSET N1 µa71m...jg PACKAGE µa71c, µa71i... D, P, OR PW PACKAGE (TOP VIEW) OFFSET N1 IN IN+ V CC OFFSET N1 IN IN+ V CC µa71m...u PACKAGE (TOP VIEW) µa71m... FK PACKAGE (TOP VIEW) V CC+ OUT OFFSET N2 V CC + OUT OFFSET N2 IN + IN OFFSET N2 + OUT OFFSET N1 IN IN V CC + OUT V CC OFFSET N2 No internal connection PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2, Texas Instruments Incorporated POST OFFICE BOX DALLAS, TEXAS

2 µa71, µa71y TA SMALL OUTLINE (D) CHIP CARRIER (FK) AVAILABLE OPTIONS CERAMIC DIP (J) PACKAGED DEVICES CERAMIC DIP (JG) PLASTIC DIP (P) TSSOP (PW) FLAT PACK (U) CHIP FORM (Y) C to 7 C µa71cd µa71cp µa71cpw µa71y C to 5 C µa71id µa71ip 55 C to 125 C µa71mfk µa71mj µa71mjg µa71mu The D package is available taped and reeled. Add the suffix R (e.g., µa71cdr). schematic VCC+ IN IN+ OUT OFFSET N1 OFFSET N2 VCC Component Count Transistors 22 Resistors 11 Diode 1 Capacitor 1 2 POST OFFICE BOX DALLAS, TEXAS 75265

3 µa71, µa71y µa71y chip information This chip, when properly assembled, displays characteristics similar to the µa71c. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS () (7) (6) IN + IN OFFSET N1 OFFSET N2 (3) (2) (1) (5) + VCC+ (7) () VCC (6) OUT 5 (5) (1) () CHIP THICKNESS: 15 TYPICAL BONDING PADS: MINIMUM (2) (3) TJmax = 15 C. TOLERAES ARE ±%. 36 ALL DIMENSIONS ARE IN MILS. POST OFFICE BOX DALLAS, TEXAS

4 µa71, µa71y absolute maximum ratings over operating free-air temperature range (unless otherwise noted) µa71c µa71i µa71m UNIT Supply voltage, VCC+ (see Note 1) V Supply voltage, VCC (see Note 1) V Differential input voltage, VID (see Note 2) ±15 ±3 ±3 V Input voltage, VI any input (see Notes 1 and 3) ±15 ±15 ±15 V Voltage between offset null (either OFFSET N1 or OFFSET N2) and VCC ±15 ±.5 ±.5 V Duration of output short circuit (see Note ) unlimited unlimited unlimited Continuous total power dissipation See Dissipation Rating Table Operating free-air temperature range, TA to 7 to 5 55 to 125 C Storage temperature range 65 to to to 15 C Case temperature for 6 seconds FK package 26 C Lead temperature 1,6 mm (1/16 inch) from case for 6 seconds J, JG, or U package 3 C Lead temperature 1,6 mm (1/16 inch) from case for seconds D, P, or PW package C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, unless otherwise noted, are with respect to the midpoint between VCC+ and VCC. 2. Differential voltages are at IN+ with respect to IN. 3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.. The output may be shorted to ground or either power supply. For the µa71m only, the unlimited duration of the short circuit applies at (or below) 125 C case temperature or 75 C free-air temperature. PACKAGE TA 25 C POWER RATING DERATING FACTOR DISSIPATION RATING TABLE DERATE ABOVE TA TA = 7 C POWER RATING TA = 5 C POWER RATING TA = 125 C POWER RATING D 5 mw 5. mw/ C 6 C 6 mw 377 mw N/A FK 5 mw 11. mw/ C 5 C 5 mw 5 mw 275 mw J 5 mw 11. mw/ C 5 C 5 mw 5 mw 275 mw JG 5 mw. mw/ C 9 C 5 mw 5 mw 2 mw P 5 mw N/A N/A 5 mw 5 mw N/A PW 525 mw.2 mw/ C 25 C 336 mw N/A N/A U 5 mw 5. mw/ C 57 C 32 mw 351 mw 135 mw POST OFFICE BOX DALLAS, TEXAS 75265

5 µa71, µa71y electrical characteristics at specified free-air temperature, V CC± = ±15 V (unless otherwise noted) PARAMETER VIO Input offset voltage VO = TEST CONDITIONS µa71c µa71i, µa71m TA MIN TYP MAX MIN TYP MAX 25 C Full range VIO(adj) Offset voltage adjust range VO = 25 C ±15 ±15 mv IIO Input offset current VO = IIB Input bias current VO = VICR VOM AVD 25 C Full range C 5 5 Full range 15 Common-mode input 25 C ±12 ±13 ±12 ±13 voltage range Full range ±12 ±12 RL = kω 25 C ±12 ±1 ±12 ±1 Maximum peak output RL kω Full range ±12 ±12 voltage swing RL = 2 kω 25 C ± ±13 ± ±13 RL 2 kω Full range ± ± Large-signal g differential RL 2 kω 25 C voltage amplification VO = ± V Full range ri Input resistance 25 C MΩ ro Output resistance VO =, See Note 5 25 C Ω Ci Input capacitance 25 C pf CMRR ksvs Common-mode rejection ratio Supply voltage sensitivity ( VIO / VCC) VIC = VICRmin 25 C Full range 7 7 UNIT mv na na V V V/mV 25 C VCC = ±9 Vto±15 V µv/v Full range IOS Short-circuit output current 25 C ±25 ± ±25 ± ma ICC Supply current VO =, No load PD Total power dissipation VO =, No load 25 C Full range C Full range All characteristics are measured under open-loop conditions with zero common-mode input voltage unless otherwise specified. Full range for the µa71c is C to 7 C, the µa71i is C to 5 C, and the µa71m is 55 C to 125 C. NOTE 5: This typical value applies only at frequencies above a few hundred hertz because of the effects of drift and thermal feedback. operating characteristics, V CC± = ±15 V, T A = 25 C PARAMETER TEST CONDITIONS µa71c µa71i, µa71m MIN TYP MAX MIN TYP MAX tr Rise time VI = 2 mv, RL = 2 kω,,.3.3 µs Overshoot factor CL = pf, See Figure 1 5% 5% SR Slew rate at unity gain VI = V, CL = pf, RL = 2 kω, See Figure 1 db ma mw UNIT.5.5 V/µs POST OFFICE BOX DALLAS, TEXAS

6 µa71, µa71y electrical characteristics at specified free-air temperature, V CC± = ±15 V, T A = 25 C (unless otherwise noted) PARAMETER TEST CONDITIONS µa71y MIN TYP MAX VIO Input offset voltage VO = 1 6 mv VIO(adj) Offset voltage adjust range VO = ±15 mv IIO Input offset current VO = 2 2 na IIB Input bias current VO = 5 na VICR Common-mode input voltage range ±12 ±13 V VOM Maximum peak output voltage swing RL = kω ±12 ±1 RL = 2 kω ± ±13 AVD Large-signal differential voltage amplification RL 2 kω 2 2 V/mV ri Input resistance.3 2 MΩ ro Output resistance VO =, See Note 5 75 Ω Ci Input capacitance 1. pf CMRR Common-mode rejection ratio VIC = VICRmin 7 9 db ksvs Supply voltage sensitivity ( VIO / VCC) VCC = ±9 V to ±15 V 3 15 µv/v IOS Short-circuit output current ±25 ± ma ICC Supply current VO =, No load ma PD Total power dissipation VO =, No load 5 5 mw All characteristics are measured under open-loop conditions with zero common-mode voltage unless otherwise specified. NOTE 5: This typical value applies only at frequencies above a few hundred hertz because of the effects of drift and thermal feedback. operating characteristics, V CC ± = ±15 V, T A = 25 C PARAMETER TEST CONDITIONS µa71y MIN TYP MAX tr Rise time VI = 2 mv, RL = 2 kω,,.3 µs Overshoot factor CL = pf, See Figure 1 5% SR Slew rate at unity gain VI = V, CL = pf, RL = 2 kω, See Figure 1 UNIT V UNIT.5 V/µs 6 POST OFFICE BOX DALLAS, TEXAS 75265

7 µa71, µa71y PARAMETER MEASUREMENT INFORMATION VI V INPUT VOLTAGE WAVEFDORM IN + CL = pf OUT RL = 2 kω TEST CIRCUIT Figure 1. Rise Time, Overshoot, and Slew Rate APPLICATION INFORMATION Figure 2 shows a diagram for an input offset voltage null circuit. IN + IN + OUT OFFSET N2 OFFSET N1 kω To VCC Figure 2. Input Offset Voltage Null Circuit POST OFFICE BOX DALLAS, TEXAS

8 µa71, µa71y TYPICAL CHARACTERISTICS Input Offset Current na IO I ÏÏÏÏÏ VCC+ = 15 V ÏÏÏÏÏ VCC = 15 V INPUT OFFSET CURRENT vs FREE-AIR TEMPERATURE Input Bias Current na IB I VCC+ = 15 V ÏÏÏÏÏ VCC = 15 V INPUT BIAS CURRENT vs FREE-AIR TEMPERATURE TA Free-Air Temperature C TA Free-Air Temperature C Figure 3 Figure Maximum Peak Output Voltage V OM V ±1 ±13 ±12 ±11 ± ±9 ± ±7 ±6 ±5 MAXIMUM PEAK OUTPUT VOLTAGE vs LOAD RESISTAE VCC+ = 15 V VCC = 15 V TA = 25 C ± RL Load Resistance kω 7 Figure 5 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX DALLAS, TEXAS 75265

9 µa71, µa71y TYPICAL CHARACTERISTICS V OM Maximum Peak Output Voltage V ±2 ±1 ±16 ±1 ±12 ± ± ±6 ± ±2 MAXIMUM PEAK OUTPUT VOLTAGE vs FREQUEY VCC+ = 15 V VCC = 15 V RL = kω TA = 25 C A VD Open-Loop Signal Differential Voltage Amplification V/mV 2 2 OPEN-LOOP SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION vs SUPPLY VOLTAGE VO = ± V RL = 2 kω TA = 25 C 1k k k 1M f Frequency Hz VCC ± Supply Voltage V Figure 6 Figure 7 A VD Open-Loop Signal Differential Voltage Amplification db OPEN-LOOP LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION vs FREQUEY 1k k k f Frequency Hz VCC+ = 15 V VCC = 15 V VO = ± V RL = 2 kω TA = 25 C 1M M POST OFFICE BOX DALLAS, TEXAS

10 µa71, µa71y TYPICAL CHARACTERISTICS CMRR Common-Mode Rejection Ratio db COMMON-MODE REJECTION RATIO vs FREQUEY k 1M M f Frequency Hz VCC+ = 15 V VCC = 15 V BS = kω TA = 25 C Output Voltage mv V O % 9% OUTPUT VOLTAGE vs ELAPSED TIME tr t Time µs VCC+ = 15 V VCC = 15 V RL = 2 kω CL = pf TA = 25 C Figure Figure 9 Input and Output Voltage V VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE VO VI VCC+ = 15 V VCC = 15 V RL = 2 kω CL = pf TA = 25 C t Time µs Figure POST OFFICE BOX DALLAS, TEXAS 75265

11 PACKAGE OPTION ADDENDUM 12-Jan-26 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty UA71CD ACTIVE SOIC D 75 Green (RoHS & no Sb/Br) UA71CDE ACTIVE SOIC D 75 Green (RoHS & no Sb/Br) UA71CDR ACTIVE SOIC D 25 Green (RoHS & no Sb/Br) UA71CDRE ACTIVE SOIC D 25 Green (RoHS & no Sb/Br) Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU UA71CJG OBSOLETE CDIP JG TBD Call TI Call TI UA71CJG OBSOLETE CDIP JG TBD Call TI Call TI UA71CP ACTIVE PDIP P 5 Pb-Free (RoHS) UA71CPE ACTIVE PDIP P 5 Pb-Free (RoHS) UA71CPSR ACTIVE SO PS 2 Green (RoHS & no Sb/Br) UA71CPSRE ACTIVE SO PS 2 Green (RoHS & no Sb/Br) CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU UA71MFKB OBSOLETE LCCC FK 2 TBD Call TI Call TI UA71MJ OBSOLETE CDIP J 1 TBD Call TI Call TI UA71MJB OBSOLETE CDIP J 1 TBD Call TI Call TI UA71MJG OBSOLETE CDIP JG TBD Call TI Call TI UA71MJGB OBSOLETE CDIP JG TBD Call TI Call TI Level-1-26C-UNLIM Level-1-26C-UNLIM Level-1-26C-UNLIM Level-1-26C-UNLIM N / A for Pkg Type N / A for Pkg Type Level-1-26C-UNLIM Level-1-26C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

12 PACKAGE OPTION ADDENDUM 12-Jan-26 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

13 MECHANICAL DATA MCER1A JANUARY 1995 REVISED JANUARY 1997 JG (R-GDIP-T) CERAMIC DUAL-IN-LINE. (,16).355 (9,) 5.2 (7,11).25 (6,22) 1.65 (1,65).5 (1,1).63 (1,6).15 (,3).2 (,51) MIN.3 (7,7).29 (7,37).2 (5,) MAX Seating Plane.13 (3,3) MIN. (2,5).23 (,5).15 (,3).1 (,36). (,2) 15 7/C /96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 135 GDIP1-T POST OFFICE BOX DALLAS, TEXAS 75265

15 MECHANICAL DATA MLCC6B OCTOBER 1996 FK (S-CQCC-N**) 2 TERMINAL SHOWN LEADLESS CERAMIC CHIP CARRIER NO. OF TERMINALS ** MIN A MAX MIN B MAX (,69).35 (9,9).37 (7,).35 (9,9) A SQ B SQ (11,23).6 (16,26).739 (1,7).93 (23,3) 1.11 (2,99).5 (11,63).66 (16,76).761 (19,32).962 (2,3) (29,59).6 (,31).95 (12,5).95 (12,5).5 (21,6) 1.7 (26,6).5 (11,63).56 (1,22).56 (1,22).5 (21,) 1.63 (27,).2 (,51). (,25). (2,3).6 (1,63).2 (,51). (,25).55 (1,).5 (1,1).5 (1,1).35 (,9).2 (,71).22 (,5).5 (1,27).5 (1,1).35 (,9) 1/ D /96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS- POST OFFICE BOX DALLAS, TEXAS 75265

16 MECHANICAL DATA MPDI1A JANUARY 1995 REVISED JUNE 1999 P (R-PDIP-T) PLASTIC DUAL-IN-LINE. (,6).355 (9,2) 5.26 (6,6).2 (6,) 1.7 (1,7) MAX.2 (,51) MIN.325 (,26).3 (7,62).15 (,3).2 (5,) MAX Gage Plane Seating Plane.125 (3,1) MIN. (,25) NOM.21 (,53).15 (,3). (2,5). (,25) M.3 (,92) MAX 2/D 5/9 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-1 For the latest package information, go to POST OFFICE BOX DALLAS, TEXAS 75265

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GENERAL-PURPOSE OPERATIONAL AMPLIFIERS

GENERAL-PURPOSE OPERATIONAL AMPLIFIERS Short-Circuit Protection Offset-Voltage Null Capability Large Common-Mode and Differential Voltage Ranges No Frequency Compensation Required Low Power Consumption No Latch-Up Designed to Be Interchangeable