LOGARITHMIC AMPLIFIER

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1 LOGARITHMIC AMPLIFIER FEATURES ACCEPTS INPUT VOLTAGES OR CURRENTS OF EITHER POLARITY WIDE INPUT DYNAMIC RANGE 6 Decades of Decades of Voltage VERSATILE Log, Antilog, and Log Ratio Capability DESCRIPTION Packaged in a ceramic double wide DIP, the is the first hybrid logarithmic amplifier that accepts signals of either polarity from current or voltage sources. A special purpose monolithic chip, developed specifically for logarithmic conversions, functions accurately for up to six decades of input current and four decades of input voltage. In addition, a current inverter and a precise internal reference allow pin programming of the as a logarithmic, log ratio, or antilog amplifier. To further increase its versatility and reduce your system cost, the has an uncommitted operational amplifier in its package that can be used as a buffer, inverter, filter, or gain element. The is available with initial accuracies (log conformity) of 0.% and 1.0%, and operates over an ambient temperature range of C to +0 C. With its versatility and high performance, the has many applications in signal compression, transducer linearization, and phototube buffering. Manufacturers of medical euipment, analytical instruments, and process control instrumentation will find the a low cost solution to many signal processing problems. International Airport Industrial Park Mailing Address: PO Box 10 Tucson, AZ 83 Street Address: 630 S. Tucson Blvd. Tucson, AZ 806 Tel: (0) Twx: Cable: BBRCORP Telex: FAX: (0) Immediate Product Info: (800) Burr-Brown Corporation PDS-36F Printed in U.S.A. October, 93 SBFS0

2 SPECIFICATIONS ELECTRICAL Typical Specifications at + C with rated supplies, unless otherwise noted. MODEL KG JG ACCURACY (1), % of FSR Source Input: 1nA to 1mA 0.% max 1% max Voltage Input: 1mV to V 0.% max 1% max INPUT Source Input, Pin +1nA to +1mA Source Input, Pin 1nA to 1mA Reference Input, Pin +1µA to +1mA Absolute Maximum Inputs ±ma or ±Supply Volts OUTPUT Voltage ±V ±ma Impedance Ω FREQUENCY RESPONSE 3dB Small Signal at Input of 0µA 90kHz of µa 0kHz of 1µA khz of 0nA 0Hz of na 80Hz Step Response to within ±1% of Final Value ( = 1µA, A = ) ms STABILITY Scale Factor Drift ( A/ C) ±0.000A/ C Reference Drift ( / C) ±0.001 / C for 1µA ±0.003 / C for 00nA < < 1µA Input Offset Drift ( / C) pa at + C, Doubles Every C Input Offset Voltage Drift ±µv/ C Accuracy vs Supply Variation Reference ±0.001 /V Input Offset Voltage ±300µV/V Input Noise - Input 1pA, rms, Hz to khz Input Noise - Voltage Input µa, rms, Hz to khz UNCOMMITTED OP AMP CHARACTERISTICS Input Offset Voltage mv Input Bias 0nA Input Impedance 1MΩ Large Signal Voltage 8dB Output ma TEMPERATURE RANGE Specification 0 C to +60 C Operating C to +0 C Storage C to +1 C POWER SUPPLY REQUIREMENTS Rated Supply Voltages ±1VDC Supply Voltage Range ±1VDC to ±16VDC Supply Drain at Quiescent, max ±0mA at Full Load, max ±6mA PIN CONFIGURATION Top View EF Output EF Input No Pin Present +I Input (1) Inverter Output (1) No Pin Present Inverter Input No Pin Present Op Amp + Input Op Amp Input Op Amp Output 11 No Pin Present 1 No Pin Present 3 EF Bias Postive Supply 1 Common 0 No Pin Present Adjust Log Output 1 No Pin Present 16 No Pin Present 1 No Pin Present 1 Negative Supply 13 NC NOTE: (1) Pins and are internally connected. PACKAGE INFORMATION PACKAGE DRAWING MODEL PACKAGE NUMBER (1) KG -Pin 0 JG -Pin 0 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. NOTE: (1) Log conformity at C. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

3 TYPICAL PERFORMANCE CURVES At + C with rated supplies, unless otherwise noted. Reference 0µA µa 1µA 0nA na k RELATIONSHIP OF REFERENCE CURRENT, AND EXTERNAL RESISTOR, R 1 I = A log S IR 1 0 0k 1M Resistance (Ω) M 0M Scale Factor A (V) RELATIONSHIP OF SCALE FACTOR A TO GAIN SETTING RESISTOR, R Resistance (kω) = A log LOG RELATIONSHIP OF AND OUTPUT VOLTAGE IN TERMS OF A RELATIONSHIP OF AND OUTPUT VOLTAGE For = 1µA and A = V and V A A Output Voltage Volts I = A log S Input V V Output Voltage A = V A = V = A log Input A V 0.01µA 0.1µA 1µA µa 0µA Range of Adjustment A V 0dB 80dB DISCUSSION OF SPECIFICATIONS ACCURACY The deviation from the ideal output voltage defined as a percent of the full scale output voltage. INPUT/OUTPUT RANGE E S The log relationships of A log and A log are R subject to the constraints specified. The can be operated with inputs lower than those given, but the accuracy will be degraded. FREQUENCY RESPONSE The small-signal freuency response varies considerably with signal level and scaling, so the freuency response is specified under several different operating conditions. STABILITY The use of a monolithic transistor uad and low-drift amps minimizes drift, but some drift remains in the scale-factor, reference current, and input offset. Input offset consists of a bias current plus the op amp input voltage offset divided by the signal source resistance. Also, there is some slight drift in conformity to the log function and in output amplifier offset, but this is generally negligible. THEORY OF OPERATION The is a complete logarithmic amplifier that can be pin-programmed to accept input currents or voltages of either polarity. By making use of the internal current inverter, reference current generator, log ratio element, and uncommitted op amp, you can generate a variety of logarith- 3

4 mic functions, including the log ratio of two signals, the logarithm of an input signal, or the antilog of an input signal. The uniue FET-input current-inverting element removes the polarity limitations present in most conventional log amplifiers. Utilizing the inherent exponential characteristics of transistor functions, the calculates accurate log functions for input currents from 1nA to 1mA, or input voltages from 1mV to V. Carefully matched monolithic uad transistors and temperature sensitive gain elements are used to produce a log amplifier with excellent temperature characteristics. A functional diagram of the circuit is shown in Figure 1. In addition to the basic log amplifier, the contains a separate internal current source, a current inverter, and an uncommitted operational amplifier. The current inverter accurately converts negative input current to a positive current of eual magnitude. The is capable of accurately logging input current over a db range, but to use this full range, good shielding practice must be followed. A current source input is, by definition, a high impedance source and is therefore subject to electrostatic pickup. The input op amps, A 1 and A 3, have FET input stages for low noise and very-low input bias current. The op amp, A 1, will make the collector current of Q 1 eual to the signal input current, and the collector current of Q will be the reference input current. From the semiconductor junction characteristics, the baseto-emitter voltage will be: mkt V BE ln, where: I C = Collector current I L = Reverse saturation current, m, K = Constants T = Absolute temperature mkt So E 1 = 1 mkt l n and E E 1 = ln If the transistors Q 1 and Q are at the same temperature and have matched characteristics, then: mkt E = l n ln E = mkt I L1 ln The output op amp, A, provides a voltage gain of approximately ( + R )/, and the value of (mkt)/ is about 6mV at room temperature. Since resistor varies with temperature to compensate for gain drift, the output voltage,, expressed as a log will be: I C I L I L I L I L Inverter Input Inverter Output A 3 Q 1 0Ω Thermistor E Q A Adjust R Log Output Op Amp Input +I INPUT EF Input A 1 E 1 A 11 9 Op Amp Output Op Amp +Input kω 3 1 EF Output I EF R R Common FIGURE 1. Functional Diagram.

5 = A log, I MAX 6 = = 0 + R 1 where A (6mV), 0Ω 0.3 The external resistor R 1 sets the reference current and resistor R sets the scale-factor A. R 1 and R must be trimmed to the desired values, but the approximate relationships are shown in Typical Performance Curves. The relationship between the input current,, and the output voltage,, in terms of the externally adjusted parameters, and A, is illustrated in Typical Performance Curves. This relationship is, of course, restricted to values of between 1nA and 1mA and output voltages of less than ±V. CHOOSING THPTIMUM SCALE FACTOR AND REFERENCE CURRENT To minimize the effects of output offset and noise, it is usually best to use the full ±V output range. Once an output range of ±V has been chosen, then A and can be determined from the Min/Max of the input current,. = A log, where I MIN < < I MAX The output range of ±V for an input range of I MIN to I MAX means that: + = A log and = A log Adding these two euations together log I MAX + I MIN The value for A can be found from: I MIN = 0, or = I MAX I MIN I MAX = A log I MAX I MIN In terms of the input current range for, the values for and A that will provide a full ±V output swing are: = I MAX I MIN and A = log EXAMPLE Assume that I MIN is +na and I MAX is +0µA. This is an 80dB range. I MAX I MAX I MAX log = ; So, A = For an of 1µA and A of, = log CONNECTION DIAGRAMS Transfer function is = A log 1µA where is a positive input current and is the resistor-programmed internal reference current (see Figure ). Reference R (1) 3 (1) FIGURE. Transfer Function When is Positive. 1 Reference.. Apply =, adjust R 1 such that = Apply = I MAX, adjust R for the proper output voltage.. Repeat steps and 3 if necessary.. Ignore this step if MIN na. Otherwise, apply I = 1 1nA, make = 1kMΩ and adjust R for the proper output voltage. For, a single resistor is recommended. A voltage divider network is difficult to use due to amplifier offset voltage. Transfer function is = A log where is a negative input current and is the resistor-programmed internal reference current (see Figure 3). 1 1 NOTE: (1) Needed only if < na. R = I MAX I MIN = ( ) ( 8 ) = 6, or 1µA.

6 Reference R (1) 3 (1) FIGURE 3. Transfer Function When is Negative. Reference.. Apply = adjust R 1 such that = Apply = I MAX, adjust R for the proper output voltage. Repeat steps and 3 if necessary.. Ignore this step if MIN na. Otherwise, apply = 1nA, make = 1kMΩ and adjust R for the proper output voltage. For, a single resistor is recommended. A voltage divider network is difficult to use due to amplifier offset voltage. Transfer function is = A log, where E 1 is a R positive input voltage and is the resistor-programmed internal reference current (see Figure ). Reference R 1 3 NOTE: (1) Needed only if < na. E R. Apply E 1 = E MIN, adjust for the proper output.. Repeat steps through if necessary. E 1 Transfer function is = A log, where E 1 is a R negative input voltage and is the resistor-programmed internal reference current (see Figure ). Reference E 1 R 1 3 R ±1% FIGURE. Transfer Function When E 1 is Negative. 0MΩ Reference.. Apply E 1 = (), adjust R 1 such that = Apply E 1 = E MAX, adjust R for the proper output voltage.. Apply E 1 = E MIN, adjust for the proper output.. Repeat steps through if necessary. Transfer function is = A log with and I I negative; 1nA, I 1µA (see Figure 6) R E 1 ±1% 0MΩ 1 R FIGURE. Transfer Function When E 1 is Positive. Reference.. Apply E 1 = (), adjust R 1 such that = Apply E 1 = E MAX, adjust R for the proper output voltage. R (1) (1) R () I R 6 () NOTES:(1) Needed only if < na. () R = R 6 ±1% FIGURE 6. Transfer Function When and I are Negative. 6

7 Reference.. No further adjustment is necessary if MIN na, otherwise connect the and R network, with R = and = 9 Ω. Adjust R for proper output voltage after adjusting gain errors. Since the voltage at pin is in the range of ±mv, it is not practical to use a T-network to replace. range of ±mv, it is not practical to use a T-network to replace. I 1 1 Transfer function is = A log with negative, I positive; 1nA, I 1µA (see Figure ). I R (1) (1) NOTE: (1) Needed only if < na. 1 1 FIGURE 8. Transfer Function When and I is Positive. I (1) NOTE: (1) Needed only if < na. ANTILOG OPERATION The can also perform the antilog function. The output is connected through a resistor, R O, into the current input, pin. The input signal is connected through a gain resistor to pin as shown in Figure 9. R (1) FIGURE. Transfer Function When is Negative, I is Positive. Reference.. No further adjustment is necessary if MIN na, otherwise connect the and R network, with R = and = 9 Ω. Adjust R for proper output voltage after adjusting gain errors. Since the voltage at pin is in the range of ±mv, it is not practical to use a T-network to replace.. I Transfer function is = A log 1 with and I positive; 1nA, I 1µA (see Figure 8). Reference.. No further adjustment is necessary if MIN na, otherwise connect the and R network, with R = and = 9 Ω. Adjust R for proper output voltage after adjusting gain errors. Since the voltage at pin is in the I Ref. E S R R 1 3 Insert 0.01µF between Pin and Pin if the unit oscillates. FIGURE 9. Antilog Operation R O 0MΩ Offset Adjust These connections form an implicit loop for computing the antilog function. From the block diagram of Figure 1, the voltage at the inverting input of the output amplifier A must eual E, so E E S, 0Ω + R Since the output is connected through R O to pin, the current will eual /R O and E will be mkt E = ln R O

8 Combining expressions for E gives the relationship: + R E S = mkt l n R O E S = log A R O where: + R 1 A (6mV) 0.3 = R O Antilog E S A Setting R O and will set the scale factor. For example, an R O of 1MΩ and of 1µA will give a scale factor of unity and = Antilog E S A 8

9 PACKAGPTION ADDENDUM 3-Oct-003 PACKAGING INFORMATION ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY JG NRND CDIP JNA 1 KG NRND CDIP JNA 1 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

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4423 Typical Circuit A2 A V

4423 Typical Circuit A2 A V SBFS020A JANUARY 1978 REVISED JUNE 2004 FEATURES Sine and Cosine Outputs Resistor-Programmable Frequency Wide Frequency Range: 0.002Hz to 20kHz Low Distortion: 0.2% max up to 5kHz Easy Adjustments Small