High Voltage FET-Input OPERATIONAL AMPLIFIER

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1 For most current data sheet and other product information, visit High Voltage FET-Input OPERATIONAL AMPLIFIER FEATURES WIDE-POWER SUPPLY RANGE: ±V to ±V HIGH SLEW RATE: V/µs LOW INPUT BIAS CURRENT: pa STANDARD-PINOUT TO-99, DIP, AND SURFACE-MOUNT PACKAGES DESCRIPTION APPLICATIONS TEST EQUIPMENT HIGH-VOLTAGE REGULATORS POWER AMPLIFIERS DATA ACQUISITION SIGNAL CONDITIONING AUDIO PIEZO DRIVERS The is a monolithic operational amplifier capable of operation from power supplies up to ±V and output currents of ma. It is useful in a wide variety of applications requiring high output voltage or large common-mode voltage swings. The s high slew rate provides wide powerbandwidth response, which is often required for highvoltage applications. FET input circuitry allows the use of high-impedance feedback networks, thus minimizing their output loading effects. Laser trimming of the input circuitry yields low input offset voltage and drift. The is available in standard pin-out TO-99, DIP-8, and SO-8 surface-mount packages. It is fully specified from C to +8 C and operates from C to + C. A SPICE macromodel is available for design analysis. NC Offset Trim 8 7 V+ Offset Trim 8 NC In 6 Output In 7 V+ +In 3 Offset Trim +In V 3 6 Output Offset Trim V 8-Pin DIP, SO-8 Case is connected to V TO-99 International Airport Industrial Park Mailing Address: PO Box, Tucson, AZ 873 Street Address: 673 S. Tucson Blvd., Tucson, AZ 876 Tel: () 76- Twx: 9-9- Internet: Cable: BBRCORP Telex: FAX: () 889- Immediate Product Info: (8) 8-63 SBOS6 987 Burr-Brown Corporation PDS-7H Printed in U.S.A. March,

2 SPECIFICATIONS At T A = + C, V S = ±V, and R L = kω, unless otherwise specified. Boldface limits apply over the specified temperature range, T A = C to +8 C. V S = ±V. BM AP, AU PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS OFFSET VOLTAGE Input Offset Voltage V OS V CM =, I O = ± ±3 ±. ± mv vs Temperature V OS /dt T A = C to +8 C ± µv/ C vs Power Supply PSRR V S = ±V to ±V µv/v INPUT BIAS CURRENT () Input Bias Current I B V CM = V ± ± ± pa Over Specified Temperature Range ± ± na Input Offset Current I OS V CM = V ± ± ± pa Over Specified Temperature Range ± ± na NOISE Input Voltage Noise Density, f = khz e n nv/ Hz Current Noise Density, f = khz i n 6 fa/ Hz INPUT VOLTAGE RANGE Common-Mode Voltage Range V CM V S = ±V (V )+ (V+) V Common-Mode Rejection CMRR V CM = 3V to +3V 8 9 db Over Specified Temperature Range 8 db INPUT IMPEDANCE Differential 3 Ω pf Common-Mode 3 Ω pf OPEN-LOOP GAIN, DC Open-Loop Voltage Gain A OL V O = 3V to +3V db Over Specified Temperature Range 97 db FREQUENCY RESPONSE Gain Bandwidth Product GBW MHz Slew Rate SR V O = 7Vp-p V/µs Full Power Bandwidth V O = 7Vp-p 3 7 khz Rise Time V O = ±mv ns Overshoot G = +, Z L = kω pf 3 % Total Harmonic Distortion + Noise THD+N f = khz, V O = 3.Vrms, G =. % f = khz, V O = Vrms, G =.8 % OUTPUT Voltage Output V O (V )+ (V+) V Over Specified Temperature Range (V )+ (V+) V Current Output I O V O = ±8V ± ma Output Resistance, Open Loop R O dc Ω Short Circuit Current I SC ±6 ma Capacitive Load Drive C LOAD See Typical Curve () POWER SUPPLY Specified Operating Range V S ± V Operating Voltage Range ± ± V Quiescent Current I Q I O = ±. ±.7 ma TEMPERATURE RANGE Specification Range +8 C Operating Range + C Storage Range C Thermal Resistance θ JA TO-99 C/W 8-Pin DIP C/W SO-8 Surface-Mount C/W Specifications same as BM. NOTE: () High-speed test at T J = + C. () See Small-Signal Overshoot vs Load Capacitance in the Typical Performance Curves section. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

3 ABSOLUTE MAXIMUM RATINGS () Power Supply... ±V Differential Input Voltage... ±8V Input Voltage Range... ±V S 3V Storage Temperature Range: M... 6 C to + C P, U... C to + C Operating Temperature Range... C to + C Lead Temperature (soldering, s) C Output Short-Circuit to Ground (T J < + C)... Continuous Junction Temperature: M... 7 C P,U... C NOTE: () Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PACKAGE SPECIFIED DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER () MEDIA AP 8-Pin DIP 6 C to +8 C AP AP Rails AU SO-8 Surface-Mount 8 C to +8 C AU AU Rails AU " " " " AU/K Tape and Reel BM 8-Pin TO-99 C to +8 C BM BM Rails NOTE: () Products followed by a slash (/) are only available in Tape and Reel in the quantities indicated (e.g., /K indicates devices per reel). Ordering pieces of AU/K will get a single piece Tape and Reel. 3

4 TYPICAL PERFORMANCE CURVES At T A = + C, V S = ±V, unless otherwise noted. OPEN-LOOP GAIN AND PHASE vs FREQUENCY OPEN-LOOP GAIN AND SUPPLY CURRENT vs SUPPLY VOLTAGE. Voltage Gain (db) 8 6 θ 9 3 Phase (Degrees) Voltage Gain (db) A VOL I Q. 3. Supply Current (ma) Gain 8 k k k M M Frequency (Hz) Supply Voltage (±V S ).6 GAIN BANDWIDTH AND SLEW RATE vs TEMPERATURE 6. GAIN BANDWIDTH AND SLEW RATE vs SUPPLY VOLTAGE 9 Gain Bandwidth (MHz) GBW SR 3 Slew Rate (V/µs) Gain Bandwidth (MHz)..8 GBW SR 7 Slew Rate (V/µs). 7 7 Ambient Temperature ( C) Supply Voltage (±V S ) na INPUT BIAS CURRENT vs TEMPERATURE INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE na 3 Input Bias Current na pa pa pa Bias Current (pa) 3 I B +I B.pA.pA 7 7 Temperature ( C) 3 3 Common-Mode Voltage (V)

5 TYPICAL PERFORMANCE CURVES (Cont.) At T A = + C, V S = ±V, unless otherwise noted. POWER SUPPLY REJECTION vs FREQUENCY COMMON-MODE REJECTION vs FREQUENCY Power Supply Rejection (db) 8 6 PSRR +PSRR Common-Mode Rejection (db) k k k M M M Frequency (Hz) k k k M M Frequency (Hz) OPEN-LOOP GAIN vs TEMPERATURE 3 POWER SUPPLY REJECTION AND COMMON-MODE REJECTION vs TEMPERATURE Voltage Gain (db) PSRR, CMRR (db) 9 PSRR CMRR Ambient Temperature ( C) Ambient Temperature ( C) INPUT VOLTAGE NOISE SPECTRAL DENSITY. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY Voltage Noise (nv/ Hz) THD+Noise (%)... V O = 3.Vrms G = V O = Vrms V O = 3.Vrms G = V O = Vrms k k k Frequency (Hz). k k k Frequency (Hz)

6 TYPICAL PERFORMANCE CURVES (Cont.) At T A = + C, V S = ±V, unless otherwise noted. Output Voltage Swing (V) (V+) (V+) (V+) (V+) 6 (V+) 8 (V+) (V ) + (V ) +8 (V ) +6 (V ) + (V ) + (V ) OUTPUT VOLTAGE SWING vs OUTPUT CURRENT Sourcing Current Sinking Current ± ± ± ± ± ±3 Output Current (ma) Output Voltage Swing (V) OUTPUT VOLTAGE SWING vs TEMPERATURE (V+) (V+) Positive Swing (V+) (V+) 3 (V+) (V ) + (V ) +3 Negative Swing (V ) + (V ) + (V ) 7 7 Temperature ( C) SUPPLY CURRENT vs TEMPERATURE 3 OUTPUT CURRENT vs TEMPERATURE Supply Current (ma) 3 Output Current (ma) 3 Short-Circuit Current Output Current V O = ±3V 7 7 Ambient Temperature ( C) 7 Temperature ( C) Output Voltage (Vp-p) MAXIMUM OUTPUT VOLTAGE SWING vs FREQUENCY Maximum output without slew-rate induced distortion. k k k M Frequency (Hz) Dissipation (W) MAXIMUM POWER DISSIPATION vs TEMPERATURE T J (max) TO-99: C DIP, SO: C TO-99 SO-8 No Heat Sink Plastic DIP 7 Temperature ( C) 6

7 TYPICAL PERFORMANCE CURVES (Cont.) At T A = + C, V S = ±V, unless otherwise noted. Percent of Amplifiers (%) OFFSET VOLTAGE PRODUCTION DISTRIBUTION Typical production distribution of packaged units. Percent of Amplifiers (%) OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION Typical production distribution of packaged units Offset Voltage (mv) Offset Voltage Drift (µv/ C) SMALL-SIGNAL STEP RESPONSE G =, C L = pf LARGE-SIGNAL STEP RESPONSE G =, C L = pf mv/div V/div ns/div.µs/div 6 SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE Overshoot (%) 3 G = G = + G = G = pf pf nf nf Load Capacitance 7

8 APPLICATION INFORMATION Figure shows the connected as a basic noninverting amplifier. The can be used in virtually any op amp configuration. Power supply terminals should be bypassed with.µf capacitors, or greater, near the power supply pins. Be sure that the capacitors are appropriately rated for the power supply voltage used. V+ 7 Use offset adjust pins only to null offset voltage of op amp see text. V+ 3 () V 6 mv Typical Trim Range NOTE: () kω to MΩ Trim Potentiometer (kω recommended)..µf G = + R R FIGURE. Offset Voltage Trim. V IN.µF V FIGURE. Offset Voltage Trim. POWER SUPPLIES The may be operated from power supplies up to ±V or a total of 9V with excellent performance. Most behavior remains unchanged throughout the full operating voltage range. Parameters which vary significantly with operating voltage are shown in the typical performance curves. Some applications do not require equal positive and negative output voltage swing. Power supply voltages do not need to be equal. The can operate with as little as V between the supplies and with up to 9V between the supplies. For example, the positive supply could be set to 8V with the negative supply at V, or vice-versa. OFFSET VOLTAGE TRIM The provides offset voltage trim connections on pins and. Offset voltage can be adjusted by connecting a potentiometer as shown in Figure. This adjustment should be used only to null the offset of the op amp, not to adjust system offset or offset produced by the signal source. Nulling system offset could degrade the offset voltage drift behavior of the op amp. While it is not possible to predict the exact change in drift, the effect is usually small. SAFE OPERATING AREA Stress on the output transistors is determined both by the output current and by the output voltage across the conducting output transistors, V S V O. The power dissipated by the Z L V O output transistor is equal to the product of the output current and the voltage across the conducting transistor, V S V O. The Safe Operating Area (SOA curve, Figures 3,, and ) shows the permissible range of voltage and current. The curves shown represent devices soldered to a circuit board with no heat sink. Increasing printed circuit trace area or the use of a heat sink (TO-99 package) can significantly reduce thermal resistance (θ), resulting in increased output current for a given output voltage (see Heat Sink text). The safe output current decreases as V S V O increases. Output short-circuits are a very demanding case for SOA. A short-circuit to ground forces the full power supply voltage (V+ or V ) across the conducting transistor and produces a typical output current of ma. With ±V power supplies, this creates an internal dissipation of W. This exceeds the maximum rating and is not recommended. If operation in this region is unavoidable, a heat sink is required. For further insight on SOA, consult Application Bulletin AB-39. Output Current (ma) SAFE OPERATING AREA T A = C T A = 8 C T A = C T A + ( V S V O ) I O θ JA T J (max) θja = C/W T J (max) = C. V S V O (V) FIGURE 3. 8-Pin DIP Safe Operating Area. 8

9 Output Current (ma) Output Current (ma) T A + ( V S V O ) I O θ JA T J (max) θja = C/W T J (max) = C. V S V O (V) T A = C SAFE OPERATING AREA FIGURE. SO-8 Safe Operating Area. SAFE OPERATING AREA T A = C T A = 8 C T A = 8 C T A = C T A = C T A + ( V S V O ) I O θ JA T J (max) θja = C/W (No Heat Sink*) T J (max) = C *Simple clip-on heatsinks can. reduce θ by as much as C/W. V S V O (V) FIGURE. TO-99 Safe Operating Area. POWER DISSIPATION Power dissipation depends on power supply, signal, and load conditions. For dc signals, power dissipation is equal to the product of the output current times the voltage across the conducting output transistor, P D = I L (V S V O ). Power dissipation can be minimized by using the lowest possible power supply voltage necessary to assure the required output voltage swing. For resistive loads, the maximum power dissipation occurs at a dc output voltage of one-half the power supply voltage. Dissipation with ac signals is lower. Application Bulletin AB-39 explains how to calculate or measure dissipation with unusual loads or signals. The can supply output currents of ma and larger. This would present no problem for a standard op amp operating from ±V supplies. With high supply voltages, however, internal power dissipation of the op amp can be quite large. Operation from a single power supply (or unbalanced power supplies) can produce even larger power dissipation since a large voltage is impressed across the conducting output transistor. Applications with large power dissipation may require a heat sink. HEAT SINKING Power dissipated in the will cause the junction temperature to rise. For reliable operation junction temperature should be limited to C, maximum ( C for TO-99 package). Some applications will require a heat sink to assure that the maximum operating junction temperature is not exceeded. In addition, the junction temperature should be kept as low as possible for increased reliability. Junction temperature can be determined according to the following equation: T J = T A + P D θ JA Package thermal resistance, θ JA, is affected by mounting techniques and environments. Poor air circulation and use of sockets can significantly increase thermal resistance. Best thermal performance is achieved by soldering the op amp into a circuit board with wide printed circuit traces to allow greater conduction through the op amp leads. Simple clip-on heat sinks (such as Thermalloy 7) can reduce the thermal resistance of the TO-99 metal package by as much as C/W. For additional information on determining heat sink requirements, consult Applications Bulletin AB-38. CAPACITIVE LOADS The dynamic characteristics of the have been optimized for commonly encountered gains, loads, and operating conditions. The combination of low closed-loop gain and capacitive load will decrease the phase margin and may lead to gain peaking or oscillations. Figure 6 shows a circuit which preserves phase margin with capacitive load. The circuit does not suffer a voltage drop due to load current, however, input impedance is reduced at high frequencies. Consult Application Bulletin AB-8 for details of analysis techniques and application circuits. V IN kω R C Ω C C.µF R kω R R C = C L X ( + R / ) C C = C L X 3 R C R G = + V O C L pf NOTE: Design equations and component values are approximate. User adjustment is required for optimum performance. FIGURE 6. Driving Large Capacitive Loads. 9

10 INCREASING OUTPUT CURRENT In those applications where the ma of output current is not sufficient to drive the required load, output current can be increased by connecting two or more s in parallel as shown in Figure 7. Amplifier A is the master amplifier and may be configured in virtually an op amp circuit. Amplifier A, the slave, is configured as a unity gain buffer. Alternatively, external output transistors can be used to boost output current. The circuit in Figure 8 is capable of supplying output currents up to A. INPUT PROTECTION The inputs of conventional FET-input op amps should be protected against destructive currents that can flow when input FET gate-to-substrate isolation diodes are forwardbiased. This can occur if the input voltage exceeds the power supplies or there is an input voltage with V S = V. Protection is easily accomplished with a resistor in series with the input. Care should be taken because the resistance in series with the input capacitance may affect stability. Many input signals are inherently current-limited, therefore, a limiting resistor may not be required. V IN R MASTER SLAVE R S () Ω R S () Ω NOTE: () R S resistors minimize the circulating current that will always flow between the two devices due to V OS errors. FIGURE 7. Parallel Amplifiers Increase Output Current Capability. R L R +V TIP9C C F R 3 () Ω R.Ω V O V IN R.Ω LOAD TIP3C V NOTE: () Provides current limit for and allows the amplifier to drive the load when the output is between.7v and.7v. FIGURE 8. External Output Transistors Boost Output Current up to Amp.

11 TYPICAL APPLICATIONS kω R kω V +V +6V.µF V R 3 kω I L = [(V V )/R ] (R / ) = (V V )/kω V Compliance Voltage Range = ±3V R 9.9kΩ I L R Ω Load DAC8-CBI-I Protects DAC During Slewing -ma kω V.µF V O = to +V at ma NOTE: = R 3 and R = R + R FIGURE 9. Voltage-to-Current Converter. FIGURE. Programmable Voltage Source. kω R 9kΩ R 3 kω +V R kω +V 6V SLAVE V IN ±V MASTER Piezo () Crystal V V NOTE: () For transducers with large capacitance the stabilization technique described in Figure 6 may be necessary. Be certain that the Master amplifier is stable before stabilizing the Slave amplifier. FIGURE. Bridge Circuit Doubles Voltage for Piezo Crystals.

12 PACKAGE OPTION ADDENDUM 8-Nov- PACKAGING INFORMATION Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan () Lead/Ball Finish MSL Peak Temp (3) AP ACTIVE PDIP P 8 TBD Call TI Level-NA-NA-NA AU ACTIVE SOIC D 8 Pb-Free (RoHS) AU/K ACTIVE SOIC D 8 Pb-Free (RoHS) BM NRND TO-99 LMC 8 Green (RoHS & no Sb/Br) CU NIPDAU CU NIPDAU Call TI Level-3-6C-68 HR Level-3-6C-68 HR Level-NC-NC-NC () The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. () Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed.% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed.% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page

13 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio Data Converters dataconverter.ti.com Automotive DSP dsp.ti.com Broadband Interface interface.ti.com Digital Control Logic logic.ti.com Military Power Mgmt power.ti.com Optical Networking Microcontrollers microcontroller.ti.com Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box 633 Dallas, Texas 76 Copyright, Texas Instruments Incorporated

High-Speed FET-INPUT OPERATIONAL AMPLIFIERS

OPA32 OPA32 OPA232 OPA232 OPA32 OPA32 OPA32 OPA232 OPA32 SBOS5A JANUARY 995 REVISED JUNE 2 High-Speed FET-INPUT OPERATIONAL AMPLIFIERS FEATURES FET INPUT: I B = 5pA max OPA32 WIDE BANDWIDTH: 8MHz Offset