Programmable Gain AMPLIFIER

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PGA Programmable Gain AMPLIFIER FEATURES DIGITALLY PROGRAMABLE GAINS: G=,, V/V CMOS/TTL-COMPATIBLE INPUTS LOW GAIN ERROR: ±.5% max, G= LOW OFFSET VOLTAGE DRIFT: µv/ C LOW QUIESCENT CURRENT:.

1 PGA Programmable Gain AMPLIFIER FEATURES DIGITALLY PROGRAMABLE GAINS: G=,, V/V CMOS/TTL-COMPATIBLE INPUTS LOW GAIN ERROR: ±.5% max, G= LOW OFFSET VOLTAGE DRIFT: µv/ C LOW QUIESCENT CURRENT:.mA LOW COST -PIN PLASTIC DIP, SO- PACKAGES APPLICATIONS DATA ACQUISITION SYSTEMS GENERAL PURPOSE ANALOG BOARDS MEDICAL INSTRUMENTATION DESCRIPTION The PGA is a programmable-gain amplifier for general purpose applications. Gains of,, or are digitally selected by two CMOS/TTL-compatible inputs. The PGA is ideal for systems that must handle wide dynamic range signals. The PGA s high speed circuitry provides fast settling time, even at G= (µs to.%). Bandwidth is 5kHz at G=, yet quiescent current is only.ma. It operates from ±.5V to ±V power supplies. The PGA is available in -pin plastic DIP and SO- surface-mount packages, specified for the C to +5 C temperature range. V+ V PGA = G GAIN A A International Airport Industrial Park Mailing Address: PO Box Tucson, AZ 5 Street Address: S. Tucson Blvd. Tucson, AZ 5 Tel: (5) - Twx: Cable: BBRCORP Telex: -9 FAX: (5) 9-5 Immediate Product Info: () 5- PGA 99 Burr-Brown Corporation PDS-B Printed in U.S.A. November, 99

2 SPECIFICATIONS ELECTRICAL T A = +5 C, V S = ±5V, R L = kω unless otherwise specified. PGAP, U PARAMETER CONDITIONS MIN TYP MAX UNITS INPUT Offset Voltage, RTI G = T A = +5 C ± ±5 µv G = ± ±5 µv G = ± ±5 µv vs Temperature T A = T MIN to T MAX G = ±5 µv/ C G = ± µv/ C G = ± µv/ C vs Power Supply V S = ±.5V to ±V G = µv/v G = 5 µv/v G = 5 µv/v Impedance Ω pf INPUT BIAS CURRENT Initial Bias Current ±5 ±5 na vs Temperature ± pa/ C NOISE VOLTAGE, RTI G =, R S = Ω f = Hz nv/ Hz f = Hz nv/ Hz f = khz nv/ Hz f B =.Hz to Hz. µvp-p NOISE CURRENT f = Hz. pa/ Hz f = khz. pa/ Hz f B =.Hz to Hz pap-p GAIN Gain Error G = ±.5 ±. % G = ±. ±.5 % G = ±. ±. % Gain vs Temperature G = ± ppm/ C G = ± ppm/ C G = ± ppm/ C Nonlinearity G = ±. ±. % of FSR G = ±. ±.5 % of FSR G = ±. ±. % of FSR OUTPUT Voltage, Positive (V+).5 (V+).5 V Negative (V ) +.5 (V ) +.5 V Load Capacitance, max pf Short-Circuit Current ±5 ma FREQUEY RESPONSE Bandwidth, db G =.5 MHz G = 5 khz G = 5 khz Slew Rate = ±V 9 V/µs Settling Time,.% G = µs G =. µs G =.5 µs Settling Time,.% G =.5 µs G =.5 µs G = µs Overload Recovery 5% Overdrive.5 µs DIGITAL LOGIC INPUTS Digital Low Voltage 5.. V Digital Low or High Current µa Digital High Voltage V+ V PGA

3 SPECIFICATIONS (CONT) ELECTRICAL T A = +5 C, V S = ±5V, R L = kω unless otherwise specified. PGAP, U PARAMETER CONDITIONS MIN TYP MAX UNITS POWER SUPPLY Voltage Range ±.5 ±5 ± V Current = V ±. ±.5 ma TEMPERATURE RANGE Specification +5 C Operating +5 C θ JA : P or U Package C/W PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Top View A A Ground V+ V DIP/SO- Supply Voltage... ±V Analog Input Voltage Range... V to V+ Logic Input Voltage Range... V to V+ Output Short Circuit (to ground)... Continuous Operating Temperature... C to +5 C Storage Temperature... C to +5 C Junction Temperature C Lead Temperature (soldering,s)... + C 5 PACKAGE INFORMATION ORDERING INFORMATION MODEL PACKAGE TEMPERATURE RANGE PGAP -Pin Plastic DIP C to +5 C PGAU SO- Surface-Mount C to +5 C PACKAGE DRAWING MODEL PACKAGE NUMBER () PGAP -Pin Plastic DIP PGAU SO- Surface-Mount NOTE: () For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. ELECTROSTATIC DISCHARGE SENSITIVITY Any integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. PRICES MODEL PGAP $.5 $.9 $.9 PGAU PGAD Contact Factory The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. PGA

DICE INFORMATION C PAD FUTION A A A, B, C () Ground A, B, C () V V+ : No Connection NOTES: () Connect all three indicated pads. () Connect all three indicated pads. Substrate Bias: Internally connected to V power supply.

4 DICE INFORMATION C PAD FUTION A A A, B, C () Ground A, B, C () V V+ : No Connection NOTES: () Connect all three indicated pads. () Connect all three indicated pads. Substrate Bias: Internally connected to V power supply. A B C A B MECHANICAL INFORMATION MILS (.") MILLIMETERS PGA DIE TOPOGRAPHY Die Size 9 x 5 ±5.5 x. ±. Die Thickness ±.5 ±. Min. Pad Size x. x. Backing Gold TYPICAL PERFORMAE CURVES T A = +5 C, V S = ±5V unless otherwise noted. 5 VOLTAGE GAIN vs FREQUEY POWER SUPPLY REJECTION vs FREQUEY Voltage Gain (db) G= G= G= Power Supply Rejection (db) G= G= G= k k M M Frequency (Hz) k k k M Frequency (Hz) PGA

5 TYPICAL PERFORMAE CURVES (CONT) T A = +5 C, V S = ±5V unless otherwise noted. INPUT VOLTAGE NOISE vs FREQUEY INPUT CURRENT NOISE vs FREQUEY Voltage Noise (nv/ Hz) G= G= G= Bandwidth Limited Current Noise (pa/ Hz) All Gains k k k M Frequency (Hz). k k k M Frequency (Hz) QUIESCENT CURRENT vs TEMPERATURE SMALL SIGNAL RESPONSE G= Quiescent Current (ma) 5mV/div G= G= Temperature ( C) µs/div G= LARGE SIGNAL RESPONSE G= G= 5V/div µs/div 5 PGA

6 APPLICATION INFORMATION Figure shows the basic connections required for operation of the PGA. Applications with noisy or high impedance power supplies may require decoupling capacitors close to the device pins as shown. Some applications select gain of the PGA with switches or jumpers. Figure shows pull-up resistors connected to assure a noise-free logic when the switch or jumper is off or open. Fixed-gain applications can connect the logic inputs directly to V+ or ground (or other valid logic level) without a series resistor..µf V+ +5V V 5V.µF V+ V PGA A A = G V+ PGA A A kω kω S S GAIN S S Closed Closed Closed Open Open Closed Not Valid Open Open GAIN A A Not Valid NOTE: () Low impedance ground connection required for good gain accuracy see text. FIGURE. Basic Connections. The input and output are referred to the ground terminal, pin. This must be a low-impedance connection to assure good gain accuracy. A resistance of.ω in series with the ground pin will cause the gain in G= to decrease by approximately.%. DIGITAL INPUTS The digital inputs, A and A, select the gain according to the logic table in Figure. The digital inputs interface directly to common CMOS and TTL logic components. The logic inputs are referenced to the ground terminal, pin. The logic table in Figure shows that logic on both A and A is invalid. This logic code will not cause damage, but the amplifier output will not be predictable while this code is selected. The output will recover when a valid code is selected. The digital inputs are not latched, so a change in logic inputs immediately selects a new gain. Switching time of the logic is approximately.5µs. The time to respond to gain change is equal to the switching time plus the time it takes the amplifier to settle to a new output voltage in the newly selected gain (see settling time specifications). Many applications use an external logic latch to access gain control signals from a high speed data bus. Using an external latch isolates the high speed digital bus from sensitive analog circuitry. Locate the latch circuitry as far as practical from analog circuitry to avoid coupling digital noise into the analog circuitry. PGA Logic : ( 5.) V.V Logic : V V (V+) Logic voltages referred to pin. FIGURE. Switch or Jumper-Selected Gains. OFFSET TRIMMING Offset voltage is laser-trimmed to typically less than µv (referred to input) in all three gains. The input-referred offset voltage can be different for each gain. +5V 5V PGA = G ( V TRIM ) A A V TRIM () Logic threshold voltage is altered by V TRIM. OK for V TRIM mv. OPA ±5mV Trim Range kω Ω NOTE: () Op amp buffer is required to preserve good gain accuracy see text. FIGURE. Offset Voltage Trim Circuit. +5V 5V 5kΩ Figure shows a circuit used to trim the offset voltage of the PGA. An op amp buffers the trim voltage to provide a low impedance at the ground terminal. This is required to maintain accurate gain. Remember that the logic inputs, A and A, are referenced to this ground connection, so the logic threshold voltage will be affected by the trim voltage. This is insignificant if the offset adjustment is used only to trim offset voltage. If a large offset is used (greater than.v), be sure that the logic input signals provide valid logic levels when referred to the voltage at the ground terminal, pin.

7 + PGA5 True instrumentation amplifier input. GAIN V + V V+ V G =,,, G =,, PGA A A G = G G Accepts inputs to ±V. kω D.kΩ D +5V 5V PGA A A A A FIGURE 5. Wide Input Voltage Range Amplifer. G =.,, D, D ; IN FIGURE. Programmable Gain Instrumentation Amplifier. MODEL INA INA5 INA INA INA INA INA CHARACTERISTICS Low Noise, nv/ Hz IA G = Difference Amp G = Difference Amp Resistor-Programmed Gain, Precision ±V C-M Input Range Difference Amp FET Input, High Speed IA Precision, G = IA + G G =,, INA PGA G = G G A A FIGURE. Instrumentation Amplifier with Programmable Gain Output Amp. PGA

8 PACKAGE DRAWINGS PGA

High Speed FET-Input INSTRUMENTATION AMPLIFIER

High Speed FET-Input INSTRUMENTATION AMPLIFIER FEATURES FET INPUT: I B = 2pA max HIGH SPEED: T S = 4µs (G =,.%) LOW OFFSET VOLTAGE: µv max LOW OFFSET VOLTAGE DRIFT: µv/ C max HIGH COMMON-MODE REJECTION: