High Speed FET-INPUT OPERATIONAL AMPLIFIERS
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1 OPA OPA OPA OPA OPA OPA OPA OPA OPA High Speed FET-INPUT OPERATIONAL AMPLIFIERS FEATURES FET INPUT: I B = 5pA max WIDE BANDWIDTH: MHz HIGH SLEW RATE: V/µs LOW NOISE: nv/ Hz (khz) LOW DISTORTION:.% HIGH OPEN-LOOP GAIN: db (Ω load) Offset Trim In +In V OPA 5 Offset Trim V+ Output NC WIDE SUPPLY RANGE: ±.5 to ±V -Pin DIP, SO- LOW OFFSET VOLTAGE: 5µV max SINGLE, DUAL, AND QUAD VERSIONS DESCRIPTION OPA The OPA series of FET-input op amps provides high-speed and excellent dc performance. The combination of high slew rate and wide bandwidth provide fast settling time. Single, dual, and quad versions have identical specifications for maximum design flexibility. High performance grades are available in the single and dual versions. All are ideal for generalpurpose, audio, data acquisition and communications applications, especially where high source impedance is encountered. OPA op amps are easy to use and free from phase inversion and overload problems often found in common FET-input op amps. Input cascode circuitry provides excellent common-mode rejection and maintains low input bias current over its wide input voltage range. OPA series op amps are stable in unity gain and provide excellent dynamic behavior over a wide range of load conditions, including high load capacitance. Dual and quad versions feature completely independent circuitry for lowest crosstalk and freedom from interaction, even when overdriven or overloaded. Single and dual versions are available in -pin DIP and SO- surface-mount packages. Quad is available in -pin DIP and SO- surface-mount packages. All are specified for C to +5 C operation. Out A In A +In A V Out A In A +In A V+ +In B 5 In B Out B A B A B -Pin DIP, SO- OPA -Pin DIP SO- D C 5 V+ Out B In B +In B Out D In D +In D V +In C 9 In C Out C International Airport Industrial Park Mailing Address: PO Box Tucson, AZ 5 Street Address: S. Tucson Blvd. Tucson, AZ 5 Tel: (5) - Twx: Cable: BBRCORP Telex: -9 FAX: (5) 9-5 Immediate Product Info: () Burr-Brown Corporation PDS-9B Printed in U.S.A. December, 995 PDS-9B
2 SPECIFICATIONS At T A = +5 C, V S = ±5V, unless otherwise noted. OPAP, U OPAP, U OPAPA, UA OPAPA, UA OPAPA, UA PARAMETER CONDITION MIN TYP MAX MIN TYP MAX UNITS OFFSET VOLTAGE Input Offset Voltage ±.5 ±.5 ±.5 ± mv vs Temperature () Operating Temperature Range ± ± * * µv/ C vs Power Supply V S = ±.5V to ±V 5 5 * µv/v Channel Separation (dual and quad) R L = kω. * µv/v INPUT BIAS CURRENT Input Bias Current () V CM = V +5 ±5 * * pa vs Temperature See Typical Curve * Input Offset Current () V CM = V ± ±5 * * pa NOISE Input Voltage Noise Noise Density, f = Hz * nv/ Hz f = Hz * nv/ Hz f = khz * nv/ Hz f = khz * nv/ Hz Current Noise Density, f = khz * fa/ Hz INPUT VOLTAGE RANGE Common-Mode Voltage Range (V )+.5 ± (V+).5 * * * V Common-Mode Rejection V CM =.5V to +.5V 9 9 db INPUT IMPEDANCE Differential * Ω pf Common-Mode V CM =.5V to +.5V * Ω pf OPEN-LOOP GAIN Open-Loop Voltage Gain R L = kω, V O =.5V to +.V * db R L = kω, V O =.V to +.5V db R L = Ω, V O =.V to +.5V db FREQUENCY RESPONSE Gain-Bandwidth Product * MHz Slew Rate ± * V/µs Settling Time:.% G =, V Step, C L = pf. * µs.% G =, V Step, C L = pf * µs Overload Recovery Time G = ±.5 * µs Total Harmonic Distortion + Noise khz, G =, V O =.5Vrms R L = kω. * % R L = Ω.9 * % OUTPUT Voltage Output, Positive R L = kω (V+). (V+).9 * * V Negative (V )+.5 (V )+. * * V Positive R L = kω (V+).5 (V+). * * V Negative (V )+. (V )+.9 * * V Positive R L = Ω (V+).5 (V+). * * V Negative (V )+. (V )+.9 * * V Short-Circuit Current ± * ma Capacitive Load Drive (Stable Operation) See Typical Curve * POWER SUPPLY Specified Operating Voltage ±5 * V Operating Voltage Range ±.5 ± * * V Quiescent Current (per amplifier) I O = ± ±. * * ma TEMPERATURE RANGE Operating Range +5 * * C Storage +5 * * C Thermal Resistance, θ JA -Pin DIP * C/W SO- Surface-Mount 5 * C/W -Pin DIP * C/W SO- Surface-Mount * C/W *Specifications same as OPAP, OPAU. NOTES: () Guaranteed by wafer test. () High-speed test at T J = 5 C. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. OPA,,
3 ABSOLUTE MAXIMUM RATINGS Supply Voltage, V+ to V... V Input Voltage... (V ).V to (V+) +.V Output Short-Circuit ()... Continuous Operating Temperature... C to +5 C Storage Temperature... C to +5 C Junction Temperature... 5 C Lead Temperature (soldering, s)... C NOTE: () Short-circuit to ground, one amplifier per package. PACKAGE INFORMATION PACKAGE DRAWING MODEL PACKAGE NUMBER () Single OPAPA -Pin Plastic DIP OPAP -Pin Plastic DIP OPAUA SO- Surface-Mount OPAU SO- Surface-Mount Dual OPAPA -Pin Plastic DIP OPAP -Pin Plastic DIP OPAUA SO- Surface-Mount OPAU SO- Surface-Mount Quad OPAPA -Pin Plastic DIP OPAUA SO- Surface-Mount 5 ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: () For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. ORDERING INFORMATION MODEL PACKAGE TEMPERATURE RANGE Single OPAPA -Pin Plastic DIP C to +5 C OPAP -Pin Plastic DIP C to +5 C OPAUA SO- Surface-Mount C to +5 C OPAU SO- Surface-Mount C to +5 C Dual OPAPA -Pin Plastic DIP C to +5 C OPAP -Pin Plastic DIP C to +5 C OPAUA SO- Surface-Mount C to +5 C OPAU SO- Surface-Mount C to +5 C Quad OPAPA -Pin Plastic DIP C to +5 C OPAUA SO- Surface-Mount C to +5 C OPA,,
4 TYPICAL PERFORMANCE CURVES At T A = +5 C, V S = ±5V, R L = kω, unless otherwise noted. Voltage Gain (db) OPEN-LOOP GAIN/PHASE vs FREQUENCY 5 φ 9 5 G. k k k M M Phase Shift ( ) PSR, CMR (db) POWER SUPPLY AND COMMON-MODE REJECTION vs FREQUENCY +PSR PSR CMR k k k M k INPUT VOLTAGE AND CURRENT NOISE SPECTRAL DENSITY vs FREQUENCY CHANNEL SEPARATION vs FREQUENCY R L = Voltage Noise (nv/ Hz) Current Noise (fa/ Hz) Voltage Noise Current Noise k k k M Channel Separation (db) R L = kω Dual and quad devices. G =, all channels. Quad measured channel A to D or B to C other combinations yield improved rejection. k k k Input Bias Current (pa) k k k INPUT BIAS CURRENT vs TEMPERATURE High Speed Test Warmed Up Dual Single Quad Ambient Temperature ( C) Input Bias Current (pa) INPUT BIAS CURRENT vs INPUT COMMON-MODE VOLTAGE 9 High Speed Test Common-Mode Voltage (V) OPA,,
5 TYPICAL PERFORMANCE CURVES (CONT) At T A = +5 C, V S = ±5V, R L = kω, unless otherwise noted. A OL, CMR, PSR vs TEMPERATURE. QUIESCENT CURRENT AND SHORT-CIRCUIT CURRENT vs TEMPERATURE A OL, CMR, PSR (db) CMR Open-Loop Gain PSR Quiescent Current Per Amp (ma)....9 ±I Q ±I SC 5 Short-Circuit Current (ma) Ambient Temperature ( C) Ambient Temperature ( C) Percent of Amplifiers (%) OFFSET VOLTAGE PRODUCTION DISTRIBUTION Typical production distribution of packaged units. Single, dual and quad units included. Percent of Amplifiers (%) OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION Typical production distribution of packaged units. Single, dual and quad units included. Offset Voltage (µv) Offset Voltage Drift (µv/ C). TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY R L kω Ω V S = ±5V MAXIMUM OUTPUT VOLTAGE vs FREQUENCY Maximum output voltage without slew-rate induced distortion THD+Noise (%).. G = + G = + Output Voltage (Vp-p) V S = ±5V V O =.5Vrms. k k k V S = ±.5V k k M M 5 OPA,,
6 TYPICAL PERFORMANCE CURVES (CONT) At T A = +5 C, V S = ±5V, R L = kω, unless otherwise noted. SMALL-SIGNAL STEP RESPONSE G =, C L = pf LARGE-SIGNAL STEP RESPONSE G =, C L = pf 5mV/div 5V/div ns/div µs/div SETTLING TIME vs CLOSED-LOOP GAIN SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE 5 G = + Settling Time (µs).% FPO.% Overshoot (%) G = G = ±. ± ± ± ± Closed-Loop Gain (V/V) pf nf nf Load Capacitance Output Voltage Swing (V) OUTPUT VOLTAGE SWING vs OUTPUT CURRENT 5 V IN = 5V 55 C 5 C 5 C 5 C 5 C 5 C 5 C 55 C 5 V IN = 5V 5 Output Current (ma) OPA,,
7 APPLICATIONS INFORMATION OPA series op amps are unity-gain stable and suitable for a wide range of general-purpose applications. Power supply pins should be bypassed with nf ceramic capacitors or larger. OPA op amps are free from unexpected output phasereversal common with FET op amps. Many FET-input op amps exhibit phase-reversal of the output when the input common-mode voltage range is exceeded. This can occur in voltage-follower circuits, causing serious problems in control loop applications. OPA series op amps are free from this undesirable behavior. All circuitry is completely independent in dual and quad versions, assuring normal behavior when one amplifier in a package is overdriven or short-circuited. OPERATING VOLTAGE OPA series op amps operate with power supplies from ±.5V to ±V with excellent performance. Although specifications are production tested with ±5V supplies, most behavior remains unchanged throughout the full operating voltage range. Parameters which vary significantly with operating voltage are shown in the typical performance curves. OFFSET VOLTAGE TRIM Offset voltage of OPA series amplifiers is laser trimmed and usually requires no user adjustment. The OPA (single op amp version) provides offset voltage trim connections on pins and. Offset voltage can be adjusted by connecting a potentiometer as shown in Figure. This adjustment should be used only to null the offset of the op amp, not to adjust system offset or offset produced by the signal source. Nulling offset could degrade the offset voltage drift behavior of the op amp. While it is not possible to predict the exact change in drift, the effect is usually small. nf nf V+ V kω OPA Trim Range: ±mv typ OPA single op amp only. Use offset adjust pins only to null offset voltage of op amp see text. FIGURE. OPA Offset Voltage Trim Circuit. INPUT BIAS CURRENT The FET-inputs of the OPA series provide very low input bias current and cause negligible errors in most applications. For applications where low input bias current is crucial, junction temperature rise should be minimized. The input bias current of FET-input op amps increases with temperature as shown in the typical performance curve Input Bias Current vs Temperature. The OPA series may be operated at reduced power supply voltage to minimize power dissipation and temperature rise. Using ±V supplies reduces power dissipation to one-fifth that at ±5V. The dual and quad versions have higher total power dissipation than the single, leading to higher junction temperature. Thus, a warmed-up quad will have higher input bias current than a warmed-up single. Furthermore, an SOIC will generally have higher junction temperature than a DIP at the same ambient temperature because of a larger θ JA. Refer to the specifications table. Circuit board layout can also help minimize junction temperature rise. Temperature rise can be minimized by soldering the devices to the circuit board rather than using a socket. Wide copper traces will also help dissipate the heat by acting as an additional heat sink. Input stage cascode circuitry assures that the input bias current remains virtually unchanged throughout the full input common-mode range of the OPA series. See the typical performance curve Input Bias Current vs Common- Mode Voltage. OPA,,
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