Programmable Gain INSTRUMENTATION AMPLIFIER

Transcription

1 PGA PGA Programmable Gain INSTRUMENTATION AMPLIFIER FEATURES DIGITALLY PROGRAMMABLE GAIN: PGA: G=,,, V/V PGA: G=,,, 8V/V LOW OFFSET VOLTAGE: µv max LOW OFFSET VOLTAGE DRIFT:.µV/ C LOW INPUT BIAS CURRENT: na max LOW QUIESCENT CURRENT:.mA typ NO LOGIC SUPPLY REQUIRED 6-PIN PLASTIC DIP, SOL-6 PACKAGES APPLICATIONS DATA ACQUISITION SYSTEM GENERAL PURPOSE ANALOG BOARDS MEDICAL INSTRUMENTATION DESCRIPTION The PGA and PGA are low cost, general purpose programmable-gain instrumentation amplifiers offering excellent accuracy. Gains are digitally selected: PGA,,,, and PGA,,, 8V/V. The precision and versatility, and low cost of the PGA and PGA make them ideal for a wide range of applications. Gain is selected by two TTL or CMOS-compatible address lines, A and A. Internal input protection can withstand up to ±V on the analog inputs without damage. The PGA and PGA are laser trimmed for very low offset voltage (µv), drift (.µv/ C) and high common-mode rejection (db at G=). They operate with power supplies as low as ±.V, allowing use in battery operated systems. Quiescent current is ma. The PGA and PGA are available in 6-pin plastic DIP, and SOL-6 surface-mount packages, specified for the C to 8 C temperature range. V O V 3 A PGA PGA Feedback A A Digital Ground 6 Digitally Selected Feedback Network A 3 V O A Ref V OS Adj V O V International Airport Industrial Park Mailing Address: PO Box Tucson, AZ 873 Street Address: 673 S. Tucson Blvd. Tucson, AZ 876 Tel: () 76- Twx: 9-9- Cable: BBRCORP Telex: FAX: () 889- Immediate Product Info: (8) 8-63 PGA/ 99 Burr-Brown Corporation PDS-76A Printed in U.S.A. October, 993 SBOS

2 SPECIFICATIONS ELECTRICAL At T A = C, V S = ±V, and R L = kω unless otherwise noted. PGA G=,,, V/V PGABP, BU PGAAP, AU PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS INPUT Offset Voltage, RTI T A = C ±/G ±/G ±3/G ±/G µv vs Temperature T A =T MIN to T MAX ±../G ±./G ±./G ±/G µv/ C vs Power Supply V S =±.V to ±8V./G 3/G * * µv/v Long-Term Stability ±../G * µv/mo Impedance, Differential 6 * Ω pf Common-Mode 6 * Ω pf Input Common-Mode Range V O =V (see text) ±. ±.7 * * V Safe Input Voltage ± * V Common-Mode Rejection V CM =±V, R S =kω G= db G= db G= 3 6 db G= 3 6 db BIAS CURRENT ±. ± * ± na vs Temperature ±8 * pa/ C Offset Current ±. ± * * na vs Temperature ±8 * pa/ C NOISE, Voltage, RTI () : f=hz G, R S =Ω 6 * nv/ Hz f=hz G, R S =Ω 3 * nv/ Hz f=khz G, R S =Ω 3 * nv/ Hz f B =.Hz to Hz G, R S =Ω. * µvp-p Noise Current f=hz. * pa/ Hz f=khz. * pa/ Hz f B =.Hz to Hz 8 * pap-p GAIN, Error G= ±. ±. * ±. % G= ±. ±. * ±. % G= ±. ±. * ±. % G= ±. ±. * ±. % Gain vs Temperature G= to ±. ± * * ppm/ C Nonlinearity G= ±. ±. * ±. % of FSR G= ±. ±. * ±. % of FSR G= ±. ±. * ±. % of FSR G= ±.8 ±. * ±. % of FSR OUTPUT Voltage, Positive () I O =ma, T MIN to T MAX (V). (V).3 * * V Negative () I O =ma, T MIN to T MAX (V). (V).3 * * V Load Capacitance Stability * pf Short Circuit Current 3/7 * ma FREQUENCY RESPONSE Bandwidth, 3dB G= * MHz G= 8 * khz G= * khz G= * khz Slew Rate V O =±V, G=.3.7 * * V/µs Settling Time (3),.% G= * µs G= 3 * µs G= * µs G= * µs.% G= 3 * µs G= 8 * µs G= * µs G= 3 * µs Overload Recovery % Overdrive 7 * µs DIGITAL LOGIC Digital Ground Voltage, V DG V (V) * * V Digital Low Voltage V V DG.8V * * V Digital Input Current * µa Digital High Voltage V DG V * * V POWER SUPPLY, Voltage ±. ± ±8 * * * V Current =V./. ±6. * ±7. ma TEMPERATURE RANGE Specification 8 * * C Operating * * C θ JA 8 * C/W * Specification same as PGABP. NOTES: () Input-referred noise voltage varies with gain. See typical curves. () Output voltage swing is tested for ±V min on ±.V power supplies. (3) Includes time to switch to a new gain. PGA/

3 SPECIFICATIONS ELECTRICAL At T A = C, V S = ±V, and R L = kω unless otherwise noted. PGA G=,,, 8V/V PGABP, BU PGAAP, AU PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS INPUT Offset Voltage, RTI T A = C ±/G ±/G ±3/G ±/G µv vs Temperature T A =T MIN to T MAX ±../G ±./G ±./G ±/G µv/ C vs Power Supply V S =±.V to ±8V./G 3/G * * µv/v Long-Term Stability ±../G * µv/mo Impedance, Differential 6 * Ω pf Common-Mode 6 * Ω pf Input Common-Mode Range V O =V (see text) ±. ±.7 * * V Safe Input Voltage ± * V Common-Mode Rejection V CM =±V, R S =kω G= db G= db G= db G= db BIAS CURRENT ±. ± * ± na vs Temperature ±8 * pa/ C Offset Current ±. ± * * na vs Temperature ±8 * pa/ C Noise Voltage, RTI () : f=hz G=8, R S =Ω 9 * nv/ Hz f=hz G=8, R S =Ω * nv/ Hz f=khz G=8, R S =Ω * nv/ Hz f B =.Hz to Hz G=8, R S =Ω. * µvp-p Noise Current f=hz. * pa/ Hz f=khz. * pa/ Hz f B =.Hz to Hz 8 * pap-p GAIN, Error G= ±. ±. * ±. % G= ±. ±. * ±. % G= ±. ±. * ±. % G=8 ±. ±. * ±. % Gain vs Temperature G= to 8 ±. ± * * ppm/ C Nonlinearity G= ±. ±. * ±. % of FSR G= ±. ±. * ±. % of FSR G= ±. ±. * ±. % of FSR G=8 ±. ±. * ±. % of FSR OUTPUT Voltage, Positive () I O =ma, T MIN to T MAX (V). (V).3 * * V Negative () I O =ma, T MIN to T MAX (V). (V).3 * * V Load Capacitance Stability * pf Short Circuit Current 3/7 * ma FREQUENCY RESPONSE Bandwidth, 3dB G= * MHz G= * khz G= * khz G=8 * khz Slew Rate V O =±V, G=8.3.7 * * V/µs Settling Time (3),.% G= * µs G= * µs G= 3 * µs G=8 3 * µs.% G= 3 * µs G= 3 * µs G= * µs G=8 8 * µs Overload Recovery % overdrive 7 * µs DIGITAL LOGIC INPUTS Digital Ground Voltage, V DG V (V) * * V Digital Low Voltage V V DG.8V * * V Digital Low Current * µa Digital High Voltage V DG V * * V POWER SUPPLY, Voltage ±. ± ±8 * * * V Current =V./. ±6. * ±7. ma TEMPERATURE RANGE Specification 8 * * C Operating * * C θ JA 8 * C/W * Specification same as PGABP. NOTES: () Input-referred noise voltage varies with gain. See typical curves. () Output voltage swing is tested for ±V min on ±.V power supplies. (3) Includes time to switch to a new gain. 3 PGA/

4 PACKAGE INFORMATION PACKAGE DRAWING MODEL PACKAGE NUMBER () PGAAP 6-Pin Plastic DIP 8 PGABP 6-Pin Plastic DIP 8 PGAAU SOL-6 Surface Mount PGABU SOL-6 Surface Mount PGAAP 6-Pin Plaseic DIP 8 PGABP 6-Pin Plastic DIP 8 PGAAU SOL-6 Surface Mount PGABU SOL-6 Surface Mount ABSOLUTE MAXIMUM RATINGS Supply Voltage... ±8V Analog Input Voltage Range... ±V Logic Input Voltage Range... ±V S Output Short-Circuit (to ground)... Continuous Operating Temperature... C to C Storage Temperature... C to C Junction Temperature... C Lead Temperature (soldering s)... 3 C NOTE: () For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. ORDERING INFORMATION MODEL GAINS PACKAGE TEMPERATURE RANGE PGAAP,,, V/V 6-Pin Plastic DIP to 8 C PGABP,,, V/V 6-Pin Plastic DIP to 8 C PGAAU,,, V/V SOL-6 Surface-Mount to 8 C PGABU,,, V/V SOL-6 Surface-Mount to 8 C PGAAP,,, 8V/V 6-Pin Plastic DIP to 8 C PGABP,,, 8V/V 6-Pin Plastic DIP to 8 C PGAAU,,, 8V/V SOL-6 Surface-Mount to 8 C PGABU,,, 8V/V SOL-6 Surface-Mount to 8 C PGA/

5 DICE INFORMATION FPO PAD FUNCTION PAD FUNCTION V O 9 V O Ref 3 V O V IN Feedback V IN 3 V 6 V OS Adj Dig. Ground 7 V OS Adj A 8 V 6 A Substrate Bias: Internally connected to V power supply. MECHANICAL INFORMATION MILS (.") MILLIMETERS Die Size 86 x 3 ±.7 x 3.3 ±.3 Die Thickness ±3. ±.8 Min. Pad Size x. x. Backing Gold PGA/ DIE TOPOGRAPHY PIN CONFIGURATION Top View ELECTROSTATIC DISCHARGE SENSITIVITY V O NC NC V IN V IN V OS Adjust V OS Adjust V A A Dig. Ground V Feedback V O Ref V O This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NC: No Internal Connection. PGA/

6 TYPICAL PERFORMANCE CURVES At T A = C, and V S = ±V, unless otherwise noted. Gain (V/V) k G=k G= G= G= GAIN vs FREQUENCY k k k M Frequency (Hz) Common-Mode Rejection (db) 8 6 COMMON-MODE REJECTION vs FREQUENCY B Grade G = G = k, G = G = k k k M Frequency (Hz) G = k G = G = Common-Mode Voltage (V) INPUT COMMON-MODE VOLTAGE RANGE vs OUTPUT VOLTAGE Limited by A Output Swing V D/ V D/ V CM (Any Gain) A 3 Output Swing Limit Limited by A Output Swing Output Voltage (V) Limited by A Output Swing V O A 3 Output Swing Limit Limited by A Output Swing Power Supply Rejection (db) 8 6 POSITIVE POWER SUPPLY REJECTION vs FREQUENCY G = G = G = k G = k k k M Frequency (Hz) Power Supply Rejection (db) 8 6 NEGATIVE POWER SUPPLY REJECTION vs FREQUENCY k k k M Frequency (Hz) G = k G = G = G = Input-Referred Noise Voltage (nv/ Hz) k INPUT- REFERRED NOISE VOLTAGE vs FREQUENCY G =, k G = G = k Frequency (Hz) G = k BW Limit k PGA/ 6

7 TYPICAL PERFORMANCE CURVES (CONT) At T A = C, and V S = ±V, unless otherwise noted. Offset Voltage Change (µv) 6 6 INPUT-REFERRED OFFSET VOLTAGE WARM-UP vs TIME G > Time from Power Supply Turn-on (s) Input Bias and Input Offset Current (na) 7 INPUT BIAS AND INPUT OFFSET CURRENT vs TEMPERATURE ±I B I OS 7 Temperature ( C) 3 INPUT BIAS CURRENT vs DIFFERENTIAL INPUT VOLTAGE 3 INPUT BIAS CURRENT vs COMMON-MODE INPUT VOLTAGE I b I b Both Inputs Input Current (ma) G = G = Input Bias Current (ma) One Input Normal Operation One Input G =, k Differential Overload Voltage (V) 3 Both Inputs 3 3 Common-Mode Voltage (V) 3 MAXIMUM OUTPUT VOLTAGE vs FREQUENCY. SLEW RATE vs TEMPERATURE Output Voltage (Vp-p) G Slew Rate (V/µs) G=8 or k k k M 7 7 Frequency (Hz) Temperature ( C) 7 PGA/

8 TYPICAL PERFORMANCE CURVES (CONT) At T A = C, and V S = ±V, unless otherwise noted. 3 OUTPUT CURRENT LIMIT vs TEMPERATURE 6. QUIESCENT CURRENT vs TEMPERATURE Short Circuit Current (ma) I CL I CL Quiescent Current (ma) Temperature ( C) Temperature ( C). QUIESCENT CURRENT vs POWER SUPPLY VOLTAGE V 6 POSITIVE OUTPUT SWING vs TEMPERATURE V S = ±V Quiescent Current (ma)... V Output Voltage (V) 8 6 V S =. V S = ±. 3. ± ± ± ± Power Supply Voltage (V) 7 7 Temperature ( C) 6 NEGATIVE OUTPUT SWING vs TEMPERATURE V S = ±V Output Voltage (V) 8 6 V S =. V S = ±. 7 7 Temperature ( C) PGA/ 8

9 TYPICAL PERFORMANCE CURVES (CONT) At T A = C, and V S = ±V, unless otherwise noted. SMALL-SIGNAL RESPONSE, G = LARGE-SIGNAL RESPONSE, G = mv V mv V SMALL-SIGNAL RESPONSE, G = LARGE-SIGNAL RESPONSE, G = mv V mv V SMALL-SIGNAL RESPONSE, G = LARGE-SIGNAL RESPONSE, G = mv V mv V 9 PGA/

10 TYPICAL PERFORMANCE CURVES (CONT) At T A = C, and V S = ±V, unless otherwise noted. INPUT-REFERRED NOISE,. TO Hz, G = NOISE,. TO Hz, G =.µv/div.µv/div s/div s/div APPLICATION INFORMATION Figure shows the basic connections required for operation of the PGA/. Applications with noisy or high impedance power supplies may require decoupling capacitors close to the device pins as shown. The output is referred to the output reference (Ref) terminal which is normally grounded. This must be a low-impedance connection to assure good common-mode rejection. A resistance of Ω in series with the Ref pin will cause a typical device to degrade to approximately 8dB CMR (G=). The PGA/ has an output feedback connection (pin ). Pin must be connected to the output terminal (pin ) for proper operation. The output Feedback connection can be used to sense the output voltage directly at the load for best accuracy. DIGITAL INPUTS The digital inputs A and A select the gain according to the logic table in Figure. Logic is defined as a voltage greater than V above digital ground potential (pin ). Digital ground can be connected to any potential from the V power supply to V less than V. Digital ground is normally connected to ground. The digital inputs interface directly CMOS and TTL logic components. Approximately µa flows out of the digital input pins when a logic is applied. Logic input current is nearly zero with a logic input. A constant current of approximately V µf V O A PGA PGA Feedback 6 Digitally Selected Feedback Network A 3 V O V O = G ( ) A Ref PGA GAIN PGA 8 A A V OS Adj V O V µf Sometimes shown in simplified form: PGA V O A A FIGURE. Basic Connections. PGA/

11 kω V Switches, jumpers or open-collector logic output. kω 6 Digital ground can alternatively be connected to V power supply. FIGURE. Switch or Jumper-Selected Digital Inputs..3mA flows in the digital ground pin. It is good practice to return digital ground through a separate connection path so that analog ground is not affected by the digital ground current. The digital inputs, A and A, are not latched; a change in logic inputs immediately selects a new gain. Switching time of the logic is approximately µs. The time to respond to gain change is effectively the time it takes the amplifier to settle to a new output voltage in the newly selected gain (see settling time specifications). Many applications use an external logic latch to access gain control data from a high speed data bus (see Figure 7). Using an external latch isolates the high speed digital bus from sensitive analog circuitry. Locate the latch circuitry as far as practical from analog circuitry. A Digitally Selected Feedback Network A V OS Adj V O Some applications select gain of the PGA/ with switches or jumpers. Figure shows pull-up resistors connected to assure a noise-free logic when the switch, jumper or open-collector logic is open or off. Fixed-gain applications can connect the logic inputs directly to V or V (or other valid logic level); no resistor is required. OFFSET VOLTAGE Voltage offset of the PGA/ consists of two components input stage offset and output stage offset. Both components are specified in the specification table in equation form: V OS = V OSI V OSO / G () where: V OS total is the combined offset, referred to the input. V OSI is the offset voltage of the input stage, A and A. V OSO is the offset voltage of the output difference amplifier, A 3. V OSI and V OSO do not change with gain. The composite offset voltage V OS changes with gain because of the gain term in equation. Input stage offset dominates in high gain (G ); both sources of offset may contribute at low gain (G= to ). OFFSET TRIMMING Both the input and output stages are laser trimmed for very low offset voltage and drift. Many applications require no external offset adjustment. Figure 3 shows an optional input offset voltage trim circuit. This circuit should be used to adjust only the input stage offset voltage of the PGA/. Do this by programming V O V A A Digital Ground 6 A Digitally Selected Feedback Network 6 A 7 V O V A 3 PGA PGA Feedback V REF ±mv Adjustment Range V O = G ( ) V REF OPA77 Resistors can be substituted for REF. Power supply rejection will be degraded. kω V µa / REF Ω Ω Input Offset Adjustment Trim Range ±µv V kω to MΩ Output Offset Adjustment µa / REF V FIGURE 3. Optional Offset Voltage Trim Circuit. PGA/

12 it to its highest gain and trimming the output voltage to zero with the inputs grounded. Drift performance usually improves slightly when the input offset is nulled with this procedure. Do not use the input offset adjustment to trim system offset or offset produced by a sensor. Nulling offset that is not produced by the input amplifiers will increase temperature drift by approximately 3.3µV/ C per mv of offset adjustment. Many applications that need input stage offset adjustment do not need output stage offset adjustment. Figure 3 also shows a circuit for adjusting output offset voltage. First, adjust the input offset voltage as discussed above. Then program the device for G= and adjust the output to zero. Because of the interaction of these two adjustments at G=8, the PGA may require iterative adjustment. The output offset adjustment can be used to trim sensor or system offsets without affecting drift. The voltage applied to the Ref terminal is summed with the output signal. Low impedance must be maintained at this node to assure good common-mode rejection. This is achieved by buffering the trim voltage with an op amp as shown. NOISE PERFORMANCE The PGA/ provides very low noise in most applications. Low frequency noise is approximately.µvp-p measured from. to Hz. This is approximately one-tenth the noise of low noise chopper-stabilized amplifiers. Microphone, Hydrophone etc. Thermocouple V R Bridge 7kΩ kω 7kΩ PGA PGA PGA Center-tap provides bias current return. PGA INPUT BIAS CURRENT RETURN PATH The input impedance of the PGA/ is extremely high approximately Ω. However, a path must be provided for the input bias current of both inputs. This input bias current is typically less than ±na (it can be either polarity due to cancellation circuitry). High input impedance means that this input bias current changes very little with varying input voltage. Input circuitry must provide a path for this input bias current if the PGA/ is to operate properly. Figure shows provisions for an input bias current path. Without a bias current return path, the inputs will float to a potential which exceeds the common-mode range of the PGA/ and the input amplifiers will saturate. If the differential source resistance is low, bias current return path can be connected to one input (see thermocouple example in Figure ). With higher source impedance, using two resistors provides a balanced input with possible advantages of lower input offset voltage due bias current and better common-mode rejection. Many sources or sensors inherently provide a path for input bias current (e.g. the bridge sensor shown in Figure ). These applications do not require additional resistor(s) for proper operation. Bias current return inherrently provided by source. FIGURE. Providing an Input Common-Mode Current Path. INPUT COMMON-MODE RANGE The linear common-mode range of the input op amps of the PGA/ is approximately ±.7V (or.3v from the power supplies). As the output voltage increases, however, the linear input range will be limited by the output voltage swing of the input amplifiers, A and A. The commonmode range is related to the output voltage of the complete amplifier see performance curve Input Common-Mode Range vs Output Voltage. A combination of common-mode and differential input voltage can cause the output of A or A to saturate. Figure shows the output voltage swing of A and A expressed in terms of a common-mode and differential input voltages. Output swing capability of these internal amplifiers is the same as the output amplifier, A 3. For applications where input common-mode range must be maximized, limit the output voltage swing by selecting a lower gain of the PGA/ (see performance curve Input Common-Mode Voltage Range vs Output Voltage ). If necessary, add gain after the PGA/ to increase the voltage swing. PGA/

13 V CM G V D V O V 3 PGA PGA Feedback V D A V D A A Digital Ground 6 Digitally Selected Feedback Network A 3 V O V CM A Ref V CM G V D 9 8 V O V FIGURE. Voltage Swing of A and A. Input-overload often produces an output voltage that appears normal. For example, consider an input voltage of V on one input and V on the other input will obviously exceed the linear common-mode range of both input amplifiers. Since both input amplifiers are saturated to the nearly the same output voltage limit, the difference voltage measured by the output amplifier will be near zero. The output of the PGA/ will be near V even though both inputs are overloaded. INPUT PROTECTION The inputs of the PGA/ are individually protected for voltages up to ±V. For example, a condition of V on one input and V on the other input will not cause damage. Internal circuitry on each input provides low series impedance under normal signal conditions. To provide equivalent protection, series input resistors would contribute excessive noise. If the input is overloaded, the protection circuitry limits the input current to a safe value (approximately.ma). The typical performance curve Input Bias Current vs Common-Mode Input Voltage shows this input current limit behavior. The inputs are protected even if no power supply voltage is present. 7kΩ SWITCH POSITION V D, D: IN8, IN9, etc. A B C D A B C D 7kΩ PGA A A X GAIN PGA PGA PGA 8 FIGURE 6. Switch-Selected PGIA. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. 3 PGA/

14 V HI A V O V 3 PGA PGA Feedback A A 6 Digitally Selected Feedback Network A A 3 Ref V O A A V V OS Adj V O V Data Out 7HC7 Data In Data Bus CK To Address Decoding Logic FIGURE 7. Multiplexed-Input Programmable Gain IA. A A PGA PGA V O V O Ref V O Ω A A kω kω OPA77 FIGURE 8. Shield Drive Circuit. A A O PGA A AO PGA V O PGA PGA Ref C.µF V O R MΩ A A GAIN A 3 A A A OPA6 f 3dB = πr C =.9Hz FIGURE 9. Binary Gain Steps, G= to G=6. FIGURE. AC-Coupled PGIA. PGA/

15 PACKAGE OPTION ADDENDUM -Oct-7 PACKAGING INFORMATION Orderable Device Status () Package Type Package Drawing Pins Package Qty PGAAP ACTIVE PDIP N 6 Green (RoHS & PGAAPG ACTIVE PDIP N 6 Green (RoHS & PGAAU ACTIVE SOIC DW 6 8 Green (RoHS & PGAAU/K ACTIVE SOIC DW 6 Green (RoHS & PGAAU/KE ACTIVE SOIC DW 6 Green (RoHS & PGAAUE ACTIVE SOIC DW 6 8 Green (RoHS & PGABP ACTIVE PDIP N 6 Green (RoHS & PGABPG ACTIVE PDIP N 6 Green (RoHS & PGABU ACTIVE SOIC DW 6 8 Green (RoHS & PGABU/K ACTIVE SOIC DW 6 Green (RoHS & PGABU/KE ACTIVE SOIC DW 6 Green (RoHS & PGABUE ACTIVE SOIC DW 6 8 Green (RoHS & PGAAP ACTIVE PDIP N 6 Green (RoHS & PGAAPG ACTIVE PDIP N 6 Green (RoHS & PGAAU ACTIVE SOIC DW 6 8 Green (RoHS & PGAAU/K ACTIVE SOIC DW 6 Green (RoHS & PGAAU/KG ACTIVE SOIC DW 6 Green (RoHS & PGAAUG ACTIVE SOIC DW 6 8 Green (RoHS & PGABP ACTIVE PDIP N 6 Green (RoHS & PGABPG ACTIVE PDIP N 6 Green (RoHS & PGABU ACTIVE SOIC DW 6 8 Green (RoHS & PGABUG ACTIVE SOIC DW 6 8 Green (RoHS & Eco Plan () Lead/Ball Finish MSL Peak Temp (3) N / A for Pkg Type N / A for Pkg Type Level-3-6C-68 HR Level-3-6C-68 HR Level-3-6C-68 HR Level-3-6C-68 HR N / A for Pkg Type N / A for Pkg Type Level-3-6C-68 HR Level-3-6C-68 HR Level-3-6C-68 HR Level-3-6C-68 HR N / A for Pkg Type N / A for Pkg Type Level-3-6C-68 HR Level-3-6C-68 HR Level-3-6C-68 HR Level-3-6C-68 HR N / A for Pkg Type N / A for Pkg Type Level-3-6C-68 HR Level-3-6C-68 HR () The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. Addendum-Page

16 PACKAGE OPTION ADDENDUM -Oct-7 OBSOLETE: TI has discontinued the production of the device. () Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed.% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either ) lead-based flip-chip solder bumps used between the die and package, or ) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & : TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed.% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page

17 PACKAGE MATERIALS INFORMATION -Mar-8 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Reel Diameter Width (mm) W (mm) A (mm) B (mm) K (mm) P (mm) PGAAU/K SOIC DW Q PGABU/K SOIC DW Q PGAAU/K SOIC DW Q W (mm) Pin Quadrant Pack Materials-Page

18 PACKAGE MATERIALS INFORMATION -Mar-8 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PGAAU/K SOIC DW PGABU/K SOIC DW PGAAU/K SOIC DW Pack Materials-Page

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