Precision Gain = 10 DIFFERENTIAL AMPLIFIER

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1 Precision Gain = 0 DIFFERENTIAL AMPLIFIER SBOSA AUGUST 987 REVISED OCTOBER 00 FEATURES ACCURATE GAIN: ±0.0% max HIGH COMMON-MODE REJECTION: 8dB min NONLINEARITY: 0.00% max EASY TO USE PLASTIC 8-PIN DIP, SO-8 SOIC PACKAGES APPLICATIONS G = 0 DIFFERENTIAL AMPLIFIER G = +0 AMPLIFIER G = 0 AMPLIFIER G = + AMPLIFIER INSTRUMENTATION AMPLIFIER DESCRIPTION The is a monolithic Gain = 0 differential amplifier consisting of a precision op amp and on-chip metal film resistors. The resistors are laser trimmed for accurate gain and high common-mode rejection. Excellent TCR tracking of the resistors maintains gain accuracy and common-mode rejection over temperature. The differential amplifier is the foundation of many commonly used circuits. The provides this precision circuit function without using an expensive resistor network. The is available in 8-pin plastic DIP and SO-8 surface-mount packages. In +In R R R R Sense V+ Output V Reference Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright , Texas Instruments Incorporated

2 SPECIFICATIONS ELECTRICAL At + C, V S = ±V, unless otherwise specified. KP, U PARAMETER CONDITIONS MIN TYP MAX UNITS GAIN Initial () 0 V/V Error % vs Temperature 4 ppm/ C Nonlinearity () % OUTPUT Related Voltage I O = +0mA, ma 0 V Rated Current V O = 0V +0, ma Impedance 0.0 Ω Current Limit To Common +40/ 0 ma Capacitive Load Stable Operation 000 pf INPUT Impedance Differential 0 kω Common-Mode 0 kω Voltage Range Differential ± V Common-Mode ± V Common-Mode Rejection () T A = T MIN to T MAX 8 00 db OFFSET VOLTAGE RTI (4) Initial 0 00 µv vs Temperature 0. µv/ C vs Supply ±V S = V to 8V 0 µv/v vs Time 0 µv/mo NOISE VOLTAGE RTI () f B = 0.0Hz to 0Hz µvp-p f O = 0kHz 0 nv/ Hz DYNAMIC RESPONSE Small Signal db MHz Full Power BW V O = 0Vp-p 0 0 khz Slew Rate V/µs Settling Time: 0.% V O = 0V Step µs 0.0% V O = 0V Step 0 µs 0.0% V CM = 0V Step, V DIFF = 0V µs POWER SUPPLY Rated ± V Voltage Range Derated Performance ± ±8 V Quiescent Current V O = 0V ±. ± ma TEMPERATURE RANGE Specification C Operation C Storage +0 C NOTES: () Connected as difference amplifier (see Figure ). () Nonlinearity is the maximum peak deviation from the best-fit straight line as a percent of full-scale peakto-peak output. () With zero source impedance (see Maintaining CMR section). (4) Includes effects of amplifiers s input bias and offset currents. () Includes effect of amplifier s input current noise and thermal noise contribution of resistor network. SBOSA

3 PIN CONFIGURATION Top View () Ref 8 In 7 +In V 4 DIP/SOIC NC V+ Output Sense ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: () Pin indentifier for SO-8 package. Model number identification may be abbreviated on SO-8 package due to limited available space. ABSOLUTE MAXIMUM RATINGS Power Supply Voltage... ±8V Input Voltage Range... ±V S Operating Temperature Range: P, U C to +8 C Storage Temperature Range C to +8 C Lead Temperature (soldering, 0s): P C Wave Soldering (s, max) U C Output Short Circuit to Common... Continuous PACKAGE/ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet. NOTE: () Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. SBOSA

4 TYPICAL PERFORMANCE CURVES At T A = + C, V S = ±V, unless otherwise noted. STEP RESPONSE SMALL SIGNAL RESPONSE (No Load) 0 Output Voltage (mv) 0 0 µs/div µs/div SMALL SIGNAL RESPONSE (R LOAD =, C LOAD = 00pF) TOTAL HARMONIC DISTORTION AND NOISE vs FREQUENCY A = 0dB, Vrms, load 0 Output Voltage (mv) 0 THD + N (%) Noninverting Inverting 0 µs/div kHz low-pass filtered k 0k 00k Frequency (Hz) V OUT (V) MAXIMUM V OUT vs I OUT (Negative Swing) V S = ±8V V S = ±V V S = ±V V OUT (V) MAXIMUM V OUT vs I OUT (Positive Swing) V S = ±8V V S = ±V V S = ±V. V S = ±V I OUT (ma). V S = ±V I OUT (ma) 4 SBOSA

5 TYPICAL PERFORMANCE CURVES (CONT) At T A = + C, V S = ±V, unless otherwise noted. 0 CMR vs FREQUENCY 40 POWER SUPPLY REJECTION vs FREQUENCY 00 0 CMR (db) PSRR (db) V 70 0 V k 0k 00k Frequency (Hz) k 0k 00k Frequency (Hz) APPLICATIONS INFORMATION Figure shows the basic connections required for operation of the. Power supply bypass capacitors should be connected close to the device pins as shown. µf V 4 7 R R V+ µf V Ref terminal will be summed with the output signal. The source impedance of a signal applied to the Ref terminal should be less than 0Ω to maintain good common-mode rejection. Figure shows a voltage applied to pin to trim the offset voltage of the. The known 00Ω source impedance of the trim circuit is compensated by the 0Ω resistor in series with pin to maintain good CMR. V R R 4 + V OUT = 0(V V ) V V 0Ω R R R V O FIGURE. Basic Power Supply and Signal Connections. The differential input signal is connected to pins and as shown. The source impedance connected to the inputs must be equal to assure good common-mode rejection. A Ω mismatch in source impedance will degrade the commonmode rejection of a typical device to approximately 8dB. If the source has a known source impedance mismatch, an additional resistor in series with one input can be used to preserve good common-mode rejection. The output is referred to the output reference terminal (pin ) which is normally grounded. A voltage applied to the Compensates for some impedance at pin. See text. V O = V V Offset Adjustment Range = ±mv FIGURE. Offset Adjustment. R 4 00Ω 499kΩ +V V Referring to Figure, the CMR depends upon the match of the internal R 4 /R ratio to the R /R ratio. A CMR of 0dB requires resistor matching of 0.00%. To maintain high CMR over temperature, the resistor TCR tracking must be better than ppm/ C. These accuracies are difficult and expensive to reliably achieve with discrete components. SBOSA

6 V 0Ω 00Ω Gain Adjust E In A R V 0Ω To eliminate adjustment interactions, first adjust gain with V grounded. 00Ω FIGURE. Difference Amplifier with Gain and CMR Adjust. V Gain Error = 0.0% maximum Nonlinearity = 0.00% maximum Gain Drift =.ppm/ C FIGURE 4. Precision G = 0 Inverting Amplifier. V O V O = 0V E 0 CMR Adjust E +In R A R E 0 = 0( + R /R ) (E E ) To make a high performance high gain instrumentation amplifier, the can be combined with state-of-the-art op amps. For low source impedance applications, OPA7s will give the best noise, offset, and temperature drift. At source impedances above about, the bias current noise of the OPA7 reacting with input impedance degrades noise. For these applications, use an OPA or a dual OPA FET input op amp for lower noise. For an electrometer grade IA, use the OPA8 see table below. Using the for the difference amplifier also extends the input commonmode range of the instrumentation amplifier to ±0V. A conventional IA with a unity-gain difference amplifier has an input common-mode range limited to ±V for an output swing of ±0V. This is because a unity-gain difference amp needs ±V at the input for 0V at the output, allowing only V additional for common-mode. R R GAIN CMRR NOISE AT khz A, A (Ω) (kω) (V/V) (db) I b (pa) (nv/ Hz) OPA7A OPAB OPA8LM FIGURE. Precision Instrumentation Amplifier. R R E 0 Output R R V V R 4 R V 0 V 0 = V + 0 V V IN R 4 V O V O = V IN FIGURE 7. Precision Summing Amplifier. ±00V Safe Input R This circuit follows an / divider with a gain of for an overall gain of unity. With an / divider, the input signal can exceed 00V without damage. FIGURE. Voltage Follower with Input Protection. V O V IN V O = V IN Gain Error = 0.0% maximum FIGURE 8. Precision G = Buffer. SBOSA

7 PACKAGE OPTION ADDENDUM 4-Aug-08 PACKAGING INFORMATION Orderable Device Status () Package Type Package Drawing Pins Package Qty Eco Plan KP ACTIVE PDIP P 8 0 Green (RoHS & no Sb/Br) U ACTIVE SOIC D 8 7 Green (RoHS & no Sb/Br) U/K ACTIVE SOIC D 8 00 Green (RoHS & no Sb/Br) UE4 ACTIVE SOIC D 8 7 Green (RoHS & no Sb/Br) () Lead/Ball Finish () MSL Peak Temp () Op Temp ( C) CU NIPDAU N / A for Pkg Type -40 to 8 KP CU NIPDAU-DCC Level--0C-8 HR INA 0U CU NIPDAU-DCC Level--0C-8 HR INA 0U CU NIPDAU-DCC Level--0C-8 HR INA 0U Device Marking (4/) Samples () The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. () RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 0 RoHS substances, including the requirement that RoHS substance do not exceed 0.% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=000ppm threshold. Antimony trioxide based flame retardants must also meet the <=000ppm threshold requirement. () MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. () Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. () Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page

8 PACKAGE OPTION ADDENDUM 4-Aug-08 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page

9 PACKAGE MATERIALS INFORMATION 4-Jul-0 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W (mm) A0 (mm) B0 (mm) K0 (mm) P (mm) W (mm) Pin Quadrant U/K SOIC D Q Pack Materials-Page

10 PACKAGE MATERIALS INFORMATION 4-Jul-0 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) U/K SOIC D Pack Materials-Page

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