High Common-Mode Voltage Difference Amplifier AD629

Transcription

1 a FEATURES Improved Replacement for: INAP and INAKU V Common-Mode Voltage Range Input Protection to: V Common Mode V Differential Wide Power Supply Range (. V to V) V Output Swing on V Supply ma Max Power Supply Current HIGH ACCURACY DC PERFORMAE ppm Max Gain Nonlinearity V/ C Max Offset Drift (AD9A) V/ C Max Offset Drift (AD9B) ppm/ C Max Gain Drift EXCELLENT AC SPECIFICATIONS db Min Hz (AD9A) db Min Hz (AD9B) khz Bandwidth APPLICATIONS High Voltage Current Sensing Battery Cell Voltage Monitor Power Supply Current Monitor Motor Control Isolation High Common-Mode Voltage Difference Amplifier AD9 FUTIONAL BLOCK DIAGRAM -Lead Plastic Mini-DIP (N) and SOIC (R) Packages.k k AD9 GENERAL DESCRIPTION The AD9 is a difference amplifier with a very high input common-mode voltage range. It is a precision device that allows the user to accurately measure differential signals in the presence of high common-mode voltages up to ± V. The AD9 can replace costly isolation amplifiers in applications that do not require galvanic isolation. The device will operate over a ± V common-mode voltage range and has inputs that are protected from common-mode or differential mode transients up to ± V. The AD9 has low offset, low offset drift, low gain error drift, as well as low common-mode rejection drift, and excellent CMRR over a wide frequency range. The AD9 is available in low-cost, plastic -lead DIP and SOIC packages. For all packages and grades, performance is guaranteed over the entire industrial temperature range from C to + C. COMMON-MODE REJECTION RATIO db 9 9 ERROR mv/div mv/div V/DIV k k k FREQUEY Hz Figure. Common-Mode Rejection Ratio vs. Frequency COMMON-MODE VOLTAGE Volts Figure. Common-Mode Operating Range. Error Voltage vs. Input Common-Mode Voltage Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: /9- World Wide Web Site: Fax: /- Analog Devices, Inc.,

2 AD9 SPECIFICATIONS AD9A AD9B Parameter Condition Min Typ Max Min Typ Max Unit GAIN = ± V, R L = kω Nominal Gain V/V Gain Error.... % Gain Nonlinearity ppm R L = kω ppm Gain vs. Temperature T A = T MIN to T MAX ppm/ C OFFSET VOLTAGE Offset Voltage... mv V S = ± V mv vs. Temperature T A = T MIN to T MAX µv/ C vs. Supply (PSRR) V S = ± V to ± V 9 db INPUT Common-Mode Rejection Ratio V CM = ± V dc 9 db T A = T MIN to T MAX db V CM = V p-p DC to Hz db V CM = V p-p DC to khz 9 db Operating Voltage Range Common-Mode ± ± V Differential ± ± V Input Operating Impedance Common-Mode kω Differential kω Operating Voltage Range R L = kω ± ± V R L = kω ±. ±. V V S = ± V, R L = kω ± ± V Output Short Circuit Current ± ± ma Capacitive Load Stable Operation pf DYNAMIC RESPONSE Small Signal db Bandwidth khz Slew Rate.... V/µs Full Power Bandwidth = V p-p khz Settling Time.%, = V Step µs.%, = V Step µs.%, V CM = V Step, V DIFF = V µs NOISE VOLTAGE. Hz to Hz µv p-p Spectral Density, Hz nv/ Hz POWER SUPPLY Operating Voltage Range ±. ± ±. ± V Quiescent Current = V.9.9 ma T MIN to T MAX.. ma TEMPERATURE RANGE For Specified Performance T A = T MIN to T MAX + + C NOTES See Figure 9. Specifications subject to change without notice. (T A = C, V S = V unless otherwise noted)

3 ABSOLUTE MAXIMUM RATINGS Supply Voltage V S ± V Internal Power Dissipation DIP (N) See Derating Curves SOIC (R) See Derating Curves Input Voltage Range, Continuous ± V Common-Mode and Differential, sec ± V Output Short Circuit Duration Indefinite Pin, Pin V to +. V Maximum Junction Temperature C Operating Temperature Range C to + C Storage Temperature Range C to + C Lead Temperature Range (Soldering sec) C NOTES Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may effect device reliability. Specification is for device in free air: -Lead Plastic DIP, θ JA = C/W; -Lead SOIC Package, θ JA = C/W. MAXIMUM POWER DISSIPATION Watts.... -LEAD MINI-DIP PACKAGE -LEAD SOIC PACKAGE T J = C 9 AMBIENT TEMPERATURE C Figure. Derating Curve of Maximum Power Dissipation vs. Temperature for SOIC and PDIP Packages ORDERING GUIDE AD9 THEORY OF OPERATION The AD9 is a unity gain differential-to-single-ended amplifier (Diff Amp) that can reject extremely high common-mode signals (in excess of V with V supplies). It consists of an operational amplifier (Op Amp) and a resistor network. In order to achieve high common-mode voltage range, an internal resistor divider (Pin, Pin ) attenuates the noninverting signal by a factor of. Other internal resistors (Pin, Pin, and the feedback resistor) restores the gain to provide a differential gain of unity. The complete transfer function equals: = V () V () Laser wafer trimming provides resistor matching so that commonmode signals are rejected while differential input signals are amplified. The op amp itself, in order to reduce output drift, uses super beta transistors in its input stage The input offset current and its associated temperature coefficient contribute no appreciable output voltage offset or drift. This has the added benefit of reducing voltage noise because the corner where /f noise becomes dominant is below Hz. In order to reduce the dependence of gain accuracy on the op amp, the open-loop voltage gain of the op amp exceeds million, and the PSRR exceeds db..k k AD9 Figure. Functional Block Diagram Temperature Package Package Model Range Description Option AD9AR C to + C -Lead Plastic SOIC SO- AD9AR-REEL C to + C -Lead Plastic SOIC SO- AD9AR-REEL C to + C -Lead Plastic SOIC SO- AD9BR C to + C -Lead Plastic SOIC SO- AD9BR-REEL C to + C -Lead Plastic SOIC SO- AD9BR-REEL C to + C -Lead Plastic SOIC SO- AD9AN C to + C -Lead Plastic DIP N- AD9BN C to + C -Lead Plastic DIP N- NOTES " Tape and Reel of each " Tape and Reel of each CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE

4 AD9 Typical Performance Characteristics C, V S = V unless otherwise noted) COMMON-MODE REJECTION RATIO db 9 k k k M M FREQUEY Hz Figure. Common-Mode Rejection Ratio vs. Frequency COMMON-MODE VOLTAGE Volts T A = + C T A = + C T A = C POWER SUPPLY VOLTAGE Volts Figure. Common-Mode Operating Range vs. Power Supply Voltage mv/div R L = k R L = k V S = V V S = V ERROR mv/div V S = V V S = V ERROR mv/div V S = V V S = V V S = V V/DIV V S = V V/DIV Volts Figure. Typical Gain Error = V and Output Voltage Operating Range vs. Supply Voltage, R L = kω (Curves Offset for Clarity) Volts Figure 9. Typical Gain Error = V and Output Voltage Operating Range vs. Supply Voltage, R L = kω (Curves Offset for Clarity) R L = k V S = V V S = V, R L = k ERROR mv/div V S = V V S = V ERROR mv/div V S = V, R L = k V S = V, R L = k V S = V V/DIV V S =.V, R L = k V/DIV Volts Figure. Typical Gain Error = V and Output Voltage Operating Range vs. Supply Voltage, R L = kω (Curves Offset for Clarity) Volts Figure. Typical Gain Error = V and Output Voltage Operating Range vs. Supply Voltage (Curves Offset for Clarity)

5 AD9 ERROR.ppm/DIV ERROR ppm/div Volts Figure. Gain Nonlinearity; V S = ± V, R L = kω Volts Figure. Gain Nonlinearity; V S = ± V, R L = kω... C C ERROR ppm/div Volts VOLTAGE Volts. V S = V + C + C C + C. + C. CURRENT ma Figure. Gain Nonlinearity; V S = ± V, R L = kω Figure. Output Voltage Operating Range vs. Output Current; V S = ± V. + C. 9. C C ERROR.ppm/DIV VOLTAGE Volts V S = V C + C + C + C Volts Figure. Gain Nonlinearity; V S = ± V, R L = kω. + C. CURRENT ma Figure. Output Voltage Operating Range vs. Output Current; V S = ± V

6 AD9. + C VOLTAGE Volts C C V S = V + C + C C + C + C R L = k C L = pf. + C + C. CURRENT ma Figure. Output Voltage Operating Range vs. Output Current; V S = ± V mv/div s/div Figure. Small Signal Pulse Response; G =, R L = kω POWER SUPPLY REJECTION RATIO db 9 mv/div R L = k C L = pf s/div. k k FREQUEY Hz Figure. Power Supply Rejection Ratio vs. Frequency Figure. Small Signal Pulse Response; G =, R L = kω, C L = pf.... G = + R L = k C L = pf. V/ Hz..... V/DIV s/div.. k k k FREQUEY Hz Figure 9. Voltage Noise Spectral Density vs. Frequency Figure. Large Signal Pulse Response; G =, R L = kω, C L = pf

7 AD9 V/DIV V/DIV +V V V V ERROR mv =.% ERROR mv =.% mv/div s/div mv/div s/div Figure. Settling Time to.%, For V to V Output Step; G =, R L = kω Figure. Settling Time to.% for V to V Output Step; G =, R L = kω N = n PCS. FROM ASSEMBLY LOTS N = n PCS. FROM ASSEMBLY LOTS NUMBER OF UNITS NUMBER OF UNITS COMMON-MODE REJECTION RATIO ppm Figure. Typical Distribution of Common-Mode Rejection; Package Option N- 9 9 OFFSET VOLTAGE V Figure. Typical Distribution of Offset Voltage; Package Option N- N = n PCS. FROM ASSEMBLY LOTS N = n PCS. FROM ASSEMBLY LOTS NUMBER OF UNITS NUMBER OF UNITS GAIN ERROR ppm Figure. Typical Distribution of Gain Error; Package Option N- + GAIN ERROR ppm Figure. Typical Distribution of + Gain Error; Package Option N-

8 AD9 APPLICATIONS Basic Connections Figure 9 shows the basic connections for operating the AD9 with a dual supply. A supply voltage of between ± V and ± V is applied between Pins and. Both supplies should be decoupled close to the pins using. µf capacitors. µf electrolytic capacitors, also located close to the supply pins, may also be required if low frequency noise is present on the power supply. While multiple amplifiers can be decoupled by a single set of µf capacitors, each in amp should have its own set of. µf capacitors so that the decoupling point can be located physically close to the power pins. I SHUNT R SHUNT V REF.k AD9 V X V Y k = V REF I SHUNT (SEE TEXT) R SHUNT.k AD9 k V TO V V TO V (SEE TEXT) = I SHUNT R SHUNT Figure. Operation with a Single Supply Applying a reference voltage to and and operating on a single supply will reduce the input common-mode range of the AD9. The new input common-mode range depends upon the voltage at the inverting and noninverting inputs of the internal operational amplifier, labeled V X and V Y in Figure. These nodes can swing to within V of either rail. So for a (single) supply voltage of V, V X and V Y can range between V and 9 V. If V REF is set to V, the permissible common-mode range is + V to V. The common-mode voltage ranges can be calculated using the following equation. Figure 9. Basic Connections The differential input signal, which will typically result from a load current flowing through a small shunt resistor, is applied to Pins and with the polarity shown in order to obtain a positive gain. The common-mode range on the differential input signal can range from V to + V and the maximum differential range is ± V. When configured as shown, the device operates as a simple gain-of-one differential-to-single-ended amplifier, the output voltage being the shunt resistance times the shunt current. The output is measured with respect to Pins and. Pins and ( and ) should be grounded for a gain of unity and should be connected to the same low impedance ground plane. Failure to do this will result in degraded common-mode rejection. Pin is a no connect pin and should be left open. Single Supply Operation Figure shows the connections for operating the AD9 with a single supply. Because the output can swing to within only about V of either rail, it is necessary to apply an offset to the output. This can be conveniently done by connecting and to a low impedance reference voltage (some analogto-digital converters provide this voltage as an output), which is capable of sinking current. Thus, for a single supply of V, V REF might be set to V for a bipolar input signal. This would allow the output to swing ± V around the central V reference voltage. Alternatively, for unipolar input signals, V REF could be set to about V, allowing the output to swing from + V (for a V input) to within V of the positive rail. ( ) = ( ± ) V ± V 9V CM X / Y REF System-Level Decoupling and Grounding The use of ground planes is recommended to minimize the impedance of ground returns (and hence the size of dc errors). Figure shows how to work with grounding in a mixed-signal environment, that is, with digital and analog signals present. In order to isolate low-level analog signals from a noisy digital environment, many data-acquisition components have separate analog and digital ground returns. All ground pins from mixedsignal components such as analog-to-digital converters should be returned through the high quality analog ground plane. This includes the digital ground lines of mixed-signal converters that should also be connected to the analog ground plane. This may seem to break the rule of keeping analog and digital grounds separate, but in general, there is also a requirement to keep the voltage difference between digital and analog grounds on a converter as small as possible (typically <. V). The increased noise, caused by the converter s digital return currents flowing through the analog ground plane, will typically be negligible. Maximum isolation between analog and digital is achieved by connecting the ground planes back at the supplies. Note that Figure, as drawn, suggests a star ground system for the analog circuitry, with all ground lines being connected, in this case, to the ADC s analog ground. However, when ground planes are used, it is sufficient to connect ground pins to the nearest point on the low impedance ground plane.

9 AD9 AD9 ANALOG POWER SUPPLY DIGITAL POWER SUPPLY V +V GND GND +V V DD V IN V IN AGND DGND AD9- GND V DD PROCESSOR Figure. Optimal Grounding Practice for a Bipolar Supply Environment with Separate Analog and Digital Supplies POWER SUPPLY +V GND shows some sample error voltages generated by a common-mode voltage of V dc with shunt resistors from Ω to Ω. Assuming that the shunt resistor has been selected to utilize the full ± V output swing of the AD9, the error voltage becomes quite significant as R SHUNT increases. Table I. Error Resulting from Large Values of R SHUNT (Uncompensated Circuit) R S ( ) Error (V) Error Indicated (ma) If it is desired to measure low current or current near zero in a high common-mode environment, an external resistor equal to the shunt resistor value may be added to the low impedance side of the shunt resistor as shown in Figure..k AD9 V DD AGND DGND V DD GND AD9 V IN ADC PROCESSOR V REF I SHUNT R COMP R SHUNT Figure. Optimal Ground Practice in a Single Supply Environment If there is only a single power supply available, it must be shared by both digital and analog circuitry. Figure shows how to minimize interference between the digital and analog circuitry. In this example, the ADC s reference is used to drive the AD9 s and pins. This means that the reference must be capable of sourcing and sinking a current equal to V CM / kω. As in the previous case, separate analog and digital ground planes should be used (reasonably thick traces can be used as an alternative to a digital ground plane). These ground planes should be connected at the power supply s ground pin. Separate traces (or power planes) should be run from the power supply to the supply pins of the digital and analog circuits. Ideally, each device should have its own power supply trace, but these can be shared by a number of devices as long as a single trace is not used to route current to both digital and analog circuitry. Using a Large Sense Resistor Insertion of a large shunt resistance across the input Pins and will imbalance the input resistor network, introducing a commonmode error. The magnitude of the error will depend on the common-mode voltage and the magnitude of R SHUNT. Table I k Figure. Compensating for Large Sense Resistors Output Filtering A simple -pole low-pass Butterworth filter can be implemented using the OP at the output of the AD9 to limit noise at the output, as shown in Figure. Table II gives recommended component values for various corner frequencies, along with the peak-to-peak output noise for each case..k AD9 k OP Figure. Filtering of Output Noise Using a -Pole Butterworth Filter R C R C Table II. Recommended Values for -Pole Butterworth Filter Corner Frequency R R C C Output Noise (p-p) No Filter. mv khz.9 kω ± %. kω ± %. nf ± % nf ± % mv khz.9 kω ± %. kω ± % nf ± % nf ± %. mv Hz.9 kω ± %. kω ± % nf ± %. µf ± % µv Hz. kω ± %. kω ± %. µf ± % µf ± % µv 9

10 AD9 Output Current and Buffering The AD9 is designed to drive loads of kω to within V of the rails, but can deliver higher output currents at lower output voltages (see Figure ). If higher output current is required, the AD9 s output should be buffered with a precision op amp such as the OP as shown in Figure. This op amp can swing to within V of either rail while driving a load as small as Ω. THERMOCOUPLE V REF.k AD9 k.k AD9 k OP Figure. Output Buffering Application A Gain of 9 Differential Amplifier While low level signals can be connected directly to the and inputs of the AD9, differential input signals can also be connected as shown in Figure to give a precise gain of 9. However, large common-mode voltages are no longer permissible. Cold junction compensation can be implemented using a temperature sensor such as the AD9. Figure. A Gain of 9 Thermocouple Amplifier Error Budget Analysis Example In the dc application below, the A output current from a device with a high common-mode voltage (such as a power supply or current-mode amplifier) is sensed across a Ω shunt resistor (Figure ). The common-mode voltage is V, and the resistor terminals are connected through a long pair of lead wires located in a high-noise environment, for example, Hz/ Hz V ac power lines. The calculations in Table III assume an induced noise level of V at Hz on the leads, in addition to a full-scale dc differential voltage of V. The error budget table quantifies the contribution of each error source. Note that the dominant error source in this example is due to the dc common-mode voltage. Table III. AD9 vs. INA Error Budget Analysis Example (V CM = V dc) Error, ppm of FS Error Source AD9 INA AD9 INA ACCURACY, T A = C Initial Gain Error (. ) V (. ) V Offset Voltage (. V V) (. V V) DC CMR (Over Temperature) ( - V) V ( - V) V,, Total Accuracy Error:,, TEMPERATURE DRIFT ( C) Gain ppm/ C C ppm/ C C Offset Voltage ( µv/ C C) / V ( µv/ C C) / V Total Drift Error: RESOLUTION Noise, Typ,. Hz, µv p-p µv V µv V CMR, Hz ( V) V ( V) V Nonlinearity ( V) V ( V) V Total Resolution Error: Total Error:,,

11 AD9 CURRENT SHUNT AMPS V CM DC TO GROUND Hz POWER LINE.k AD9 k Figure. Error Budget Analysis Example. V IN = V Full-Scale, V CM = V DC. R SHUNT = Ω, V p-p Hz Power-Line Interference Error Budget Analysis Example This application is similar to the previous example except that the sensed load current is from an amplifier with an ac commonmode component of ± V (frequency = Hz) present on the shunt (Figure ). All other conditions are the same as before. Note that the same kind of power line interference can happen as detailed in Example. However, the ac commonmode component of V p-p coming from the shunt is much larger than the interference of V p-p, so that this interference component can be neglected. CURRENT SHUNT AMPS V AC CM TO GROUND Hz POWER LINE.k AD9 k Figure. Error Budget Analysis Example. V IN = V Full-Scale, V CM = ± V at Hz, R SHUNT = Ω Table IV. AD9 vs. INA AC Error Budget Example (V CM = Hz) Error, ppm of FS Error Source AD9 INA AD9 INA ACCURACY, T A = C Initial Gain Error (. ) V (. ) V Offset Voltage (. V V) (. V V) Total Accuracy Error: TEMPERATURE DRIFT ( C) Gain ppm/ C C ppm/ C C Offset Voltage ( µv/ C C) / V ( µv/ C C) / V Total Drift Error: RESOLUTION Noise, Typ,. Hz, µv p-p µv V µv V Hz ( V) V ( V) V Nonlinearity ( V) V ( V) V AC Hz ( V) V ( V) V,, Total Resolution Error:,, Total Error:,,

12 AD9 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). -Lead Plastic DIP (N-) -Lead SOIC (SO-) PIN. (.) MAX. (.). (.9). (.9). (.). (.). (.). (.) BSC. (.). (.). (.). (.). (.). (.). (.) MIN SEATING PLANE. (.). (.).9 (.9). (.9). (.). (.). (.).9 (.) PIN.9 (.). (.) SEATING PLANE.9 (.).9 (.). (.) BSC.9 (.9). (.). (.). (.). (.). (.).9 (.). (.9).9 (.).99 (.). (.). (.) Ca / (rev. A) PRINTED IN U.S.A.