High IMR, Low Cost ISOLATION AMPLIFIER

Transcription

1 49% FPO ISO High IMR, Low Cost ISOLATION AMPLIFIER FEATURES HIGH ISOLATION-MODE REJECTION: kv/µs (min) LARGE SIGNAL BANDWIDTH: 85kHz (typ) DIFFERENTIAL INPUT/DIFFERENTIAL OUTPUT VOLTAGE OFFSET DRIFT vs TEMPERATURE: 4.6µV/ C (typ) OFFSET VOLTAGE.8mV (max) INPUT REFERRED NOISE: µvrms (typ) NONLINEARITY:.5% (max) SINGLE SUPPLY OPERATION SIGMA-DELTA A/D CONVERTER TECHNOLOGY WORLDWIDE SAFETY APPROVAL: UL577 (File No. E657), VDE884 (File No. 855), CSA. (File No. 884) AVAILABLE IN 8-PIN PLASTIC DIP and 8-PIN GULL-WING PLASTIC SURFACE MOUNT V S V IN+ V IN 4 GND IMR SHIELD 8 V S 7 V OUT+ 6 V OUT 5 GND APPLICATIONS MOTOR AND SCR CONTROL MOTOR PHASE CURRENT SENSING INDUSTRIAL PROCESS CONTROL: Transducer Isolator, Isolator for Thermocouples, RTDs GENERAL PURPOSE ANALOG SIGNAL ISOLATION POWER MONITORING GROUND LOOP ELIMINATION DESCRIPTION The ISO is a high isolation-mode rejection, isolation amplifier suited for motor control applications. Its versatile design provides the precision and stability needed to accurately monitor motor currents in highnoise motor control environments. The ISO can also be used for general analog signal isolation applications requiring stability and linearity under severe noise conditions. The signal is transmitted digitally across the isolation barrier optically, using a high-speed AlGaAs LED. The remainder of the ISO is fabricated on µm CMOS IC process. A sigma-delta analog-to-digital converter, chopper stabilized amplifiers and differential input and output topologies make the isolation amplifier suitable for a variety of applications. The ISO is easy to use. No external components are required for operation. The key specifications are kv/µs isolation-mode rejection, 85kHz large signal bandwidth, and 4.6µV/ C V OS drift. A single power supply ranging from +4.5V to +5.5V makes this amplifier ideal for low power isolation applications. The ISO is available in 8-pin plastic DIP and 8-pin plastic gull-wing surface mount packages. International Airport Industrial Park Mailing Address: PO Box 4 Tucson, AZ 8574 Street Address: 67 S. Tucson Blvd. Tucson, AZ 8576 Tel: (5) 746- Twx: Cable: BBRCORP Telex: FAX: (5) Immediate Product Info: (8) Burr-Brown Corporation PDS-4B Printed in U.S.A. June, 995

2 SPECIFICATIONS ISOLATION SPECIFICATIONS VDE884 INSULATION CHARACTERISTICS At V IN, V IN = V, T A = 5 C, V S, V S = 5.V unless otherwise noted. ISOP/ISOPB ISOU/ISOUB PARAMETER CONDITIONS CHARACTERISTIC UNITS ISOLATION CHARACTERISTICS Installation Classification As Per VDE9/.8 Table I Rated Mains Voltage Vrms I-IV Rated Mains Voltage 6Vrms I-III Climatic Classification 4/85/ Pollution Degree () As Per VDE9/.8 Maximum Working Insulation Voltage (V IORM ) 6 Vrms Side A to Side B Test Voltage, Method b (V PR ) (9) Partial Discharge < 5pC V PR =.6 x V IORM, t P = s 96 Vrms Side A to Side B Test Voltage, Method a (V PR ) (9) Type and Sample Test Partial Discharge < 5pC V PR =. x V IORM, t P = 6s 7 Vrms Highest Allowable Overvoltage (V TR ) (9) Transient Overvoltage, t TR = s 6 V PEAK Safety-Limiting Values Case Temperature (T SI ) 75 C Input Power (P SI (INPUT) ) 8 mw Output Power (P SI (OUTPUT) ) 5 mw INSULATION RELATED SPECIFICATIONS Min. External Air Gap (clearance) > 7 mm Min. External Tracking Path (creepage) 8 mm Internal Isolation Gap (clearance).5 mm Tracking Resistance (CTI) 75 V Isolation Group per VDE9 III a Insulation Resistance 5 C, V ISO = 5V Ω SPECIFICATIONS ISOLATION SPECIFICATIONS At V IN +, V IN = V, T A = 5 C, V S, V S = 5.V, unless otherwise noted. ISOP, ISOPB ISOU, ISOUP PARAMETER CONDITIONS MIN TYP MAX UNITS ISOLATION Input-Output Surge Withstand Voltage (8, 9), t = MIN, RH 5% (In accordance with UL577) 75 Vrms Barrier Impedance (9) Resistance V ISO = 5VDC Ω Capacitance f = MHz.7 pf Isolation Mode Voltage Errors Rising Edge Transient Immunity V IM = kv, V OUT < 5mV 5 kv/µs Falling Edge Transient Immunity V IM = kv, V OUT < 5mV 5 kv/µs Isolation Mode Rejection Ratio () > 4 db ISO

3 SPECIFICATIONS At V IN +, V IN = V, T A = 5 C, V S, V S = 5.V unless otherwise noted. ISOP/ISOPB ISOU/ISOUB PARAMETER CONDITIONS MIN TYP MAX UNITS INPUT Initial Offset Voltage.8.9. mv vs Temperature 4.6 µv/ C vs V S µv/v vs V S 4 µv/v Power Supply Rejection; V S and V S Together MHz Square Wave, 5ns Rise/Fall Time 5 mv/v Noise.Hz to khz µvrms Input Voltage Range mv Maximum Input Voltage Range before Output Clipping ± mv Initial Input Bias Current () 67 na vs Temperature na/ C Input Resistance () 5 kω vs Temperature.8 %/ C Common-Mode Rejection Ratio (4) 7 db GAIN (5) Initial Gain ISOP/ISOU mv < V IN + < mv V/V ISOPB/ISOUB mv < V IN + < mv V/V Gain vs Temperature ppm/ C Gain vs V S. ppm/mv Gain vs V S.6 ppm/mv Gain Nonlinearity for mv < V IN + < mv..5 % for mv < V IN + < mv..5 % vs Temperature (6) mv < V IN + < mv. % pts/ C vs V (6) S mv < V IN + < mv.5 % pts/v vs V (6) S mv < V IN + < mv.7 % pts/v OUTPUT Voltage Range High V IN + = +5mV.6 V Low V IN + = 5mV.8 V Common-Mode Voltage 4 C < T A < 85 C, 4.5V < V S < 5.5V..9.6 V Current Drive (7) ma Short-Circuit Current V OUT = V or V OUT = V S 9. ma Output Resistance Ω vs Temperature.6 %/ C FREQUENCY RESPONSE Bandwidth db 4 C to 85 C 5 85 khz 45 5 khz Rise/Fall Time (% - 9%) 4 C to 85 C µs Propagation Delay to % 4 C to 85 C.. µs to 5% 4 C to 85 C µs to 9% 4 C to 85 C µs POWER SUPPLIES Rated Voltage 5. V Voltage Range V Quiescent Current V S V IN + = mv, 4 C < T A < 85 C, 4.5V < V S < 5.5V ma V S 4 C < T A < 85 C, 4.5V < V S < 5.5V ma TEMPERATURE RANGE Specification 4 85 C Operating 4 C Storage 55 5 C θ C A 86 C/W NOTES: () This part may also be used in Pollution Degree environments where the rated mains voltage is Vrms (per DIN VDE9/.8). () IMRR = log ( V IN / V ISO ). () Time averaged value. (4) V IN + = V IN = V CM. CMRR = log ( V CM / V OS ). (5) The slope of the best-fit line of (V OUT+ V OUT ) vs (V IN+ V IN ). (6) Change in nonlinearity vs temperature or supply voltage expressed in number of percentage points per C or volt. (7) For best offset voltage performance. (8) For devices with minimum V ISO specified at 75Vrms, each isolation amplifier is proof-tested by applying an insulation test voltage 45Vrms for second (leakage current < 5µA). This specification does not guarantee continuous operation. (9) Pins -4 are shorted together and pins 5-8 are shorted together for this test. ISO

4 PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Top View V S V IN V S V OUT + 8-Pin DIP/SOIC Supply Voltages: V S, V S... V to 5.5V Steady-State Input Voltage... V to V S +.5V Second Transient Input Voltage... 6.V Output Voltages: V OUT +, V OUT....5V to V S +.5V Lead Temperature Solder (.6mm below seating plane, s)... 6 C V IN GND V OUT GND ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE INFORMATION () PACKAGE DRAWING MODEL PACKAGE NUMBER ISOP 8-Pin Plastic DIP 6- ISOPB 8-Pin Plastic DIP 6- ISOU 8-Pin Gull-Wing Plastic Surface Mount 6- ISOUB 8-Pin Gull-Wing Plastic Surface Mount 6- NOTE: () For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. ORDERING INFORMATION GAIN ERROR MODEL PACKAGE (MAX) ISOP 8-Pin Plastic DIP ±5% (mean value = 8.) ISOPB 8-Pin Plastic DIP ±% (mean value = 7.9) ISOU 8-Pin Gull-Wing Plastic Surface Mount ±5% (mean value = 8.) ISOUB 8-Pin Gull-Wing Plastic Surface Mount ±% (mean value = 7.9) The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ISO 4

5 TYPICAL PERFORMANCE CURVES At T A = 5 C, V S, V S = 5.V DC, V IN +, V IN = V unless otherwise noted. db Bandwidth (khz) BANDWIDTH vs TEMPERATURE db Bandwidth Phase Bandwidth Phase Bandwidth (khz) Relative Amplitude (db) AMPLITUDE and PHASE RESPONSE vs FREQUENCY Amplitude 5 5 Phase k k k Phase (degrees) Temperature ( C) Frequency (Hz) PROPAGATION DELAYS and RISE/FALL TIME vs TEMPERATURE INPUT VOLTAGE NOISE vs INPUT VOLTAGE Time (µs) Delay to 9% Rise/Fall Time Delay to 5% Delay to % Input Voltage Noise (mvrms) Bandwidth Limited to khz No Bandwidth Limiting Bandwidth Limited to khz Temperature ( C) Input Voltage (mv) Input Offset Voltage Change (µv) INPUT OFFSET VOLTAGE CHANGE vs TEMPERATURE Input Offset Voltage Change (µv) INPUT OFFSET VOLTAGE CHANGE vs INPUT SUPPLY VOLTAGE V S = 5V Temperature ( C) Input Supply Voltage, V S (V) 5 ISO

6 TYPICAL PERFORMANCE CURVES (CONT) At T A = 5 C, V S, V S = 5.V DC, V IN +, V IN = V unless otherwise noted. Input Offset Voltage Change (µv) 4 INPUT OFFSET VOLTAGE CHANGE vs OUTPUT SUPPLY VOLTAGE σ V S = 5V IInput Current (ma) INPUT CURRENT vs INPUT VOLTAGE Output Supply Voltage, V S (V).5 GAIN DRIFT vs TEMPERATURE.5 GAIN CHANGE vs INPUT SUPPLY VOLTAGE Gain Drift (%).5 Gain Change (%).5 V S = 5V Temperature ( C) Input Supply Voltage, V S (V).5.4 GAIN CHANGE vs OUTPUT SUPPLY VOLTAGE V S = 5V.. NONLINEARITY ERROR vs INPUT VOLTAGE Gain Change (%)... % of Full-Scale Output Supply Voltage, V S (V) ISO 6

7 TYPICAL PERFORMANCE CURVES (CONT) At T A = 5 C, V S, V S = 5.V DC, V IN +, V IN = V unless otherwise noted. Nonlinearity Change (% pts) NONLINEARITY CHANGE vs TEMPERATURE Temperature ( C) Nonlinearity Change (% pts) NONLINEARITY CHANGE vs INPUT SUPPLY VOLTAGE Input Supply Voltage, V S (V) V S = 5V Non-Linearity Change (%PTS) NONLINEARITY CHANGE vs OUTPUT SUPPLY VOLTAGE V S = 5V Error -% of Full-Scale NONLINEARITY ERROR vs INPUT VOLTAGE.5.5. Output Supply Voltage, V S (V) 4 OUTPUT VOLTAGE vs INPUT VOLTAGE INPUT CURRENT vs INPUT VOLTAGE.5 Output Voltage (V).5 V OUT (Pin 6) V OUT+ (Pin 7) Input Current (na) ISO

8 TYPICAL PERFORMANCE CURVES (CONT) At T A = 5 C, V S, V S = 5.V DC, V IN +, V IN = V unless otherwise noted..5 INPUT SUPPLY CURRENT vs INPUT VOLTAGE OUTPUT SUPPLY CURRENT vs INPUT VOLTAGE Input Supply Current (ma) T A = 85 C T A = 4 C T A = 5 C Output Supply Current (ma).5.5 T A = 4 C T A = 5 C T A = 85 C P SI - INPUT POWER (mw) 5 5 DEPENDENCE OF SAFETY-LIMITING PARAMETERS ON AMBIENT TEMPERATURE 4 P SI - OUTPUT POWER (mw) Output Input +mv mv.6v LARGE SIGNAL SINUSOIDAL RESPONSE OF ISO Ambient Temperature ( C) µs/div +mv LARGE SIGNAL SQUARE WAVE RESPONSE OF ISO OVERLOAD RECOVERY OF ISO V IN = 5mV to, khz Square Wave Output Input mv.6v Output (V) µs/div µs/div ISO 8

9 THEORY OF OPERATION The ISO isolation amplifier (Figure ) uses an input and output section galvanically isolated by a high speed optical barrier built into the plastic package. The input signal is converted to a time averaged serial bit stream by use of a sigma-delta analog-to-digital converter and then optically transmitted digitally across the isolation barrier. The output section receives the digital signal and converts it to an analog voltage, which is then filtered to produce the final output signal. Internal amplifiers are chopper-stabilized to help maintain device accuracy over time and temperature. The encoder circuit eliminates the effects of pulse-width distortion of the optically transmitted data by generating one pulse for every edge of the converter data to be transmitted. This coding scheme reduces the effects of the non-ideal characteristics of the LED, such as non-linearity and drift over time and temperature. ISOLATION AND INSULATION SPECIFICATIONS The performance of the isolation barrier of the ISO is specified with three specifications, two of which require high voltage testing. In accordance with UL577, the barrier integrity of each isolation amplifier is proof-tested by applying an insulation test voltage greater than or equal to 45Vrms for one second. This is to guarantee the isolation amplifier will survive a 75V transient voltage. The barrier leakage current test limit is 5µA. Pins -4 are shorted together and pins 5-8 are shorted together during the test. This test is followed by the partial discharge isolation voltage test as specified in the German VDE884. This method requires the measurement of small current pulses (<5pico Colomb) while applying 96Vrms across every ISO isolation barrier. This guarantees 6Vrms continuous isolation (V ISO ) voltage. No partial discharge may be initiated to pass this test. This criterion confirms transient overvoltage (.6 x 6Vrms) protection without damage to the ISO. This test method represents state of the art for nondestructive high voltage reliability testing. It is based on the effects of nonuniform fields that exist in heterogeneous dielectric material during barrier degradation. In the case of void nonuniformities, electric field stress begins to ionize the void region before bridging the entire high voltage barrier. The transient conduction of charge during and after the ionization can be detected externally as a burst of. to.µs current pulses that repeat on each AC voltage cycle. The minimum AC barrier voltage that initiates partial discharge is defined as the inception voltage. Decreasing the barrier voltage to a lower level is required before partial discharge ceases and is defined as the extinction voltage. Voltage Regulator Clk Isolation Barrier Voltage Regulator Input Σ A/D and Encoder LED Drive Circuit Detector CIrcuit Decoder and D/A Filter Output FIGURE. Block Diagram of ISO Isolation Amplifier. pf 5.kΩ In 78L5 Out +5V +5V.µF.µF + 9V.µF.µF ISO 8 7 V OUT + kω kω OPA64 V OUT µF pf 5.kΩ Pulse Generator 5V + V IM FIGURE. Isolation Mode Rejection and Transient Immunity Test Circuit. 9 ISO

10 Both tests are % production tests. The partial discharge testing of the ISO is performed after the UL577 test criterion giving more confidence in the barrier reliability. The third guaranteed isolation specification for the ISO is Transient Immunity (TI), which specifies the minimum rate of rise or fall of an isolation mode noise signal at which small output perturbations begin to occur. An isolation mode signal is defined as a signal appearing between the isolated grounds, GND and GND. Isolation Mode Voltage (IMV) is the voltage appearing between isolated grounds. Under certain circumstances this voltage across the isolation barrier can induce errors at the output of the isolation amplifier. Figure shows the Transient Immunity Test Circuit for the ISO. In this test circuit a pulse generator is placed between the isolated grounds (GND and GND ). The inputs of the ISO are both tied to GND. A difference amplifier is used V IM V OUT V FIGURE. Typical Transient Immunity Failure Waveform. V 5mV Perturbation (Definition of Failure) V to gain the output signal of the ISO. A Transient Immunity failure is determined when the output of the ISO changes by more than 5mV as illustrated in Figure. Finally, Isolation Mode Rejection Ratio (typically >4dB for the ISO) is defined as the ratio of differential signal gain to the isolation mode gain at 6Hz. The magnitude of the 6Hz voltage across the isolation barrier during this test is not so large as to cause Transient Immunity errors. The Isolation Mode Rejection Ratio should not be confused with the Common Mode Rejection Ratio. The Common Mode Rejection Ratio defines the relationship of differential signal gain (signal applied differentially between pins and ) to the common mode gain (input pins tied together and the signal applied to both inputs at the same time). APPLICATIONS INFORMATION APPLICATION CIRCUITS Figure 4 illustrates a typical application for the ISO. In this motor control circuit, the current that is sent to the motor is sensed by the resistor, R SENSE. The voltage drop across this resistor is gained up by the ISO and then transmitted across the isolation barrier. A difference amplifier, A, is used to change the differential output signal of the ISO to a single ended signal. This voltage information is then sent to the control circuitry of the motor. The ISO is particularly well suited for this application because of its superior Transient Immunity (kv/µs, max) and its excellent immunity to RF noise. HV+ V+ In 78L5 Out +5V 5pF.µF.µF ISO 8.µF 7 V + OUT kω kω kω +5V 6 OPA64.µF pF kω 5V + R SENSE HV FIGURE 4. ISO Used to Monitor Motor Current. ISO

11 The current-sensing resistor should have a relatively low value of resistance (to minimize power dissipation), a fairly low inductance (to accurately reflect high-frequency signal components), and a reasonably tight tolerance (to maintain overall circuit accuracy). LAYOUT SUGGESTIONS. Bypass capacitors should be located as close as possible to the input and output power supply pins.. In some applications, offset voltage can be reduced by placing a.µf capacitor from pin and/or pin to GND. This noise can be caused by the combination of long input leads and the switched-capacitor nature of the input circuit. This capacitor(s) should be placed as close to the isolation amplifier as possible.. The trace lengths at input should be kept short or a twisted wire pair should be used to minimize EMI and inductance effects. For optimum performance, the input signal should be as close to the input pins a possible. 4. A maximum distance between the input and output sides of the isolation amplifier should be maintained in the layout in order to minimize stray capacitance. This practice will help obtain optimal Isolation Mode performance. Ground planes should not pass below the device on the PCB. 5. Care should be taken in selecting isolated power supplies or regulators. The ISO can be affected by changes in the power supply voltages. Carefully regulated power supplies are recommended. 6. For improved nonlinearity and nonlinearity temperature drift performance, pin should be tied to GND and the input voltage range of pin should be less than mv. ISO

12 PACKAGE DRAWINGS ISO