ACPL-C87AT/ACPL-C87BT Automotive High Precision DC Voltage Isolation Sensor. Features. Applications

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ACPL-CAT/ACPL-CBT Automotive High Precision DC Voltage Isolation Sensor Data Sheet Lead (Pb) Free RoHS fully compliant RoHS fully compliant options available; -xxxe denotes a lead-free product

1 ACPL-CAT/ACPL-CBT Automotive High Precision DC Voltage Isolation Sensor Data Sheet Lead (Pb) Free RoHS fully compliant RoHS fully compliant options available; -xxxe denotes a lead-free product Description The ACPL-CAT/CBT isolation sensors utilize superior optical coupling technology, with sigma-delta (S-D) analog-to-digital converter, chopper stabilized amplifiers, and a fully differential circuit topology to provide unequaled isolation-mode noise rejection, low offset, high gain accuracy and stability. ACPL-CAT (±1% gain tolerance) and ACPL-CBT (±.5% gain tolerance) are designed for high precision DC voltage sensing in electronic motor drives, DC/DC and AC/DC converter and battery monitoring system. The ACPL-CAT/CBT features high input impedance and operate with full span of analog input voltage up to. V. The shutdown feature provides power saving and can be controlled from external source, such as microprocessor. The high common-mode transient immunity (15 kv/µs) of the ACPL-CAT/CBT maintains the precision and stability needed to accurately monitor DC rail voltage in high noise motor control environments. This galvanic safe isolation solution is delivered in a compact, surface mount stretched SO- (SSO-) package that meets worldwide regulatory safety standards. Avago R Coupler isolation products provide the reinforced insulation and reliability needed for critical automotive and high temperature industrial applications. Functional Diagram V DD1 V IN SHDN 1 3 V DD V OUT+ V OUT- Features Unity Gain +/-.5% (ACPL-CBT) and +/-1% (ACPL-CAT) Gain 5 C -.3 mv Input Offset Voltage.5% Non Linearity 5 ppm/ C Gain Drift vs. Temperature 1 khz Bandwidth to V Nominal Input Range Qualified to AEC-Q1 Grade 1 Test Guidelines Operating Temperature: - C to +15 C Shutdown Feature (Active High) 15 kv/ms Common-Mode Rejection at V CM = 1 kv Working Voltage, V IORM = 11 V peak Compact, Surface Mount Stretched SO Package Worldwide Safety Approval: UL 15 (5 V RMS / 1 min.) CSA IEC/EN/DIN EN -5-5 Applications Automotive BMS Battery Pack Voltage Sensing Automotive DC/DC Converter Voltage Sensing Automotive Motor Inverter DC Bus Voltage Sensing Automotive AC/DC (Charger) DC Output Voltage Sensing Isolation Interface for Temperature Sensing General Purpose Voltage Sensing and Monitoring GND1 Figure 1. Functional Diagram 5 SHIELD GND.1 mf bypass capacitor must be connected between pin 1 and pin, and pin 5 and pin as shown. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.

2 Functional Diagram (Cont.) V DD1 V DD V IN V OUT = V OUT+ V OUT- V V IN SHDN V OUT+ V OUT- V Isolation GND1 Figure. Functional Diagram GND 15 V 5 V V+ Gate Driver MEV1S155DC IN OUT 5 V V- M Gate Driver R1 R 39 Ω 1 nf ACPL-CAT/BT R kω R5 kω 1 nf 1 nf kω kω V OUT Figure 3. Typical Voltage Sensing Circuit 1 VDD1 VDD VIN V OUT+ 3 SHDN V OUT- GND1 GND 5 Figure. Package Pinout Pin Description Pin No. Pin Name Description Pin No. Pin Name Description 1 V DD1 Input power supply When V DD1 =, then V OUT+ = V, V OUT- =. V V DD Output power supply V IN Voltage input, Full scale Range =. V V OUT+ Positive output voltage 3 SHDN Shutdown (Active High) When active, then V OUT+ = V, V OUT- =. V V OUT- Negative output voltage GND1 Input Side Ground 5 GND Output Side Ground

3 Ordering Information Part number ACPL-CAT ACPL-CBT Option (RoHS Compliant) Package Surface Mount Tape & Reel UL 5 V rms / 1 Minute rating IEC/EN/DIN EN -5-5 Quantity -E Stetched X X X per tube -5E SO- X X X X 1 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example: ACPL-CAT-5E to order product of SSO- Surface Mount package in Tape and Reel packaging with RoHS compliant. Contact your Avago sales representative or authorized distributor for information. Package Outline Drawing (Stretched SO) RECOMMENDED LAND PATTERN 5.5 ±.5 (.3 ±.1) PART NUMBER RoHS-COMPLIANCE INDICATOR CBT YWW EE DATE CODE. ±.1 (. ±.5) EXTENDED DATECODE FOR LOT TRACKING 3.1 ±.1 (.15 ±.5).5 (.1) 1.95 (.5) 5. (.5) 1.5 (.9) 1.59 ±.1 (.3 ±.5).31 ±.1 (.15 ±.5) 1. (.5) BSG. ±.1 (. ±.).5 ±.5 (.95 ±.1) 11.5 ±.5 (.53 ±.1).5 ±.1 (.1 ±.) Dimensions in millimeters and (inches). Figure 5. Package Outline Drawing Note: Lead coplanarity =.1 mm (. inches). Floating lead protrusion =.5mm (1mils) max. 3

4 Recommended Pb-Free IR Profile Recommended reflow condition as per JEDEC Standard, J-STD- (latest revision). Note: Non-halide flux should be used Regulatory Information The ACPL-CAT and ACPL-CBT are approved by the following organizations: UL CSA IEC/EN/DIN EN -5-5 UL 15, component recognition program up to V ISO = 5kV RMS Approved under CSA Component Acceptance Notice #5. IEC -5-5 EN -5-5 DIN EN -5-5 IEC/EN/DIN EN -5-5 Insulation Characteristics Description Symbol Units Installation classification per DIN VDE 11/1.9, Table 1 for rated mains voltage 15 Vrms for rated mains voltage 3 Vrms for rated mains voltage 5 Vrms for rated mains voltage Vrms for rated mains voltage 1 Vrms I IV I IV I - IV I - IV I - III Climatic Classification /15/1 Pollution Degree (DIN VDE 11/1.9) Maximum Working Insulation Voltage V IORM 11 Vpeak Input to Output Test Voltage, Method b V IORM X 1.5 = V PR, 1% Production Test with t m = 1 sec, Partial discharge < 5 pc Input to Output Test Voltage, Method a V IORM X 1. = V PR, Type and Sample Test with t m = 1 sec, Partial discharge < 5 pc Highest Allowable Overvoltage (Transient Overvoltage t ini = sec) Safety-limiting values maximum values allowed in the event of a failure, also see Figure. Case Temperature Input Current Output Power V PR 51 Vpeak V PR Vpeak V IOTM Vpeak Ts I S, INPUT P S,OUTPUT Insulation Resistance at T S, V IO = 5 V R S > 1 9 W 15 3 C ma mw OUTPUT POWER PS, INPUT CURRENT - IS T S CASE TEMPERATURE C Figure. Dependence of safety limiting values on temperature P S (mw) I S (mw)

5 Insulation and Safety Related Specifications Parameter Symbol Value Unit Conditions Minimum External Air Gap (External Clearance) Minimum External Tracking (External Creepage) Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group (DIN BDE19) L(11). mm Measured from input terminals to output terminals, shortest distance through air. L(1). mm Measured from input terminals to output terminals, shortest distance path along body..5 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. CTI > 15 Volts DIN IEC 11/VDE 33 Part 1 IIIa Material Group (DIN VDE 11) Absolute Maximum Ratings Parameter Symbol Min. Max. Units Note Storage Temperature T S C Ambient Operating Temperature T A - 15 C Supply Voltages V DD1, V DD -.5. Volts Input Voltage V IN -. V DD1 +.5 Volts Shutdown Voltage V SD -.5 V DD1 +.5 Volts Output Voltages V OUT+, V OUT- -.5 V DD +.5 Volts Recommended Operating Conditions Parameter Symbol Min. Max. Units Notes Ambient Operating Temperature T A - 15 C Input Supply Voltage V DD Volts Output Supply Voltage V DD Volts Input Voltage V IN. Volts Shutdown Voltage V SD V DD1.5 V DD1 Volts 5

6 Electrical Specifications Unless otherwise noted, all typical values at T A = 5 C, V DD1 = V DD = 5 V, V IN = to V, V SD = V; all Minimum/Maximum specifications are at recommended voltage supply conditions:.5v < V DD1 < 5.5V,.5V < V DD < 5.5V Parameter Symbol Min. Typ. Max. Unit Test Conditions Fig. Note POWER SUPPLIES Input Supply Current I DD ma V SD = V 1, 19 Input Supply Current (Shutdown Mode) I DD1(SD) ma V SD = 5 V Output Supply Current I DD.5 1 ma 1, DC CHARACTERISTICS Gain (ACPL-CBT, +/-.5%) Gain (ACPL-CAT, +/- 1%) Magnitude of Gain Change vs Temperature G V/V T A = 5 C, V IN = V, V DD1 = V DD = 5. V G V/V T A = 5 C, V IN = V, V DD1 = V DD = 5. V dg/dt A 5 ppm/ C T A = - C to +15 C 11 Magnitude of Gain dg/dv DD1.5 %/V T A = 5 C 1 Change vs V DD1 1, 11 1 Magnitude of Gain dg/dv DD. %/V T A = 5 C 1, 13 Change vs V DD Nonlinearity NL.5.1 % V IN = to V, T A = - C to +15 C Input Offset Voltage V OS mv V IN is shorted to GND1, T A = 5 C Magnitude of Input Offset Change vs. Temperature INPUTS AND OUTPUTS Full-Scale Differential Voltage Input Range dv OS /dt A 1 mv/ C V IN is shorted to GND1, T A = - C to +15 C FSR. V Referenced to GND1 Input Bias Current I IN ma V IN = V Equivalent Input Impedance Output Common-Mode Voltage R IN 1 MW V OCM 1.3 V V IN = V, V SD = V V OUT+ Range V OUT+ V OCM +1.3 V V IN =.5 V V OUT - Range V OUT- V OCM -1.3 V V IN =.5 V Output Short-Circuit Current I OSC 3 ma V OUT+ or V OUT-, shorted to GND or V DD Output Resistance R OUT 3 W V IN = V 15, 1, 9, 1, 9

7 Electrical Specifications (continued) Unless otherwise noted, all typical values at T A = 5 C, V DD1 = V DD = 5 V, V IN = to V, V SD = V; all Minimum/Maximum specifications are at recommended voltage supply conditions:.5v < V DD1 < 5.5V,.5V < V DD < 5.5V Parameter Symbol Min. Typ. Max. Unit Test Conditions Fig. Note AC CHARACTERISTICS Small-Signal Bandwidth (-3 db) f 3 db 1 khz V OUT Noise N OUT 1.3 mv RMS V IN = V; BW = 1 khz 3 5 Input to Output Propagation Delay (1%-1%) Input to Output Propagation Delay (5%-5%) Input to Output Propagation Delay (9%-9%) Output Rise / Fall Time (1%-9%) t PD ms V IN = to V Step 1, t PD5 3.. ms V IN = to V Step 1, t PD ms V IN = to V Step 1, t R/F.. ms Step Input Shutdown Time t SD 5 ms 5 Shutdown Recovery Time t ON 15 ms 5 Power Supply Rejection PSR - db 1 Vp-p, 1 khz sine wave ripple on V DD1, differential output Common Mode Transient Immunity CMTI 1 15 kv/μs V CM = 1 kv, T A = 5 C Package Characteristics Unless otherwise noted, all typical values are at T A = 5 C; all Minimum/Maximum specifications are at Recommended Operating Conditions. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Input-Output Momentary Withstand Voltage * V ISO 5 V RMS RH < 5%, t = 1 min., T A = 5 C Input-Output Resistance R I-O 1 1 W V I-O = 5 V DC 3 Input-Output Capacitance C I-O.5 pf f =1 MHz 3 * The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. Notes: 1. Gain is defined as the slope of the best-fit line of differential output voltage (V OUT+ - V OUT- ) versus input voltage over the nominal range, with offset error adjusted..5% Gain tolerance for ACPL-CBT and 1% tolerance for ACPL-CAT.. Common mode transient immunity (CMTI) is tested by applying a fast rising/falling voltage pulse across GND1 (pin ) and GND (pin 5). The output glitch observed is less than. V from the average output voltage for less than 1 ms. 3. Device considered a two terminal device: pins 1,, 3 and shorted together, and pins 5,, and shorted together.. In accordance with UL 15, each optocoupler is proof tested by applying an insulation test voltage > V RMS for 1 second. 5. Noise is measured at the output of the differential to single ended post amplifier. 3,

8 Typical Characteristic Plots and Test Conditions All ±3s plots are based on characterization test result at the point of product release. For guaranteed specification, refer to the respective Electrical Specifications section. VDD1 VDD VDD1 VDD 1 3 ACPL-CAT/BT 5 V VOLTMETER VIN 1 3 ACPL-CAT/BT 5 V VOLTMETER GND1 GND GND1 GND Figure. Input Offset Voltage Test Circuit Figure. Gain and Nonlinearity Test Circuit G - GAIN - V/V Vos - INPUT OFFSET VOLTAGE - mv T A - TEMPERATURE - C Figure 9. Input Offset Voltage vs Temperature MEAN +3 SIGMA.99-3 SIGMA T A - TEMPERATURE - C Figure 11. Gain vs Temperature +3 SIGMA MEAN -3 SIGMA Vos - INPUT OFFSET VOLTAGE - mv Figure 1. Input Offset vs Supply Voltage G - GAIN - V/V Figure 1. Gain vs Supply Voltage vs Vdd1 vs Vdd V DD - SUPPLY VOLTAGE - V vs Vdd1 vs Vdd V DD - SUPPLY VOLTAGE - V

9 G - GAIN - V/V T A - TEMPERATURE - C Figure 13. Gain vs Temperature at Different V DD VDD = 3.3 V VDD = 5 V VDD = 5.5 V NL - NON LINEARITY - %....5 Figure 1. Nonlinearity vs Supply Voltage vs Vdd1 vs Vdd V DD - SUPPLY VOLTAGE - V NL - NON LINEARITY - % MEAN +3 SIGMA -3 SIGMA T A - TEMPERATURE - C T A - TEMPERATURE - C Figure 15. Nonlinearity vs Temperature NL - NON LINEARITY - % Figure 1. Nonlinearity vs Temperature at Different V DD VDD = 3.3 V VDD = 5. V VDD = 5.5 V Vo - OUTPUT VOLTAGE - V VOUT+ VOUT- IDD - SUPPLY CURRENT - ma 1 1 IDD1 IDD V IN - INPUT VOLTAGE - V Figure 1. Output Voltage vs Input Voltage V IN - INPUT VOLTAGE - V Figure 1. Typical Supply Current vs Input Voltage. 9

10 IDD1 - INPUT SUPPLY CURRENT - ma V DD1 =.5 V V DD1 = 5. V V DD1 = 5.5 V T A - TEMPERATURE - C Figure 19. Typical Input Supply Current vs Temperature at Different V DD1 IDD - OUTPUT SUPPLY CURRENT - ma 9 5 V DD = 3.3 V V DD = 5. V V DD = 5.5 V T A - TEMPERATURE - C Figure. Typical Output Supply Current vs Temperature at Different V DD Tp - PROPAGATION DELAY - µs T PD 5-1 T PD 5-5 T PD T A - TEMPERATURE - C Figure 1. Typical Propagation Delay vs Temperature IIN - INPUT CURRENT - na V IN - INPUT VOLTAGE - V Figure. Input Current vs Input Voltage AC NOISE - mvrms 1 V 1 IN =. V FILTER BANDWIDTH - khz Figure 3. AC Noise vs Filter Bandwidth Phase (deg) Frequency (Hz) Figure. Phase vs Frequency 1

11 5 V 5 V 1 nf 39 Ω kω kω 1 nf kω V OUT ACPL-CAT/BT 1 nf kω + V CM Figure 5. Common Mode Transient Immunity Test Circuit V SHDN V IN 5 V V V V. V V OUT+ V OUTt SD t ON V -. V Figure. Shutdown Timing Diagram V V IN V V O+ V O- V 1 V 9% 5% V T PD1 T PD5 T PD9 Figure. Propagation Delay Diagram 1% 11

12 Application Information The circuit shown in the Figure is a high voltage sensing application using ACPL-CAT/BT (isolation amplifier) and ACPL-M9T (optocoupler). The high voltage input is sensed by the precision voltage divider resistors R1 and sensing resistor R. The ratio of the voltage divider is determined by the allowable input range of the isolation amplifier ( to V). This small analog input goes through a 39 W and 1 nf anti aliasing filter (ACPL-CAT/BT utilize SD modulation). Inside the isolation amplifier: the analog input signal is digitized and optically transmitted to the output side of the amplifier. The detector will then decode the signal and converted back to analog signal. The output differential signals of ACPL-CAT/BT go through an op-amp to convert the differential signals to a single ended output. SWITCH MODE POWER SUPPLY V+ Battery Cells 1 kω R1 Ω R13 C 1 nf V- R1 R R3 39 Ω C ACPL-M9T C R kω R5 kω R kω VOUT M C U C1 1 nf ACPL-CAT/BT C 1 nf R kω Vref Figure. Typical Application Circuit for Battery Voltage Sensing Bypass Capacitor.1 mf bypass capacitor must be connected as near as possible between V DD1 to GND1 and V DD to GND (Figure 9). Anti-aliasing Filter 39 W resistor and 1 nf capacitor are recommended to be connected to the input (V IN ) as anti-aliasing filter because ACPL-CAT/BT uses sigma data modulation (Figure 3). The value of the capacitor must be greater than 1 nf and bandwidth must be less than 1 khz. Fig 3. Anti aliasing Filter C1, R3 1 R3 39 Ω C1 1 nf ACPL-CAT/BT C ACPL-CAT/BT Fig 9. Bypass Capacitors C, C ACPL-CAT/BT R kω R5 kω Fig 31. Loading Resistors R, R5 C

13 Designing the input resistor divider 1. Choose the sensing current (Isense) for bus voltage. E.g., 1 ma. Determine R, Voltage input range R = = ISENSE V 1 ma = kω 3. Determine R1 using voltage divider formula: (V+ V-) R1 = R = Voltage input range, or R1 + R (V+ V-) R Voltage input range R where (V+ V-) is the high voltage input, E.g.: to V, R1 = ( V V) kω V kω = 59 kω To reduce the voltage stress of a sole resistor, R1 can be a series of several resistors. Post Amplifier Circuit Shutdown Function The output of ACPL-CAT/BT is a differential output (V OUT+ and V OUT- pins). A post amplifier circuit is needed to convert the differential output to single ended output with a reference ground. The post amplifier circuit can also be configured to establish a desired gain if needed. It also functions as filter to high frequency chopper noise. The bandwidth can be adjusted by changing the feedback resistor and capacitor (R and C). Adjusting this bandwidth to a minimum level helps minimize the output noise. Post op-amp resistive loading (R, R5) should be equal or greater than kw (Figure 31). Resistor values lower than this can affect the overall system error due to output impedance of isolation amplifier. The application circuit in Figure features two op-amps to improve the linearity at voltage near V caused by the limited headroom of the amplifier. The second op-amp can set the reference voltage to above V. ACPL-CAT/BT has a shutdown function to disable the device and make the output (V OUT+ - V OUT- ) low. A voltage of 5V on SHDN pin will shutdown the device producing an output (V OUT+ - V OUT- ) of -. V. To be able to control the SHDN function (example, from microprocessor), an optocoupler (ACPL-M9T) is used. Total System Error Total system error is the sum of the resistor divider error, isolation amplifier error and post amplifier error. The resistor divider error is due to the accuracy of the resistors used. It is recommended to use high accuracy resistor of.1%. Post Amplifier Error is due to the resistor matching and the voltage offset characteristic which can be found on the supplier datasheet. Isolation Amplifier Error is shown in the table below: Isolation Amplifier Error Calculation 13 Typical 3s distribution or specification * ACPL-CAT ACPL-CBT A Error due to offset voltage (5 C).15%.5%.5% Offset Voltage /Recommended input voltage range (. V) B Error due to offset voltage drift (across temperature).1%.%.% Offset Voltage /Recommended input voltage range (. V) C Error due to gain tolerance (5 C) % 1%.5% specs D Error due to gain drift (across temperature).5%.%.% E Error due to Nonlinearity (across temperature).5%.1%.1% F Total uncalibrated error (A+B+C+D+E).15%.%.3% specs G Total offset calibrated error (F A).%.3% 1.% H Total gain and offset calibrated error (G C).% 1.3% 1.3% * 3s distribution is based on corner wafers. Fig specs

If the design has multiple layers, a dedicated layer for ground is recommended for flexibility in component placement.

14 PCB Layout Recommendations Bypass capacitor C and C must be located close to ACPL-CxT Pins 1 and Pin respectively. Grounded pins of C and C5 can be connected by vias through the respective ground layers. If the design has multiple layers, a dedicated layer for ground is recommended for flexibility in component placement. Anti aliasing filters R3 and C1 also need to be connected as close as possible to Pin of ACPL-CAT/BT. See Figure 3 for actual component placement of the anti-aliasing filter and bypass capacitors. GND1 and GND must be totally isolated in the PCB layout (Figure 33). Distance of separation depends on the high voltage level of the equipment. The higher the voltage level the larger the distance of separation needed. Designers can refer to specific IEC standard of their equipment for the creepage/clearance requirements. R1 which is directly connected to the high voltage input must have sufficient clearance with the low voltage components. Clearance depends on the high voltage level of the input. Designers can refer to specific IEC standards of their equipment for the clearance requirements. BYPASS CAPACITORS R1 (Series Resistors) Isolation Clearance GND1 GND ANTI ALIASING FILTER ACPL-CAT/BT Figure 3. Component Placement Recommendation Figure 33. Bottom Layer Layout Recommendation For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright 5-13 Avago Technologies. All rights reserved. AV-353EN - August, 13

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